ICX434DQN Diagonal 5.68mm (Type 1/3.2) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras Description The ICX434DQN is a diagonal 5.68mm (Type 1/3.2) interline CCD solid-state image sensor with a square pixel array and 2.02M effective pixels. Frame readout allows all pixels' signals to be output independently within approximately 1/7.5 second. Also, the adoption of high frame rate readout mode supports 30 frames per second which is four times the speed in frame readout mode. This chip features an electronic shutter with variable charge-storage time. Adoption of a design specially suited for frame readout ensures a saturation signal level equivalent to when using field readout. High resolution and high color reproductivity are achieved through the use of R, G, B primary color mosaic filters. Further, high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology. This chip is suitable for applications such as electronic still cameras, PC input cameras, etc. 16 pin SOP (Plastic) AAAAA AAAAA AAAAA AAAAA AAAAA Pin 1 Features V • Supports frame readout • High horizontal and vertical resolution • Supports high frame rate readout mode: 30 frames/s • Square pixel 4 • Horizontal drive frequency: 18MHz 48 H Pin 9 • No voltage adjustments (reset gate and substrate bias are not adjusted.) • R, G, B primary color mosaic filters on chip Optical black position • High color reproductivity, high sensitivity, low smear • Continuous variable-speed shutter (Top View) • Low dark current, excellent anti-blooming characteristics • 16-pin high-precision plastic package (top/bottom dual surface reference possible) 2 10 Device Structure • Interline CCD image sensor • Image size: Diagonal 5.68mm (Type 1/3.2) • Total number of pixels: 1688 (H) × 1248 (V) approx. 2.11M pixels • Number of effective pixels: 1636 (H) × 1236 (V) approx. 2.02M pixels • Number of active pixels: 1620 (H) × 1220 (V) approx. 1.98M pixels • Chip size: 5.27mm (H) × 4.40mm (V) • Unit cell size: 2.8µm (H) × 2.8µm (V) • Optical black: Horizontal (H) direction: Front 4 pixels, rear 48 pixels Vertical (V) direction: Front 10 pixels, rear 2 pixels • Number of dummy bits: Horizontal 28 Vertical 1 (even fields only) • Substrate material: Silicon ∗Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (HoleAccumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony Corpration. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E02202 ICX434DQN GND Vφ1B Vφ1A Vφ2 Vφ3B Vφ3A Vφ4 8 7 6 5 4 3 2 1 Vertical register VOUT Block Diagram and Pin Configuration (Top View) G B G B R G R G G B G B R G R G G B G B R G R G Note) Horizontal register 12 13 GND φSUB CSUB VL 14 15 : Photo sensor 16 Hφ2 11 Hφ1 10 φRG 9 VDD Note) Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol Vφ4 Vφ3A Vφ3B Vφ2 Vφ1A Vφ1B GND VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Signal output Pin No. 9 10 11 12 13 14 15 16 Symbol VDD GND φSUB CSUB VL φRG Hφ1 Hφ2 Description Supply voltage GND Substrate clock Substrate bias∗1 Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock ∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. Absolute Maximum Ratings Item Against φSUB Against GND Against VL Between input clock pins VDD, VOUT, φRG – φSUB Vφ1A, Vφ1B, Vφ3A, Vφ3B – φSUB Vφ2, Vφ4, VL – φSUB Hφ1, Hφ2, GND – φSUB CSUB – φSUB VDD, VOUT, φRG, CSUB – GND Vφ1A, Vφ1B, Vφ2, Vφ3A, Vφ3B, Vφ4 – GND Hφ1, Hφ2 – GND Vφ1A, Vφ1B, Vφ3A, Vφ3B – VL Vφ2, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Hφ1 – Hφ2 Hφ1, Hφ2 – Vφ4 Storage temperature Guaranteed temperature of performance Operating temperature ∗2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply. –2– Ratings –40 to +12 –50 to +15 –50 to +0.3 –40 to +0.3 –25 to –0.3 to +22 –10 to +18 –10 to +6.5 –0.3 to +28 –0.3 to +15 to +15 –6.5 to +6.5 –10to +16 –30 to +80 –10 to +60 –10 to +75 Unit V V V V V V V V V V V V V °C °C °C Remarks ∗2 ICX434DQN Bias Conditions Item Symbol Min. Typ. Max. Unit 14.55 15.0 ∗1 15.45 V Supply voltage VDD Protective transistor bias VL Substrate clock φSUB ∗2 Reset gate clock φRG ∗2 Remarks ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Symbol Supply current Min. Typ. Max. 6.5 IDD Unit Remarks mA Clock Voltage Conditions Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Reset gate clock voltage Min. Typ. Max. Unit Waveform diagram VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 –0.05 0 0.05 V 2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4 –8.0 –7.5 –7.0 V 2 VVL = (VVL3 + VVL4)/2 VφV 6.8 7.5 8.05 V 2 VφV = VVHn – VVLn (n = 1 to 4) Symbol Remarks VVH = (VVH1 + VVH2)/2 VVH3 – VVH –0.25 0.1 V 2 VVH4 – VVH –0.25 0.1 V 2 VVHH 0.5 V 2 High-level coupling VVHL 0.5 V 2 High-level coupling VVLH 0.5 V 2 Low-level coupling VVLL 0.5 V 2 Low-level coupling VφH 3.0 3.3 3.6 V 3 VHL –0.05 0 0.05 V 3 VCR 0.5 1.65 V 3 VφRG 3.0 3.3 3.6 V 4 VRGLH – VRGLL 0.4 V 4 Low-level coupling VRGL – VRGLm 0.5 V 4 Low-level coupling 23.5 V 5 Substrate clock voltage VφSUB 21.5 22.5 –3– Cross-point voltage ICX434DQN Clock Equivalent Circuit Constant Item Symbol Min. Typ. Max. Unit CφV1A, CφV3A 680 pF CφV1B, CφV3B 1500 pF CφV2, CφV4 1500 pF CφV1A2, CφV3A4 100 pF CφV1B2, CφV3B4 220 pF CφV23A, CφV41A 30 pF CφV23B, CφV41B 56 pF CφV1A3A 12 pF CφV1B3B 82 pF CφV1A3B, CφV1B3A 39 pF CφV24 100 pF CφV1A1B, CφV3A3B 30 pF 30 pF 30 pF Capacitance between horizontal transfer CφHH clocks 56 pF Capacitance between reset gate clock and GND CφRG 5 pF Capacitance between substrate clock and GND CφSUB 470 pF R1A, R3A 270 Ω R1B, R3B 110 Ω R2, R4 56 Ω Vertical transfer clock ground resistor RGND 10 Ω Horizontal transfer clock series resistor RφH 15 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Capacitance between horizontal transfer CφH1 clock and GND CφH2 Vertical transfer clock series resistor Remarks Vφ2 R2 CφV1A3A CφV23B CφV23A Vφ3A R3A CφV24 CφV1A2 Vφ1A R1A RφH CφV1B2 CφV1A CφV1A1B CφV1B3A CφV1B CφV41A Vφ1B CφV3A3B CφV1A3B CφV3B R1B CφV4 CφV41B CφHH RφH Hφ1 CφV2 CφV3A Hφ2 CφH1 CφH2 CφV3A4 R3B Vφ3B CφV3B4 RGND CφV1B3B R4 Vφ4 Horizontal transfer clock equivalent circuit Vertical transfer clock equivalent circuit –4– ICX434DQN Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II φM φM 2 VVT 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1A, Vφ1B Vφ3A, Vφ3B VVHH VVH1 VVHH VVH VVHL VVHL VVH3 VVHL VVL1 VVH VVHH VVHH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVH2 VVHL VVHL VVH4 VVL2 VVHL VVLH VVLH VVLL VVLL VVL VVL4 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) –5– VVL ICX434DQN (3) Horizontal transfer clock waveform tr twh tf Hφ2 90% VCR VφH twl VφH 2 10% VHL Hφ1 two Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. (4) Reset gate clock waveform tr twh tf VRGH RG waveform twl VφRG Point A VRGLH VRGLL VRGLm VRGL VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VφRG = VRGH – VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% φM φM 2 VφSUB VSUB 10% 0% tr twh (A bias generated within the CCD) –6– tf ICX434DQN Clock Switching Characteristics (Horizontal drive frequency:18MHz) Item tr tf Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Readout clock VT Vertical transfer clock Vφ1A, Vφ1B, Vφ2, Vφ3A, Vφ3B, Vφ4 Horizontal transfer clock twl twh Symbol 0.5 1.36 1.56 0.5 15 µs 250 ns Hφ1 14 19.5 14 19.5 8.5 14 8.5 14 Hφ2 14 19.5 14 19.5 8.5 14 8.5 14 During Hφ1 parallel-serial Hφ2 conversion 5.56 0.01 0.01 5.56 0.01 0.01 37 4 5 During imaging Reset gate clock φRG Substrate clock φSUB Item 7 10 0.5 1.7 3.6 two Symbol Min. Typ. Max. Horizontal transfer clock Hφ1, Hφ2 12 19.5 Unit Unit Remarks During readout When using CXD1267AN ns tf ≥ tr – 2ns µs ns 0.5 µs During drain charge Remarks ns Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics) 1.0 G 0.9 0.8 R Relative Response 0.7 B 0.6 0.5 0.4 0.3 0.2 0.1 0 400 450 500 550 Wave Length [nm] –7– 600 650 700 ICX434DQN Image Sensor Characteristics Item (Ta = 25°C) Symbol Measurement method mV 1 Typ. Sg 200 250 R Rr 0.46 0.72 1 B Rb 0.33 0.59 1 Saturation signal Vsat 420 Smear Sm Video signal shading SHg Dark signal G sensitivity Sensitivity comparison Max. Unit Min. Remarks 1/30s accumulation mV 2 dB 3 20 % 4 Zone 0 and I 25 % 4 Zone 0 to II' Vdt 8 mV 5 Ta = 60°C, 15 frame/s Dark signal shading ∆Vdt 4 mV 6 Ta = 60°C, 15 frame/s,∗2 Line crawl G Lcg 3.8 % 7 Line crawl R Lcr 3.8 % 7 Line crawl B Lcb 3.8 % 7 Lag Lag 0.5 % 8 –86 –76 –74 –64 Ta = 60°C Frame readout mode∗1 High frame rate readout mode ∗1 After closing the mechanical shutter, the smear can be reduced to below the detection limit by performing vertical register sweep operation. ∗2 Excludes vertical dark signal shading caused by vertical register high-speed transfer. Zone Definition of Video Signal Shading 1636 (H) 8 8 8 V 10 H 8 H 8 Zone 0, I Zone II, II' V 10 1236 (V) 8 Ignored region Effective pixel region Measurement System CCD signal output [∗A] Gr/Gb CCD C.D.S AMP S/H Gr/Gb channel signal output [∗B] R/B S/H R/B channel signal output [∗C] Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1. –8– ICX434DQN Image Sensor Characteristics Measurement Method Color coding of this image sensor & Readout B2 B1 Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr A2 A1 The primary color filters of this image sensor are arranged in the layout shown in the figure on the left (Bayer arrangement). Gr and Gb denote the G signals on the same line as the R signal and the B signal, respectively. For frame readout, the A1 and A2 lines are output as signals in the A field, and the B1 and B2 lines in the B field. Horizontal register Color Coding Diagram Readout modes The diagram below shows the output methods for the following two readout modes. Frame readout mode High frame rate readout mode 1st field VOUT 2nd field 9 R G 9 R G 9 R G 8 G B 8 G B 8 G B 7 R G 7 R G 7 R G 6 G B 6 G B 6 G B 5 R G 5 R G 5 R G 4 G B 4 G B 4 G B 3 R G 3 R G 3 R G 2 G B 2 G B 2 G B 1 R G 1 R G 1 R G VOUT VOUT Note) Blacked out portions in the diagram indicate pixels which are not read out. Output starts from the line 2 in high frame rate readout mode 1. Frame readout mode In this mode, all pixel signals are divided into two fields and output. All pixel signals are read out independently, making this mode suitable for high resolution image capturing. 2. High frame rate readout mode All effective area signals are output in 1/4 the period for frame readout mode by reading out two lines for every eight lines. The number of output lines is 309 lines. This readout mode emphasizes processing speed over vertical resolution. –9– ICX434DQN Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions, and the frame readout mode is used. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb channel signal output or the R/B channel signal output of the measurement system. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 3) Standard imaging condition III: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens (exit pupil distance –33mm) with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. G sensitivity, sensitivity comparison Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (VGr, VGb, VR and VB) at the center of each Gr, Gb, R and B channel screen, and substitute the values into the following formulas. VG = (VGr + VGb)/2 Sg = VG × 100/30 [mV] Rr = VR/VG Rb = VB/VG 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal outputs. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the following formula. ( Sm = 20 × log Vsm ÷ 1 1 Gra + Gba + Ra + Ba × × 500 10 4 – 10 – ) [dB] (1/10V method conversion value) ICX434DQN 4. Video signal shading Set to standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum (Grmax [mV]) and minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula. SHg = (Grmax – Grmin)/150 × 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Line crawl Set to standard imaging condition II. Adjusting the luminous intensity so that the average value of the Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the values into the following formula. Lci = ∆Gli/Gai × 100 [%] (i = r, g, b) 8. Lag Adjust the Gr signal output value generated by strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) × 100 [%] VD Light Strobe light timing Gr signal output 150mV Output – 11 – Vlag (lag) GND 11 10 XV1 φRG Hφ1 Hφ2 VSUB Cont. V2 12 9 XV4 VR1 (3.9k) V4 13 8 XSG1A VH 15 V1B 16 V3A 17 VL 18 V1A 14 CXD3400N 7 XSG1B 6 XV1 5 XSG3A 4 XSG3B 3 XV3 V3B 19 0.1µF 0.1µF 0.1µF 1MΩ 0.1µF 1 2 3 ICX434DQN (BOTTOM VIEW) 8 7 6 5 4 3.3µF/16V 0.1µF 9 16 15 14 13 12 11 10 Vφ4 Hφ2 2 XSUB 100kΩ Vφ3A Hφ1 1µF/35V Vφ3B φRG SHT 20 Vφ2 VL 1 VDD Vφ1A CSUB 0.1µF 15V Vφ1B –7.5V GND φSUB 3.3V VOUT GND – 12 – VDD Drive Circuit 0.01µF 3.3µF/20V 4.7kΩ CCD OUT 2SC4250 ICX434DQN – 13 – A C Exposure operation A output signal B output signal OPEN B High frame rate readout mode C output signal (ODD) CLOSE C output signal (EVEN) Frame readout mode Note) The B output signal contains a blooming component and should therefore not be used. CCD OUT VSUB Cont. Mechanical shutter TRG SUB V4 V3B V3A V2 V1B V1A VD Act. E Output after frame readout D output signal E output signal OPEN D High frame rate readout mode Drive Timing Chart (Vertical Sequence) High Frame Rate Readout Mode → Frame Readout Mode/Electronic Shutter ICX434DQN – 14 – CCD OUT VSUB Cont. Mechanical shutter TRG SUB V4 V3A/V3B V2 V1A/V1B HD VD OPEN 1 2 3 CLOSE "c" "a" 35 30 1 3 5 7 9 1 3 5 7 9 11 Exposure period "c" All pixel output period "b" 685 680 2 4 6 8 10 2 4 6 8 10 12 1229 1231 1233 1235 650 645 26 23 10 Drive Timing Chart (Vertical Sync) Frame Readout Mode 1300 1 2 3 OPEN ICX434DQN 1230 1232 1234 1236 675 673 660 – 15 – V4 V3A/V3B V2 V1A/V1B "b" Enlarged V4 V3A/V3B V2 V1A/V1B H1 "a" Enlarged 72 88 104 152 168 136 120 184 200 188 56 1848 1 216 1131 1071 1091 1071 1029 1027 Drive Timing Chart (Vertical Sync) Frame Readout Mode 1133 1175 88 104 168 152 136 120 ICX434DQN 188 56 1848 1 – 16 – V4 V3B V3A V2 V1B V1A HD 1 "c" Enlarged 56 #1 #2 #3 #4 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 Drive Timing Chart (Vertical Sync) Frame Readout Mode 42504 bits = 23 lines #758 14 14 14 14 56 ICX434DQN – 17 – CCD OUT V4 V3B V3A V2 V1B V1A HD VD "d" 15 18 20 Drive Timing Chart (Vertical Sync) High Frame Rate Readout Mode 320 1218 1223 1226 1231 1234 325 1 2 3 4 5 10 4 9 2 7 10 15 18 23 26 31 1218 1223 1226 1231 1234 325 1 10 "d" 4 9 2 7 10 15 18 23 26 31 15 18 20 ICX434DQN – 18 – V4 V3B V3A V2 V1B V1A H1 "d" Enlarged 72 104 136 168 88 120 152 188 56 1848 1 1029 1071 1071 1133 1111 1131 1091 1091 1027 1071 1175 Drive Timing Chart (Vertical Sync) High Frame Rate Readout Mode 104 136 168 88 120 152 ICX434DQN 188 56 1848 1 – 19 – SUB H2 H1 V4 V3B V3A V2 V1B V1A SHD SHP RG CLK 1 1 1 1 1 1 1 1 1 1 16 16 32 32 1 1 48 1 48 48 1 1 80 80 1 1 64 48 1 1 80 1 1 221 1 216 28 188 132 36 20 52 52 36 68 68 229 1 56 56 1848 1 1 Drive Timing Chart (Horizontal Sync) Frame Readout Mode ICX434DQN – 20 – SUB H2 H1 V4 V3B V3A V2 V1B V1A SHD SHP RG CLK 1 1 1 1 1 16 1 1 32 32 32 1 1 1 32 32 1 1 32 32 32 1 1 1 32 32 1 1 1 64 32 32 32 1 1 1 1 32 1 32 1 36 20 36 36 20 36 36 1848 1 1 1 16 32 56 56 1 1 188 126 32 32 216 28 1 1 221 1 1 32 1 229 1 Drive Timing Chart (Horizontal Sync) High Frame Rate Readout Mode ICX434DQN ICX434DQN Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited AAAA AAAA AAAA AAAA AAAA AAAA Cover glass 50N 50N 1.2Nm Plastic package Compressive strength Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. – 21 – ICX434DQN c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the poweroff mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. – 22 – – 23 – 0.6 2.5 2.5 7.0 2.3 ~ ~ 1.27 0.50g AS-D21(E) DRAWING NUMBER 42 ALLOY LEAD MATERIAL PACKAGE MASS GOLD PLATING LEAD TREATMENT ~ 0.47 9 8 2.5 0.30 ± 0.15 0.64 7.0 8.9 10.0 ± 0.10 H Plastic 1 V PACKAGE MATERIAL PACKAGE STRUCTURE B 5.0 1.0 ± 0.10 16 8.9 0.6 A 2.0 5.0 10.0 ± 0.10 B' 0.3 M (0.6) 0.15 ˚ 0˚ to 10 C 1.7 8 9 1.7 1 16 The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5. 8 9 The tilt of the effective image area relative to the bottom “C” is less than 25µm. The tilt of the effective image area relative to the top “D” of the cover glass is less than 25µm. The height from the bottom “C” to the effective image area is 1.20 ± 0.10mm. The height from the top of the cover glass “D” to the effective image area is 1.30 ± 0.15mm. 6 7 The rotation angle of the effective image area relative to H and V is ±1˚. The center of the effective image area relative to “B” and “B” is (H, V) = (5.0, 5.0) ± 0.07mm. The bottom “C” of the package, and the top of the cover glass “D” are the height reference. 5 4 3 2. The two points “B” of the package are the horizontal reference. The point “B'” of the package is the vertical reference. 1. “A” is the center of the effective image area. D 0.25 ± 0.05 16 pin SOP 2.50 ± 0.15 Unit: mm 12.0 ± 0.15 Package Outline ICX434DQN Sony Corporation