SONY ICX205AK

ICX205AK
Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX205AK is a diagonal 8mm (Type 1/2)
interline CCD solid-state image sensor with a square
pixel array and 1.45M effective pixels. Progressive
scan allows all pixels' signals to be output
independently within approximately 1/7.5 second.
Also, the adoption of high frame rate readout mode
supports 30 frames per second. This chip features
an electronic shutter with variable charge-storage
time which makes it possible to realize full-frame still
image without a mechanical shutter. High resolution
and high color reproductivity are achieved through
the use of R, G, B primary color mosaic filters.
Further, high sensitivity and low dark current are
achieved through the adoption of HAD (HoleAccumulation Diode) sensors.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
Features
• Progressive scan allows individual readout of the
image signals from all pixels.
• High horizontal and vertical resolution (both approx.
800TV-lines) still image without a mechanical shutter.
• Supports high frame rate readout mode
(effective 256 lines output, 30 frame/s)
• Square pixel
• Horizontal drive frequency: 14.318MHz
• No voltage adjustments
(reset gate and substrate bias are not adjusted.)
• R, G, B primary color mosaic filters on chip
• High resolution, high color reproductivity,
high sensitivity, low dark current
• Low smear, excellent antiblooming characteristics
• Continuous variable-speed shutter
Device Structure
• Interline CCD image sensor
• Image size:
• Total number of pixels:
• Number of effective pixels:
• Number of active pixels:
• Chip size:
• Unit cell size:
• Optical black:
• Number of dummy bits:
• Substrate material:
20 pin DIP (Cer-DIP)
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Pin 1
2
V
2
Pin 11
H
8
40
Optical black position
(Top View)
Diagonal 8mm (Type 1/2)
1434 (H) × 1050 (V) approx. 1.50M pixels
1392 (H) × 1040 (V) approx. 1.45M pixels
1360 (H) × 1024 (V) approx. 1.40M pixels (7.959mm diagonal)
7.60mm (H) × 6.20mm (V)
4.65µm (H) × 4.65µm (V)
Horizontal (H) direction: Front 2 pixels, rear 40 pixels
Vertical (V) direction: Front 8 pixels, rear 2 pixels
Horizontal 20
Vertical 3
Silicon
∗ Wfine CCD is a registered trademark of Sony Corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98118B99
ICX205AK
GND
NC
GND
NC
NC
Vφ3
Vφ2B
Vφ2A
Vφ1
10
9
8
7
6
5
4
3
2
1
B
G
B
R
G
R
G
G
B
R
...
...
...
G
...
Vertical register
VOUT
Block Diagram and Pin Configuration
(Top View)
G
B
G
R
G
G
B
G
B
R
G
R
G
Note)
Note)
: Photo sensor
16
NC
CSUB
NC
17
18
19
20
Hφ2
15
Hφ1
14
φRG
13
VL
12
φSUB
VDD
11
GND
Horizontal register
Pin Description
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
Vφ1
Vertical register transfer clock
11
VDD
Supply voltage
2
Vφ2A
Vertical register transfer clock
12
GND
GND
3
Vφ2B
Vertical register transfer clock
13
φSUB
Substrate clock
4
Vφ3
Vertical register transfer clock
14
NC
5
NC
15
CSUB
6
NC
16
NC
7
GND
17
VL
Protective transistor bias
8
NC
18
φRG
Reset gate clock
9
GND
GND
19
Hφ1
Horizontal register transfer clock
10
VOUT
Signal output
20
Hφ2
Horizontal register transfer clock
GND
Substrate bias∗1
∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
–2–
ICX205AK
Absolute Maximum Ratings
Item
Ratings
Unit Remarks
VDD, VOUT, φRG – φSUB
–40 to +10
V
Vφ2A, Vφ2B – φSUB
–50 to +15
V
Vφ1, Vφ3, VL – φSUB
–50 to +0.3
V
Hφ1, Hφ2, GND – φSUB
–40 to +0.3
V
–25 to
V
VDD, VOUT, φRG, CSUB – GND
–0.3 to +18
V
Vφ1, Vφ2A, Vφ2B, Vφ3 – GND
–10 to +18
V
Hφ1, Hφ2 – GND
–10 to +15
V
Vφ2A, Vφ2B – VL
–0.3 to +28
V
Vφ1, Vφ3, Hφ1, Hφ2, GND – VL
–0.3 to +15
V
to +15
V
Hφ1 – Hφ2
–16 to +16
V
Hφ1, Hφ2 – Vφ3
–16 to +16
V
Storage temperature
–30 to +80
°C
Operating temperature
–10 to +60
°C
Against φSUB
CSUB – φSUB
Against GND
Against VL
Voltage difference between vertical clock input pins
Between input
clock pins
∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
+16V (Max.) is guaranteed for turning on or off power supply.
–3–
∗1
ICX205AK
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
14.55
15.0
∗1
15.45
V
Supply voltage
VDD
Protective transistor bias
VL
Substrate clock
φSUB
∗2
Reset gate clock
φRG
∗2
Remarks
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Symbol
Supply current
Min.
Typ.
Max.
5.5
IDD
Unit
Remarks
mA
Clock Voltage Conditions
Min.
Typ.
Max.
Unit
Waveform
diagram
VVT
14.55
15.0
15.45
V
1
VVH02A
–0.05
0
0.05
V
2
VVH1, VVH2A,
VVH2B, VVH3
–0.2
0
0.05
V
2
VVL1, VVL2A,
VVL2B, VVL3
–8.4
–8.0
–7.6
V
2
Vφ1, Vφ2A,
Vφ2B, Vφ3
7.6
8.0
8.4
V
2
| VVL1 – VVL3 |
0.1
V
2
VVHH
0.9
V
2
High-level coupling
VVHL
1.3
V
2
High-level coupling
VVLH
1.0
V
2
Low-level coupling
VVLL
0.9
V
2
Low-level coupling
Item
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Symbol
VVH = VVH02A
VVL = (VVL1 + VVL3)/2
VφH
4.75
5.0
5.25
V
3
VHL
–0.05
0
0.05
V
3
3.0
3.3
5.5
V
4
VRGLH – VRGLL
0.4
V
4
Low-level coupling
VRGL – VRGLm
0.5
V
4
Low-level coupling
23.85
V
5
VφRG
Reset gate clock
voltage
Remarks
Substrate clock voltage VφSUB
22.15
23.0
–4–
ICX205AK
Clock Equivalent Circuit Constant
Item
Symbol
Capacitance between vertical transfer clock and
GND
Capacitance between vertical transfer clocks
Min.
Typ.
Max.
Unit
CφV1
2200
pF
CφV2A
1800
pF
CφV2B
6800
pF
CφV3
3300
pF
CφV12A, CφV2B1
1200
pF
CφV2A3, CφV32B
1200
pF
CφV13
2200
pF
Capacitance between horizontal transfer clock
and GND
CφH1, CφH2
47
pF
Capacitance between horizontal transfer clocks
CφHH
100
pF
Capacitance between reset gate clock and GND
CφRG
8
pF
Capacitance between substrate clock and GND
CφSUB
680
pF
R1
36
Ω
R2A, R3
56
Ω
R2B
43
Ω
Vertical transfer clock ground resistor
RGND
30
Ω
Horizontal transfer clock series resistor
RφH
15
Ω
Reset gate clock series resistor
RφRG
20
Ω
Vertical transfer clock series resistor
Vφ1
Remarks
Vφ2A
CφV12A
R1
R2A
RφH
RφH
Hφ2
Hφ1
CφV1
CφHH
CφV2A
CφV2B1
CφV2A3
CφH1
CφH2
CφV13
CφV2B RGND CφV3
R2B
R3
CφV32B
Vφ2B
Vφ3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
RφRG
RGφ
CφRG
Reset gate clock equivalent circuit
–5–
ICX205AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
VT
100%
90%
II
II
φM
φM
2
VVT
10%
0%
tr
twh
0V
tf
Note) Readout clock is used by composing vertical transfer clocks Vφ2A and Vφ2B.
(2) Vertical transfer clock waveform
Vφ1
VVH1
VVHH
VVH
VVHL
VVLH
VVL01
VVL1
VVL
VVLL
Vφ2A, Vφ2B
VVH02A, VVH02B
VVH2A, VVH2B
VVHH
VVH
VVHL
VVLH
VVL2A, VVL2B
VVL
VVLL
Vφ3
VVH3
VVHH
VVH
VVHL
VVLH
VVL03
VVL
VVLL
VVH = VVH02A
VVL = (VVL01 + VVL03) / 2
VVL3 = VVL03
–6–
VφV1 = VVH1 – VVL01
VφV2A = VVH02A – VVL2A
VφV2B = VVH02B – VVL2B
VφV3 = VVH3 – VVL03
ICX205AK
(3) Horizontal transfer clock waveform
tr
twh
tf
Hφ2
90%
VCR
VφH
twl
VφH
2
10%
VHL
Hφ1
two
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
tr
twh
tf
VRGH
RG waveform
twl
VφRG
Point A
VRGLH
VRGLL
VRGLm
VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL.
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
φM
φM
2
VφSUB
10%
VSUB
0%
(A bias generated within the CCD)
tr
–7–
twh
tf
ICX205AK
Clock Switching Characteristics
Item
twh
Symbol
twl
tr
tf
Unit
Remarks
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
VT
Vertical transfer
clock
Vφ1, Vφ2A,
Vφ2B, Vφ3
Horizontal
transfer clock
Readout clock
During
imaging
2.3 2.5
0.5
0.5
15
µs During readout
450 ns
∗1
∗2
Hφ1
20
25
20
25
10
15
10
15
Hφ2
20
25
20
25
10
15
10
15
During
Hφ1
parallel-serial
Hφ2
conversion
Reset gate clock
φRG
Substrate clock
φSUB
11
13
51
0.01
0.01
0.01
0.01
3
3
2.2
0.5
ns
µs
ns
0.5 µs
During drain
charge
∗1 When vertical transfer clock driver CXD1267AN × 2 is used.
∗2 tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be
at least VφH/2 [V].
Item
two
Symbol
Unit
Remarks
Min. Typ. Max.
Horizontal transfer clock
Hφ1, Hφ2
16
20
ns
Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)
1
G
R
0.8
Relative Response
B
0.6
0.4
0.2
0
400
500
600
Wave Length [nm]
–8–
700
ICX205AK
Image Sensor Characteristics
Item
(Ta = 25°C)
Symbol
Measurement
method
mV
1
Typ.
Sg
320
400
R
Rr
0.4
0.55
0.7
1
B
Rb
0.3
0.45
0.6
1
Saturation signal
Vsat
450
Smear
Sm
Video signal shading
SHg
G sensitivity
Sensitivity
comparison
Max.
Unit
Min.
Remarks
1/30s accumulation
mV
2
Ta = 60°C
0.0025
%
3
No electronic shutter
20
%
4
Zone 0 and I
25
%
4
Zone 0 to II'
∆Srg
8
%
5
∆Sbg
8
%
5
Dark signal
Vdt
16
mV
6
Ta = 60°C
Dark signal shading
∆Vdt
4
mV
7
Ta = 60°C
Line crawl G
Lcg
3.8
%
8
Line crawl R
Lcr
3.8
%
8
Line crawl B
Lcb
3.8
%
8
Lag
Lag
0.5
%
9
Uniformity between video
signal channels
0.001
Zone Definition of Video Signal Shading
1392 (H)
16
16
8
V
10
H
8
H
8
Zone 0, I
Zone II, II'
V
10
1040 (V)
8
Ignored region
Effective pixel region
Measurement System
CCD signal output [∗A]
Gr/Gb
CCD
C.D.S
AMP
S/H
Gr/Gb channel signal output [∗B]
R/B
S/H
R/B channel signal output [∗C]
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1.
–9–
ICX205AK
Image Sensor Characteristics Measurement Method
Color coding and readout of this image sensor
Gb
B
Gb
B
R
Gr
R
Gr
Gb
B
Gb
B
R
Gr
R
Gr
The primary color filters of this image sensor are arranged in the layout
shown in the figure on the left (Bayer arrangement).
Gr and Gb denote the G signals on the same line as the R signal and
the B signal, respectively.
Horizontal register
Color Coding Diagram
All pixel signals are output successively in a 1/7.5s period.
The R signal and Gr signal lines and the Gb signal and B signal lines are output successively.
– 10 –
ICX205AK
Readout modes
The diagram below shows the output methods for the following two readout modes.
High frame rate readout mode
Progressive scan mode
VOUT
16
G
B
16
G
B
15
R
G
15
R
G
14
G
B
14
G
B
13
R
G
13
R
G
12
G
B
12
G
B
11
R
G
11
R
G
10
G
B
10
G
B
9
R
G
9
R
G
8
G
B
8
G
B
7
R
G
7
R
G
6
G
B
6
G
B
5
R
G
5
R
G
4
G
B
4
G
B
3
R
G
3
R
G
2
G
B
2
G
B
1
R
G
1
R
G
VOUT
Note) Blacked out portions in the diagram indicate pixels which are not read out.
Output starts from the line 1 in high frame rate readout mode.
1. Progressive scan mode
In this mode, all pixel signals are output in non-interlace format in 1/7.5s.
The vertical resolution is approximately 800TV-lines and all pixel signals within the same exposure period
are read out simultaneously, making this mode suitable for high resolution image capturing.
2. High frame rate readout mode
All effective areas are scanned in approximately 1/30s by reading out two out of eight lines (1st and 4th
lines, 9th and 12th lines). The vertical resolution is approximately 200TV-lines.
This readout mode emphasizes processing speed over vertical resolution.
– 11 –
ICX205AK
Measurement conditions
1) In the following measurements, the device drive conditions are at the typical values of the progressive scan
mode, bias and clock voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb
signal output or the R/B signal output of the measurement system.
Definition of standard imaging conditions
1) Standard imaging condition I:
Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter
and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the
standard sensitivity testing luminous intensity.
2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. G sensitivity, sensitivity comparison
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/100s, measure the signal outputs (VGr, VGb, VR and VB) at the center of each Gr, Gb, R and B channel
screen, and substitute the values into the following formulas.
VG = (VGr + VGb)/2
Sg = VG × 100/30 [mV]
Rr = VR/VG
Rb = VB/VG
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the
average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal
outputs.
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of
the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R
signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times
the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and
the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum
value (VSm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the
following formula.
Sm = Vsm ÷
Gra + Gba + Ra + Ba
4
×
1
1
×
× 100 [%] (1/10V method conversion value)
10
500
4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the Gr signal output is 150mV. Then measure the maximum (Grmax [mV]) and
minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula.
SHg = (Grmax – Grmin)/150 × 100 [%]
– 12 –
ICX205AK
5. Uniformity between video signal channels
After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of the R signal
and the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of the B signal, and substitute the values
into the following formulas.
∆Srg = (Rmax – Rmin)/150 × 100 [%]
∆Sbg = (Bmax – Bmin)/150 × 100 [%]
6. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
7. Dark signal shading
After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Vdt = Vdmax – Vdmin [mV]
8. Line crawl
Set to standard imaging condition II. Adjusting the luminous intensity so that the average value of the Gr
signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal
lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab).
Substitute the values into the following formula.
Lci = ∆Gli/Gai × 100 [%] (i = r, g, b)
9. Lag
Adjust the Gr signal output value generated by strobe light to 150mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
Lag = (Vlag/150) × 100 [%]
VD
V2A
Light
Strobe light
Timing
Gr signal output 150mV
Output
– 13 –
Vlag (lag)
RG
H1
H2
XSUB
XV3
XV2B
XSG2
XV1
XV2A
XSG1
–8.0V
15V
22/20V
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
CXD1267AN
CXD1267AN
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
1/35V
100k
0.1
0.1
22/16V
1
2
3
4
5
6
7
8
9
10
ICX205
(Bottom View)
Vφ1
Vφ2A
Vφ2B
Vφ3
NC
NC
GND
NC
GND
VOUT
0.1
1M
2200P
22/20V
Hφ2
Hφ1
φRG
VL
NC
CSUB
NC
φSUB
GND
VDD
– 14 –
20
19
18
17
16
15
14
13
12
11
Drive Circuit
3.9k
CCD OUT
0.01
2SK523
100
ICX205AK
– 15 –
V3
V2A/V2B
V1
HD
XSG1/XSG2
XV3
XV2A/XV2B
XV1
Sensor Readout Clock Timing Chart
55.8µs (800 bits)
Progressive Scan Mode
139ns (2 bits)
3.49µs (50 bits)
Sensor readout clocks XSG1 and XSG2 are used by composing XV2A and XV2B.
ICX205AK
XSG2
XSG1
XV3
– 16 –
V3
V2B
V2A
V1
HD
XV2A/XV2B
XV1
Sensor Readout Clock Timing Chart
55.8µs (800 bits)
139ns (2 bits)
5.0µs (72 bits)
14 bits
14 bits
3.49µs (50 bits)
AAAA
AAAA
Sensor readout clock XSG1 is used by composing XV2A.
High Frame Rate Readout Mode
5.87µs (84 bits)
ICX205AK
– 17 –
CCD
OUT
V3
V2B
V2A
V1
HD
VD
Progressive Scan Mode
21
13
12
9
10
11
8
6
7
5
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10
1052
1038
1039
1040
3
4
1068
1
2
1063
1040
Drive Timing Chart (Vertical Sync)
1 2 3 4 5 6 7 8 1 2 3 4 5
ICX205AK
1068
1
1063
1044
– 18 –
CCD
OUT
V3
V2B
V2A
V1
HD
1 4 1 4 9 12 17 20 25
1/30s
1020
1025
1028
1033
1036
VD
266
267
1
2
3
4
5
6
7
8
High Frame Rate Readout Mode
1 4 1 4 9 12 17 20 25
260
261
262
263
264
265
266
267
1
2
3
4
5
6
7
8
Drive Timing Chart (Vertical Sync)
1/30s
1 4 1 4 9 12 17 20 25
ICX205AK
1020
1025
1028
1033
1036
– 19 –
RGφ
1
1
1
1
SUB
16
1
56
Vφ3
Vφ2B
Vφ2A
Vφ1
Hφ2
Hφ1
CLK
1
1790
1
HD
32
32
1
1
96
64 1
96 1
96 1
96 1
96 1
Progressive Scan Mode
392
176
176
96 1
64 1
208
208
240
2
430
Drive Timing Chart (Horizontal Sync)
ICX205AK
412
– 20 –
RGφ
1
1 14
1 14
1
SUB
16
1
56
Vφ3
Vφ2B
Vφ2A
Vφ1
Hφ2
Hφ1
CLK
1
1790
1
HD
28
1
1
1
42
96
1
42
42
1
1
42
1
42
1
42
42
42
1
1
1
42
42
42
1
1
1
42
High Frame Rate Readout Mode
168
1
42
42
42
1
1
42
1
1
1
42
1
42
42
1
1
42
1
42
1
42
42
42
112
1
1
1
1
42
1
42
42
1
1
42
392
56
1 14
28
28
42
2
430
Drive Timing Chart (Horizontal Sync)
ICX205AK
412
ICX205AK
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
AAAA AAAA AAAA AAAA
AAAA AAAA AAAA AAAA
Upper ceramic
Lower ceramic
39N
29N
29N
0.9Nm
Low melting
point glass
Compressive strength
Shearing strength
– 21 –
Tensile strength
Torsional strength
ICX205AK
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation,
use either an elastic load, such as a spring plate, or an adhesive.
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not
to perform the following actions as this may cause cracks.
• Applying repeated bending stress to the outer leads.
• Heating the outer leads for an extended period with a soldering iron.
• Rapidly cooling or heating the package.
• Applying any load or impact to a limited portion of the low melting point glass using tweezers or other
sharp tools.
• Prying at the upper or lower ceramic using the low melting point glass as a fulcrum.
Note that the same cautions also apply when removing soldered products from boards.
e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.
(reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
– 22 –
– 23 –
~
~
Cer-DIP
TIN PLATING
42 ALLOY
2.6g
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
0.3
3
14.6
M
1.778
10
11
18.0 ± 0.4
H
0.4
V
PACKAGE MATERIAL
1
20
A
0.8
0.46
B'
C
0° to 9°
1.4
10
11
(R0.7)
(1.0)
17.6
φ1.4
1
20
(1.7)
9. The notch and the hole on the bottom must not be used for reference of fixing.
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
7. The tilt of the effective image area relative to the bottom “C” is less than 60µm.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ± 1°.
4. The center of the effective image area, relative to “B” and “B'” is
(H, V) = (9.0, 7.55) ± 0.15mm.
3. The bottom “C” of the package is the height reference.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
1. “A” is the center of the effective image area.
0.25
3
11.55
PACKAGE STRUCTURE
B
3
0.55
9.0
15.1 ± 0.3
0.7
0.7
7.55
0.4
0.83
(4.0)
20pin DIP (600mil)
1.27
15.24
3.4 ± 0.3
4.0 ± 0.3
Unit: mm
~
Package Outline
ICX205AK