LCX007BNB
3.4cm (1.35-inch) Black-and-White LCD Panel
For the availability of this product, please contact the sales office.
Description
The LCX007BNB is a 3.4cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral driving
circuit. This panel, with polarizers on the both faces,
displays black-and-white images suitable to videophotographic printers and other applications.
This panel provides a wide aspect ratio of 16 : 9,
such as those represented in HD. The built-in sideblack function also allows an aspect ratio of 4 : 3 in
the NTSC/PAL mode.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing
system and control signals.
Features
• The number of active dots: 512,880 (1.35-inch; 3.4cm in diagonal)
• Horizontal resolution: 600 TV lines
• High optical transmittance: 16.5% (typ.)
• High contrast ratio with normally white mode: 190 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• NTSC/NTSC-WIDE/HD (band: 20MHz) mode selectable
(PAL/PAL-WIDE mode also available through conversion of scanned dot numbers by an external IC)
• Up/down and/or right/left inverse display function
• Side-black function
• 16 : 9 and 4 : 3 aspect-ratio switching function
Element Structure
• Dots
16 : 9 display
4 : 3 display
: 1068.5 (H) × 480 (V) = 512,880
: 799.5 (H) × 480 (V) = 383,760
• Built-in peripheral driver using polycrystalline silicon super thin film transistors.
Applications
Video-photographic printers etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95816A68-PS
Side Black
Control Circuit
V Shift Register
(Bidirectional Scanning)
V Shift Register
(Bidirectional Scanning)
Up/Down or Right/Left Inversion
4 : 3/16 : 9
Control Circuit
SID
HST
HCK1
HCK2
WID
RGT
VST
VCK
PCG
DWN
ENB
CLR
HVDD
VVDD
VSS
SIG1 (G)
SIG2 (R)
SIG3 (B)
COM
LCX007BNB
Block Diagram
1
8
10
11
6
7
16
14
15
17
13
12
5
18
9
2
3
4
19
Input Signal
Level Shifter
H Shift Register (Bidirectional Scanning)
COM
Pad
–2–
LCX007BNB
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage
HVDD
• V driver supply voltage
VVDD
• Common pad voltage
COM
• H shift register input pin voltage
HST, HCK1, HCK2
RGT, WID
• V shift register input pin voltage
VST, VCK, PCG
CLR, ENB, DWN
• Video signal input pin voltage
SIG1, SIG2, SIG3, SID
• Operating temperature
Topr
• Storage temperature
Tstg
–1.0 to +20
–1.0 to +20
–1.0 to +17
–1.0 to +17
V
V
V
V
–1.0 to +17
V
–1.0 to +15
–10 to +70
–30 to +85
V
°C
°C
Operating Conditions (VSS = 0V)
Supply voltage
HVDD
15.7 +0.3
V
–0.4
+0.3
VVDD
15.7 –0.4
V
Input pulse voltage (Vp-p of all input pins except video signal and side black signal input pins)
Vin
5.0 ± 0.5
V
Pin Description
Pin
No.
Symbol
Description
Pin
No.
Symbol
Description
1
SID
Side black signal for 4:3 display
11
HCK2
Clock pulse for H shift register
drive
2
SIG1 (G)
Video signal (G∗1) to panel
12
CLR
Improvement pulse (1) for
uniformity
3
SIG2 (R)
Video signal (R∗1) to panel
13
ENB
Enable pulse for gate selection
4
SIG3 (B)
Video signal (B∗1) to panel
14
VCK
Clock pulse for V shift register
drive
5
HVDD
Power supply for H driver
15
PCG
Improvement pulse (2) for
uniformity
6
WID
Aspect-ratio switching
(H: 16:9, L: 4:3)
16
VST
Start pulse for V shift register
drive
7
RGT
Drive direction pulse for H shift
register (H: normal, L: reverse)
17
DWN
Drive direction pulse for V shift
register (H: normal, L: reverse)
8
HST
Start pulse for H shift register
drive
18
VVDD
Power supply for V driver
9
Vss
GND (H, V drivers)
19
COM
Common voltage of panel
10
HCK1
Clock pulse for H shift register
drive
20
TEST
Test; Open
∗1 (R), (G) and (B) are indicated for convenience to show the correspondence with the dot arrangement
diagram.
–3–
LCX007BNB
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. All pins are connected to Vss with a high
resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.)
(1) SIG1, SIG2, SIG3, SID
HVDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
Input
Level conversion circuit
(2-phase input)
250Ω
1MΩ
250Ω
1MΩ
(3) RGT, WID
HVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(4) HST
HVDD
250Ω
Input
250Ω Level conversion circuit
(single-phase input)
1MΩ
(5) PCG, VCK
VVDD
250Ω
250Ω
Input
Level conversion circuit
(single-phase input)
1MΩ
(6) VST, CLR, ENB, DWN
VVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(7) COM
VVDD
Input
1MΩ
–4–
LC
LCX007BNB
Input Signals
1. Input signal voltage conditions (VSS = 0V)
Item
Min.
Typ.
Max.
Unit
(Low) VHIL
–0.5
0.0
0.3
V
(High) VHIH
4.5
5.0
5.5
V
(Low) VVIL
V driver input voltage
CLR, ENB, VCK, PCG, VST, DWN (High) VVIH
–0.5
0.0
0.3
V
4.5
5.0
5.5
V
VVC
6.5
7.0
7.2
V
Vsig
VVC – 4.5
—
VVC + 4.5
V
Vcom
VVC – 0.5
VVC – 0.4
VVC – 0.3
V
H driver input voltage
WID, RGT, HST, HCK1, HCK2
Video signal center voltage
Video signal input range∗1
Common voltage of panel∗2
Symbol
∗1 Video input signal shall be symmetrical to VVC.
∗2 Common voltage of the panel shall be adjusted to VVC – 0.4V.
Level Conversion Circuit
The LCX007BNB has a built-in level conversion circuit in the clock input unit on the panel. The input signal
level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
–5–
LCX007BNB
2. Clock timing conditions (Ta = 25°C) (fHCKn = 7.5MHz, fVCK = 15.7kHz)
Item
HST
HCK
CLR
VST
VCK
ENB
PCG
Symbol
Min.
Typ.
Max.
Hst rise time
trHst
—
—
30
Hst fall time
tfHst
—
—
30
Hst data set-up time
tdHst
20
67
100
Hst data hold time
Hckn∗3 rise time
thHst
–40
0
40
trHckn
—
—
30
Hckn∗3 fall time
tfHckn
—
—
30
Hck1 fall to Hck2 rise time
to1Hck
–15
0
15
Hck1 rise to Hck2 fall time
to2Hck
–15
0
15
Clr rise time
trClr
—
—
100
Clr fall time
tfClr
—
—
100
Clr pulse width
twClr
3000
3100
3200
Vck rise/fall to Clr fall time
tdClr
–50
0
50
Vst rise time
trVst
—
—
100
Vst fall time
tfVst
—
—
100
Vst data set-up time
tdVst
–25
15
25
Vst data hold time
thVst
5
15
25
Vck rise time
trVck
—
—
100
Vck fall time
tfVck
—
—
100
Enb rise time
trEnb
—
—
100
Enb fall time
tfEnb
—
—
100
Vck rise/fall to Enb rise time
tdEnb
350
400
450
Enb pulse width
twEnb
3450
3500
3550
Pcg rise time
trPcg
—
—
20
Pcg fall time
tfPcg
—
—
20
Pcg fall to Vck rise/fall time
toVck
650
700
750
Pcg pulse width
twPcg
1150
1200
1250
∗3 Hckn means Hck1 and Hck2.
–6–
Unit
ns
µs
ns
LCX007BNB
<Horizontal Shift Register Driving Waveform>
Item
Hst rise time
Symbol
Waveform
90%
trHst
Hst
Hst fall time
HST
Conditions
90%
10%
tfHst
10%
trHst
tfHst
∗4
Hst data set-up time
tdHst
50%
50%
Hst
Hck1
50%
Hst data hold time
50%
thHst
tdHst
Hckn∗3 rise time
∗3
Hckn∗3 fall time
Hck1 fall to Hck2 rise
time
50%
to2Hck
Clr rise time
trClr
tfHckn
50%
Hck1
50%
Hck1 rise to Hck2 fall
time
50%
Hck2
to2Hck
to1Hck
90%
90%
Clr
10%
10%
Clr fall time
tfClr
Clr pulse width
twClr
Vck rise/fall to Clr fall
time
tdClr
O Hckn∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
10%
trHckn
∗4
to1Hck
90%
10%
tfHckn
O Hckn∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
thHst
90%
trHckn
Hckn
HCK
O Hckn∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
trClr
tfClr
CLR
Vck
50%
Clr
50%
∗4
twClr
–7–
50%
tdClr
O Hckn∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
LCX007BNB
<Vertical Shift Register Driving Waveform>
Item
Vst rise time
Symbol
Waveform
90%
VST
90%
trVst
Vst
Vst fall time
Conditions
10%
tfVst
10%
trVst
tfVst
∗4
Vst data set-up time
tdVst
50%
50%
Vst
50%
50%
Vck
Vst data hold time
Vck rise time
thVst
trVck
Vck fall time
tfVck
Enb rise time
trEnb
thVst
90%
90%
10%
Vck
VCK
tdVst
10%
trVckn
90%
tfVckn
10%
10%
90%
Enb
Enb fall time
ENB
tfEnb
Vck rise/fall to Enb rise
tdEnb
time
tfEn
Vck
50%
Enb
Enb pulse width
trEn
50%
50%
twEnb
twEnb
Pcg rise time
PCG
∗4 Definitions:
50%
tfPcg
Pcg fall to Vck rise/fall
toVck
time
Pcg pulse width
∗4
trPcg
Vck
Pcg fall time
tdEnb
twPcg
Pcg
50%
50%
twPcg
toVck
∗4
The right-pointing arrow (
) means +.
The left-pointing arrow (
) means –.
The black dot at an arrow (
) indicates the start of measurement.
–8–
LCX007BNB
Electrical Characteristics (Ta = 25°C, HVDD = 15.7V, VVDD = 15.7V)
1. Horizontal drivers
Item
Symbol
Min.
Typ.
Max.
Unit
HCKn
CHckn
—
7
10
pF
HST
CHst
—
7
10
pF
HCK1
–500
–120
—
µA
HCK1 = GND
HCK2
–1000
–450
—
µA
HCK2 = GND
HST
–500
–160
—
µA
HST = GND
WID, RGT
–150
–30
—
µA
WID, RGT = GND
Input pin capacitance
Input pin current
Condition
Video signal input pin capacitance
Csig
—
250
—
pF
Current consumption
IH
—
7.5
10
mA
HCKn: HCK1, HCK2 (7.5MHz)
Symbol
Min.
Typ.
Max.
Unit
Condition
Input pin capacitance VCK
CVck
—
7
10
pF
VST
CVst
—
7
10
pF
VCK
–1000
–160
—
µA
VCK = GND
PCG, VST, EN, CLR, DWN
–150
–30
—
µA
PCG, VST, EN, CLR, DWN = GND
—
1.5
4
mA
VCK: (15.7kHz)
Symbol
Min.
Typ.
Max.
Unit
PWR
—
150
250
mW
Symbol
Min.
Typ.
Max.
Unit
Rpin
0.4
1
—
MΩ
Symbol
Min.
Typ.
Max.
Unit
CSIDon
8
10
12
nF
2. Vertical drivers
Item
Input pin current
Current consumption
IV
3. Total power consumption of the panel
Item
Total power consumption of
the panel (NTSC)
4. Pin input resistance
Item
Pin-VSS input resistance
5. Side signal input pin capacitance
Item
Side signal input pin
capacitance
–9–
LCX007BNB
Electro-optical Characteristics
(Ta = 25°C, NTSC mode)
Item
Symbol
Measurement
method
Min.
Typ.
Max.
Unit
Contrast ratio
60°C
CR60
1
130
190
—
—
Optical transmittance
60°C
T
2
14.0
16.5
—
%
RV90-25
1.2
1.5
1.8
GV90-25
1.4
1.7
2.0
BV90-25
1.7
2.0
2.3
RV90-60
1.1
1.4
1.7
GV90-60
1.2
1.5
1.8
BV90-60
1.4
1.7
2.0
RV50-25
1.7
2.0
2.3
GV50-25
1.8
2.1
2.4
2.0
2.3
2.6
RV50-60
1.5
1.8
2.1
GV50-60
1.6
1.9
2.2
BV50-60
1.8
2.1
2.4
RV10-25
2.3
2.6
2.9
GV10-25
2.4
2.7
3.0
BV10-25
2.6
2.9
3.2
RV10-60
2.1
2.4
2.7
GV10-60
2.2
2.5
2.8
BV10-60
2.4
2.7
3.0
0°C
ton0
—
50
100
25°C
ton25
—
15
40
0°C
toff0
—
52
150
25°C
toff25
—
16
60
Flicker
60°C
F
5
—
—
–30
dB
Image retention time
25°C
YT60
6
—
—
0
s
Cross talk
25°C
CTK
7
—
—
5
%
25°C
V90
60°C
25°C
V-T
characteristics
BV50-25
V50
60°C
25°C
V10
60°C
ON time
Response time
OFF time
3
4
– 10 –
V
ms
LCX007BNB
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 15.7V, VVDD = 15.7V
VVC = 7.0V, Vcom = 6.6V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of screen unless otherwise specified.
(4) Measurement systems
Two types of measurement system are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.0 ± VAC [V]
(VAC: signal amplitude)
Back Light
∗ Measurement system I
Luminance
Meter
3.5mm
Measurement
Equipment
Back light: color temperature 6500 ± 700K (25°C)
Polarizer: POLATECHNO Co., Ltd. THC-13U (Luminance meter side)
LCD panel
∗ Measurement system II
Optical fiber
Light receptor lens
Light Detector
Measurement
Equipment
LCD panel
Drive Circuit
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
CR =
L (White)
... (1)
L (Black)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.5V.
Both luminosities are measured by System I.
– 11 –
LCX007BNB
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
T=
L (White)
× 100 [%] ... (2)
Luminance of Back Light
3. V-T Characteristics
V-T characteristics, the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II. V90, V50 and V10 correspond to
the each voltage which defines 90%, 50% and 10% of
transmittance respectively.
Transmittance [%]
L (White) is the same expression as defined in the 'Contrast Ratio' section.
90
50
10
V90
V50 V10
VAC – Signal amplitude [V]
4. Response Time
Response time 'ton' and 'toff' are defined by
the formula (5) and (6) respectively.
Input signal voltage (waveform applied to the measured pixels)
4.5V
ton = t1 – tON ... (5)
toff = t2 – tOFF ... (6)
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
0.5V
7.0V
0V
Light transmission output waveform
100%
90%
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
10%
0%
tON
t1
ton
– 12 –
tOFF
t2
toff
LCX007BNB
5. Flicker
Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the
panel output signal for gray raster∗1 mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
F [dB] = 20 log
AC component
... (7)
{ DC
component }
∗1 Each input signal condition for gray raster mode is given by
Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives 50% of
transmittance in V-T characteristics.
6. Image Retention Time
Image Retention time is given by following procedures.
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of
Vsig = 7.0 ± VAC (VAC: 3 to 4V). Hold VAC that maximizes image retention judging by sight. Measure the time
till the residual image becomes indistinct.
Black level
∗ Monoscope signal conditions:
White level
4.5V
Vsig = 7.0 ± 4.5 or ± 2.0 [V]
(shown in the right figure)
Vcom = 6.6V
2.0V
7.0V
2.0V
4.5V
0V
Vsig waveform
7. Cross talk
Cross talk is determined by the luminance differences between adjacent areas represented Wi' and Wi (i = 1
to 4) around black window (Vsig = 4.5V/1V).
W1
W1'
W2
W4
W2'
W4'
W3
Cross talk CTK =
W3'
– 13 –
Wi' – Wi
Wi
× 100 [%]
LCX007BNB
Viewing angle characteristics
90
CR = 5
10
Phi
20
50
200
100
150
0
180
10
30
50
70
Theta
270
θ0°
Z
Marking
θ
φ90°
φ
φ180°
X
φ270°
– 14 –
Y
φ0°
Measurment method
LCX007BNB
Optical transmittance of LCD panel (Typical Value)
20
Trans. [%]
15
10
5
0
400
500
600
700
Wavelength [nm]
Measurement method: Measurement system II
– 15 –
3 dots
– 16 –
480 dots
(Effective 16.800mm)
3 dots
479
480
4
3
2
1
DL2
DL3
DL4
1
2
356
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
ODD = 1069 dots
EVEN = 1068 dots
(Effective 29.918mm)
DR1
DR2
DR3
DR4
GATE SW GATE SW GATE SW GATE SW GATE SW
357
ODD = 13 dots
EVEN = 13 dots
R G B
R G B R G B
R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B
R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B
R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B
R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B
R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B
R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B
R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B
R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B
R G B
R G B R G B
R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
AA
AA
AA
AA
AA
AA
AA
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
DL1
ODD = 13 dots
EVEN = 14 dots
ODD = 1094 dots
EVEN = 1095 dots
Description of Operation
1. Dot Arrangement (1) (16:9 display)
The dots are arranged in a delta pattern. The shaded area is used for the dark border around the display.
The R corresponds to SIG2, G to SIG1, and B to SIG3, respectively.
LCX007BNB
3 dots
– 17 –
480 dots
(Effective 16.800mm)
3 dots
479
480
4
3
2
1
DL2
DL3
1
2
Side Black
44
45
46
47
48
312
313
314
Side Black
ODD = 135 dots
EVEN = 134 dots
356
357
DR1
DR2
DR3
ODD = 13 dots
EVEN = 13 dots
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
311
4 : 3 Area
ODD = 799 dots
EVEN = 800 dots
(Effective 22.386mm)
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
DL4
ODD = 135 dots
EVEN = 134 dots
DR4
GATE SW
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B R G B R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B R G B R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B R G B R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B R G B R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B R G B R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B R G B R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B R G B R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B
R G B
R G B
R G B
R G B R G B R G B R G B R G B R G B R G B R G B
R G B
R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
GATE SW GATE SW GATE SW
DL1
ODD = 13 dots
EVEN = 14 dots
ODD = 1094 dots
EVEN = 1095 dots
Dot Arrangement (2) (4:3 display)
The dots are arranged in a delta pattern. The shaded area is used for the dark border around the display.
The R corresponds to SIG2, G to SIG1, and B to SIG3, respectively.
LCX007BNB
LCX007BNB
2. LCD Panel Operations
[Description of basic operations]
The basic operations of the LCD panel are shown below based on the wide-display mode.
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 480 gate lines sequentially in every horizontal scanning period.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 1068.5 signal electrodes sequentially in a single horizontal scanning period.
• Vertical and horizontal shift registers address one pixel, and then turn on Thin Film Transistors (TFTs; two
TFTs) to apply a video signal to the dot. The same procedures lead to the entire 480 × 1068.5 dots to display
a picture in a single vertical scanning period.
• The LCD pixel dots are arranged in a delta pattern, where the dots connected to the identical signal line are
positioned with 1.5-dot offset against those of the adjacent horizontal line. Horizontal Start Pulse (HST) is
generated with 1.5-bit offset between the horizontal lines to regulate the above offset. HCK and sample-hold
(S/H) pulses follow the same 1.5-bit offset scheme.
• The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While
maintaining the CLR at High level, the VVDD potential drops to approximately 9.5V. This pin shall be
grounded when not in use.
• The video signal shall be input with polarity-inverted system in every horizontal cycle.
• Timing diagrams of the vertical and the horizontal display cycle are shown below:
(1) Vertical display cycle
VD
VST
VCK
1
2
480
Vertical display cycle 480H
(2) Horizontal display cycle (16:9)
BLK
HST
356
HCK1
1
2
3
4
5
6
357
HCK2
Horizontal display cycle
(3) Horizontal display cycle (4:3)
BLK
HST
267
HCK1
1
2
3
4
5
6
268
HCK2
Horizontal display cycle
– 18 –
LCX007BNB
[Description of operating mode]
The LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
• 4:3 display mode with side-black display
These modes are controlled by three signals (RGT, DWN, and WID). The setting mode is shown below:
WID RGT
Mode
DWN
Mode
H
H
16:9 right scan
H
Down scan
H
L
16:9 left scan
L
Up scan
L
H
4:3 right scan
L
L
4:3 left scan
The direction of the right/left and/or up/down mean when Pin 1 marking is located at right side with the pin
block upside.
• The analog signal (SID) to display side-black shall be input by 1H inversion synchronized with the signal.
SIG2
S/H
S/H
CK2
CK3
SIG1
SIG3
S/H
S/H
CK1
CK3
S/H
AC Amp
3
SIG2
AC Amp
2
SIG1
AC Amp
4
SIG3
CK3
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK2
CK1
CK3
– 19 –
LCX007BNB
3. 3-dot Simultaneous Sampling
Horizontal driver samples SIG1, SIG2 and SIG3 signal simultaneously, which requires the phase matching
between SIG1, SIG2, and SIG3 signals to prevent horizontal resolution from deteriorating. Thus phase
matching between each signal is required using an external signal delaying circuit before applying video
signal to the LCD panel.
The block diagram of the delaying procedure using sample-and-hold method is as follows.
The LCX007 has the right/left inverse function. The following phase relationship diagram indicates the phase
setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be
inverted between SIG2 and SIG3 signals.
LCX007BNB
Display System Block Diagram
An example of display system is shown below.
SID
SIG2 ∗
SIG2
SIG1 ∗
RGB Driver
CXA1819Q
SIG1
SIG3 ∗
SIG3
COM
∗ The SIG1, 2, 3 and
H SYNC signals with
double-speed processing
shall be applied to those
pins in the NTSC/PAL
modes.
FRP
SH
HST
HCK1
HSYNC ∗
HCK2
VSYNC
VST
TG
CXD2412AQ
VCK
PCG
ENB
CLR
WID
RGT
DWN
– 20 –
LCD Panel
LCX007BNB
LCX007BNB
Reliability test conditions
Items
Test conditions
Time
High temperature
operation
Ta = 70°C
HVDD = 15.7V
VVDD = 15.7V
250h
High temperature storage
Ta = 85°C
250h
High temperature & high
humidity storage
Ta = 40°C
95% RH
250h
Temperature cycle
Ta = –30 to +85°C
10cy
Vibration
X, Y, Z, 1.5mm
10 to 55Hz (1min. reciprocation)
20min. for each
direction
Anti-electrostatic discharge test results
Conditions: C = 200pF, Rs = 0Ω
Result:
Breakdown
voltage
Up to 100V
101 to 200V
+
–
–
–
–
Pin 8
Pins except pin no.8 have the strength more than 200V.
– 21 –
Panel appearance
and performance
after those tests must
conform with the
standards.
LCX007BNB
Important
(1) Direction of incident light
Allow incident light to hit upon an opposite side of a mark-indicated surface.
Direction of incidence
Marking side
(2) Polarizer
This LCD is attached with a polarizer. A suitable heat-dissipation method shall be incorporated to suppress
optical degradation of a polarizer.
(3) Light source
• Use visible light (wavelength λ = 400 to 780nm) as a light source. Do not use a light source containing
infrared or ultraviolet components.
• Suppress leakage light (reflection light) into a backside of a panel to sufficiently weak level or shut it out
completely.
– 22 –
LCX007BNB
Notes on Handling
(1) Static charge prevention
Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mat on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Handle in clean environment.
b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet.
Peel off the protective sheet carefully not to damage the panel.
c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stain on the surface.
d) Use ionized air to blow off dust at a panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or a panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in
panel damages.
g) Minimum bent radius rating for flexible substrates is 1mm.
h) Panel screw torque should not exceed 3kg · cm.
– 23 –
LCX007BNB
Package Outline
Unit: mm
Except cover 3.4 ± 0.1
Thickness of the connector 0.3 ± 0.05
21.0 ± 0.15
9.75 ± 1.5
1.8 ± 0.1
31.4 ± 0.2
4.55 ± 0.1
1
(40.5)
(42.5)
4
3
Active Area
5
2
6
Incident
light
Polarizing
Axis
30.75 ± 0.2
34.0 ± 0.2
36.0 ± 0.15
76.5 ± 1.3
0.5
2-R
2-φ3.5
20.25 ± 0.25
40.5 ± 0.15
7
2.0 ± 0.1
0
φ2.5 – 0.1
(16.8)
(29.9)
13.6 ± 0.25
6
No
1.5 ± 0.15
P 1.0 × 19 = 19.0 ± 0.1
PIN20
PIN1
0.5 ± 0.15
1.0 ± 0.15
4.0 ± 0.3
1
0.6 ± 0.05
Description
F P C
2
Molding material
3
Outside frame
4
Reinforcing board
5 Reinforcing material
electrode (enlarged)
The rotation angle of the active area relative to H and V is ± 1°.
– 24 –
6
Polarizing film
7
Cover
weight 7g