LCX017DLT
4.6cm (1.8 Type) Black-and-White LCD Panel
Description
The LCX017DLT is a 4.6cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with a built-in peripheral
driving circuit. Use of three LCX017DLT panels
provides a full-color representation. The striped
arrangement suitable for data projectors is capable
of displaying fine text and vertical lines.
The adoption of DMS (Dual Metal Shield) structure
realizes a high luminance screen. And new cross
talk free and ghost free structures contribute to high
picture quality.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing and
control signals.
The panel contains an active area variable circuit
which supports S-XGA 5:4 and PC-98 8:5 data
signals by changing the active area according to the
type of input signal.
Features
• Number of active dots: 786,432 (1.8 Type, 4.6cm in diagonal)
• Accepts the computer requirements of XGA, SVGA, VGA, NTSC and PAL
• Supports SXGA with simple display
• High optical transmittance: 23% (typ.)
• New high light resistance DMS (Dual Metal Shield) structure adopted
• New cross talk free and ghost free structures
• High contrast ratio with normally white mode: 350 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• Up/down and/or right/left inverse display function
• Antidust glass used
Element Structure
• Dots: 1024 (H) × 768 (V) = 786,432
• Built-in peripheral driver using polycrystalline silicon super thin film transistors
Applications
• Liquid crystal data projectors
• Liquid crystal rear-projector TVs, etc.
∗ The company's name and product's name in this data sheet is a trademark or a registered trademark of each company.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00212A15
VCK
24 29 26
Input Signal
Level Shifter
Circuit
VB
HVDD
VVDD
Vss
VSIG1
VSIG2
15
30 20
3
4
–2–
7
8
9 10 11 12 13 14 31
COM
PAD
H Shift Register (Bidirectional Scanning)
Side-Black Control Circuit
COM
VSIG12
VSIG11
VSIG10
VSIG9
VSIG7
VSIG8
6
VSIG5
5
VSIG6
VSIG3
HB
27 28
VSIG4
ENB
DWN
23
V Shift Register
(Bidirectional Scanning)
VST
25
PCG
RGT
BLK
22 16
Black Frame Control Circuit
19 18
HCK2
17
Black Frame Control Circuit
HCK1
21 2
Precharge Control
Circuit
VSSGR
HST
PSIG
VSSGL
1
V Shift Register
(Bidirectional Scanning)
Up/Down and/or Right/Left
Inversion Control Circuit
LCX017DLT
Block Diagram
LCX017DLT
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage
HVDD
• V driver supply voltage
VVDD
• Common pad voltage
COM
• H shift register input pin voltage HST, HCK1, HCK2,
RGT
• V shift register input pin voltage VST, VCK, PCG,
BLK, ENB, DWN
HB, VB
• Video signal input pin voltage
SIG1 to 12, PSIG
• Operating temperature∗
Topr
• Storage temperature
Tstg
∗ Panel temperature inside the antidust glass
–1.0 to +20
–1.0 to +20
–1.0 to +17
–1.0 to +17
V
V
V
V
–1.0 to +17
V
–1.0 to +15
–10 to +70
–30 to +85
V
°C
°C
Operating Conditions (VSS = 0V)
• Supply voltage
13.5 ± 0.5V
HVDD
VVDD
15.5 ± 0.5V
• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)
Vin
5.0 ± 0.5V
–3–
LCX017DLT
Pin Description
Pin
No.
Symbol
Description
1
PSIG
Uniformity improvement signal
2
VSSGR
GND for right V gate
3
VSIG1
Video signal 1 to panel
4
VSIG2
Video signal 2 to panel
5
VSIG3
Video signal 3 to panel
6
VSIG4
Video signal 4 to panel
7
VSIG5
Video signal 5 to panel
8
VSIG6
Video signal 6 to panel
9
VSIG7
Video signal 7 to panel
10
VSIG8
Video signal 8 to panel
11
VSIG9
Video signal 9 to panel
12
VSIG10
Video signal 10 to panel
13
VSIG11
Video signal 11 to panel
14
VSIG12
Video signal 12 to panel
15
HVDD
Power supply for H driver
16
RGT
Drive direction pulse for H shift register (H: nomal, L: reverse)
17
HST
Start pulse for H shift register drive
18
HCK2
Clock pulse for H shift register drive 2
19
HCK1
Clock pulse for H shift register drive 1
20
VSS
GND (H, V drivers)
21
VSSGL
GND for left V gate
22
BLK
Input for PC98 mode
23
ENB
Enable pulse for gate selection
24
VCK
Clock pulse for V shift register drive
25
VST
Start pulse for V shift register drive
26
DWN
Drive direction pulse for V shift register (H: nomal, L: reverse)
27
HB
Display switch for S-XGA
28
VB
Display switch for PC98 mode
29
PCG
Improvement pulse for uniformity
30
VVDD
Power supply for V driver
31
COM
Common voltage of panel
32
TEST
Test pin, leave this pin open
–4–
LCX017DLT
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a
high resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.)
(1) VSIG1 to VSIG12, PSIG
HVDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
Input
Level conversion circuit
(2-phase input)
1MΩ
250Ω
250Ω
1MΩ
(3) RGT
HVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(4) HST
HVDD
250Ω
250Ω
Input
Level conversion circuit
(single-phase input)
1MΩ
(5) PCG, VCK
VVDD
250Ω
250Ω
Input
Level conversion circuit
(single-phase input)
1MΩ
(6) VST, BLK, ENB, DWN, HB, VB
VVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ ∗
∗ DWN is 400kΩ.
(7) COM
VVDD
Input
LC
1MΩ
(8) HVDD, VSSGR, VSSGL, VVDD
Input
are all Vss.
1MΩ
–5–
LCX017DLT
Input Signals
1. Input signal voltage conditions (VSS = 0V)
Item
Symbol
Min.
Typ.
Max.
Unit
H shift register input voltage (Low)
HST, HCK1, HCK2, RGT (High)
VHIL
–0.5
0.0
0.4
V
VHIH
4.5
5.0
5.5
V
V shift register input voltage (Low)
HB, VB, BLK, VST, VCK,
PCG, ENB, DWN
(High)
VVIL
–0.5
0.0
0.4
V
VVIH
4.5
5.0
5.5
V
Video signal center voltage
VVC
6.9
7.0
7.1
V
Video signal input range∗1
Vsig
VVC – 4.5
7.0
VVC + 4.5
V
Common voltage of panel∗2
Vcom
VVC – 0.5
VVC – 0.4
VVC – 0.3
V
Uniformity improvement signal
input voltage (PSIG)∗3
VpsigB
VVC ± 4.4
VVC ± 4.5
VVC ± 4.6
VpsigG
VVC ± 1.8
VVC ± 1.9
VVC ± 2.0
∗1
∗2
∗3
V
Input video signal shall be symmetrical to VVC.
The typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value.
When the typical value is lowered, the maximum and minimum values may lower.
Input a uniformity improvement signal PSIG in the same polarity with video signals VSIG1 to VSIG12 and
which is symmetrical to VVC. PSIG wave form is 2 steps like below, in the upper chart, upper shows signal
level of the 1st step, lower shows signal level of the 2nd step. Also, the rising and falling of PSIG are
synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed
within 450ns (as shown in a diagram below).
Input waveform of uniformity improvement signal PSIG
90%
PsigB
PSIG
PsigG
VVC
10%
trPSIG
tfPSIG
PCG
PRG∗4
∗4
PRG shows the time of the 1st step of PSIG signal, and it is not input to the panel.
Level Conversion Circuit
The LCX017DLT has a built-in level conversion circuit in the clock input unit on the panel. The input signal
level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
–6–
LCX017DLT
2. Clock timing conditions (Ta = 25°C)
(XGA mode: fHckn = 3.9MHz, fVck = 34.3kHz)
Item
HST
VST
VCK
ENB
PCG
PRG∗4
BLK∗5
∗5
∗6
Min.
Typ.
Max.
Hst rise time
trHst
—
—
30
Hst fall time
tfHst
—
—
30
Hst data set-up time
tdHst
55
65
75
Hst data hold time
thHst
55
65
75
trHckn
—
—
30
Hckn fall time∗5
tfHckn
—
—
30
Hck1 fall to Hck2 rise time
to1Hck
–15
0
15
Hck1 rise to Hck2 fall time
to2Hck
–15
0
15
Vst rise time
trVst
—
—
100
Vst fall time
tfVst
—
—
100
Vst data set-up time
tdVst
2
7
12
Vst data hold time
thVst
2
7
12
Vck rise time
trVck
—
—
100
Vck fall time
tfVck
—
—
100
Enb rise time
trEnb
—
—
100
Enb fall time
tfEnb
—
—
100
Horizontal video period completed to Enb fall time
tdEnb
760
800
—
Enb rise to PRG∗4 fall time
toPRG∗4
110
120
130
Enb fall to Pcg rise time
toPcg
830
1000
—
Enb pulse width
twEnb
1650
—
—
Pcg rise time
trPcg
—
—
30
Pcg fall time
tfPcg
—
—
30
Pcg rise to Vck rise/fall time
toVck
–100
0
100
Pcg fall to horizontal video period start time
toVideo
170
200
—
Pcg pulse width
twPcg
1400
1700
—
PRG∗4 rise to Pcg rise time
toPcgr
–10
0
10
PRG∗4
toPcgf
570
700
—
PRG∗4 pulse width
twPRG∗4
830
1000
—
Blk rise time
trBlk
—
—
100
Blk fall time
tfBlk
—
—
100
Blk rise to Enb fall time
toEnb
2
1
0
Blk fall to Pcg rise time
toPcg
–1
0
1
Hckn rise
HCK
Symbol
time∗5
fall to Pcg fall time
Hckn means Hck1 and Hck2.
Blk is the timing during PC98 mode, which keeps "H" level in other modes.
–7–
Unit
ns
µs
ns
µs
LCX017DLT
<Horizontal Shift Register Driving Waveform>
Item
Hst rise time
Symbol
Waveform
90%
trHst
Hst
HST
Hst fall time
tfHst
Hst data set-up time
tdHst
Conditions
90%
10%
10%
trHst
∗7
tfHst
50%
50%
Hst
Hck1
Hst data hold time
50%
50%
thHst
tdHst
Hckn rise time∗5
∗5
Hckn fall time∗5
tfHckn
Hck1 fall to Hck2 rise time
to1Hck
10%
trHckn
∗7
HCK
90%
10%
Hckn
50%
to2Hck
50%
50%
Hck2
to2Hck
∗7
tfHckn
Hck1
50%
Hck1 rise to Hck2 fall time
to1Hck
Definitions: The right-pointing arrow (
) means +.
The left-pointing arrow (
) means –.
The black dot at an arrow (
) indicates the start of measurement.
–8–
• Hckn∗5
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
thHst
90%
trHckn
• Hckn∗5
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
• Hckn∗5
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
LCX017DLT
<Vertical Shift Register Driving Waveform>
Item
Vst rise time
Symbol
Waveform
90%
trVst
Vst
Vst fall time
VST
Conditions
90%
10%
tfVst
10%
trVst
tfVst
∗7
Vst data set-up time
50%
tdVst
50%
Vst
50%
50%
Vck
Vst data hold time
Vck rise time
thVst
trVck
Vck fall time
tfVck
Enb rise time
trEnb
thVst
90%
90%
10%
Vck
VCK
tdVst
10%
trVckn
90%
10%
tfVckn
90%
10%
Enb
Enb fall time
tfEnb
Horizontal video period
completed to Enb fall time
tdEnb
tfEnb
H. Video period H. Blanking period
∗7
ENB
Enb rise to PRG∗4 fall time
toPRG∗4
Enb fall to Pcg rise time
toPcg
trEnb
twEnb
50%
Enb
PRG∗4
tdEnb
50%
toPRG∗4
toPcg
PCG
Enb pulse width
50%
twEnb
–9–
50%
50%
LCX017DLT
Item
Pcg rise time
Symbol
Waveform
trPcg
90%
Pcg
PCG∗8
Pcg fall time
tfPcg
Pcg rise to Vck rise/fall
time
toVck
Conditions
90%
10%
10%
trpcg
tfpcg
H. blanking period
∗7
H. video period
twPcg
Pcg fall to horizontal
video period start time
toVideo
Pcg
50%
toVideo
50%
toVck
50%
Vck
Pcg pulse width
twPcg
PRG∗4 rise to Pcg rise time toPcgr
twPRG∗4
∗7
toPcgf
PRG∗4
∗8
∗4
PRG∗4 PRG fall to Pcg fall time
50% 50%
toPcgf
toPcgr
Pcg
PRG∗4 pulse width
twPRG∗4
Blk rise time
trBlk
50%
50%
tfBlk
trBlk
90%
90%
10%
10%
Blk fall time
tfBlk
Blk rise to Enb fall time
toEnb
∗7
BLK
toPcg
Blk fall to Pcg rise time
∗8
toPcg
50%
Blk 50%
Pcg
toEnb
50%
50%
Enb
PCG input pin and PRG∗4 should be "H" level during the horizontal 1H period, where the above BLK is low
more than 10ns.
– 10 –
LCX017DLT
Electrical Characteristics (Ta = 25°C, HVDD = 13.5V, VVDD = 15.5V)
1. Horizontal drivers
Item
Input pin capacitance
Input pin current
Symbol
Min.
Typ.
Max.
Unit
Condition
HCKn
CHckn
—
30
35
pF
HST
CHst
—
35
40
pF
HCK1
–500
–220
—
µA
HCK1 = GND
HCK2
–1000 –390
—
µA
HCK2 = GND
HST
–500
–120
—
µA
HST = GND
RGT
–150
–30
—
µA
RGT = GND
Video signal input pin capacitance
Csig
—
200
250
pF
Current consumption
IH
—
14.0
20.0
mA
HCKn: HCK1, HCK2 (3.9MHz)
Min.
Typ.
Max.
Unit
Condition
2. Vertical drivers
Item
Input pin capacitance
Input pin current
Symbol
VCK
CVck
—
15
20
pF
VST
CVst
—
15
20
pF
–1000 –180
—
µA
VCK = GND, PCG = GND
–150
–40
—
µA
VST, ENB, DWN,BLK, HB
VB = GND
—
4.0
6.0
mA
VCK: (34.3kHz)
Min.
Typ.
Max.
Unit
—
250
400
mW
Symbol
Min.
Typ.
Max.
Unit
Rpin
0.4
1
—
MΩ
Min.
Typ.
Max.
Unit
—
13
16
nF
Symbol
Min.
Typ.
Max.
Unit
COM
—
20
25
nF
VCK,PCG
VST, ENB, DWN, BLK, HB,
VB
Current consumption
IV
3. Total power consumption of the panel
Item
Symbol
Total power consumption of the panel PWR
4. Pin input resistance
Item
Pin – VSS input resistance
5. Uniformity improvement signal
Item
Symbol
Input pin capacitance for uniformity
CPSIGo
improvement signal
6. COM pin capacitance
Item
COM pin capacitance
– 11 –
LCX017DLT
Electro-optical Characteristics
(XGA mode)
Item
Symbol Measurement method Min.
Typ.
Max.
Unit
Contrast ratio
25°C
CR
1
200
350
—
—
Optical transmittance
25°C
T
2
20
23
—
%
RV90-25
0.7
1.1
1.5
GV90-25
0.9
1.3
1.6
BV90-25
1.0
1.4
1.7
RV90-60
0.7
1.1
1.4
GV90-60
0.8
1.2
1.5
BV90-60
1.0
1.4
1.7
RV50-25
1.1
1.5
1.8
GV50-25
1.2
1.6
1.9
1.3
1.7
2.0
RV50-60
1.1
1.5
1.8
GV50-60
1.2
1.6
1.9
BV50-60
1.3
1.7
2.0
RV10-25
1.6
2.0
2.3
GV10-25
1.7
2.1
2.4
BV10-25
1.8
2.2
2.5
RV10-60
1.6
2.0
2.3
GV10-60
1.7
2.1
2.4
BV10-60
1.8
2.2
2.5
0°C
ton0
—
37
80
25°C
ton25
—
17
40
0°C
toff0
—
100
200
25°C
toff25
—
30
70
Flicker
60°C
F
5
—
–65
–40
dB
Image retention time
25°C
YT60
6
—
0
—
s
Cross talk
25°C
CTK
7
—
—
5
%
25°C
V90
60°C
25°C
V-T
characteristics
BV50-25
V50
60°C
25°C
V10
60°C
ON time
Response time
OFF time
3
4
V
ms
Reflection Preventive Processing
When a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a
polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. This
prevents characteristic deterioration caused by luminous reflection.
– 12 –
LCX017DLT
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 13.5V, VVDD = 15.5V
VVC = 7.0V, Vcom = 6.6V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Two types of measurement systems are used as shown below.
(5) Video input signal voltage (Vsig)
(VAC = signal amplitude)
Vsig = 7.0 ± VAC [V]
• Measurement system I
Approx. 2000mm
Screen
Luminance
Meter
Measurement
Equipment
LCD Projector
Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or equivalent
Projection lens: Focal distance 80mm, F1.9
Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500)
(× 24, Sensor area: 7mmφ)
Polarizer: Side of incidence - Nitto Denko’s EG-1224DU or Polatechno’s SKN-18242T or equivalent
Side of output light - Polatechno’s SHC-128 or equivalent
• Measurement system II
Optical fiber
Light receptor lens
Light Detector
Measurement
Equipment
Polarizer
LCD panel
Drive Circuit
Polarizer
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
CR =
L (White)
... (1)
L (Black)
L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the center of the screen at VAC = 4.5V.
Both luminosities are measured by System I.
– 13 –
LCX017DLT
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
T=
White luminance
Luminance of light source
× 100 [%] ... (2)
3. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
correspond to the voltages which define 90%, 50%,
and 10% of transmittance respectively.
Transmittance [%]
"White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V
on Measurement System I.
90
50
10
V90
V50 V10
VAC – Signal amplitude [V]
4. Response Time
Response time ton and toff are defined by
formulas (5) and (6) respectively.
ton = t1 – tON ...(5)
toff = t2 – tOFF ...(6)
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
Input signal voltage (Waveform applied to the measured pixels)
4.5V
0.5V
7.0V
0V
Optical transmittance output waveform
100%
90%
10%
0%
tON
t1
ton
– 14 –
tOFF
t2
toff
LCX017DLT
5. Flicker
Flicker (F) is given by formula (7). DC and AC (XGA/NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the
panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
F [dB] = 20log
∗ Each input signal voltage for gray raster mode
is given by Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives
50% of transmittance in V-T characteristics.
component
{ AC
} ...(7)
DC component
6. Image Retention Time
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 7.0 ± VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention,
measure the time till the residual image becomes indistinct.
∗ Monoscope signal conditions:
Vsig = 7.0 ± 4.5 or ± 2.0 [V]
(shown in the right figure)
Vcom = 6.6V
Black level
4.5V
White level
2.0V
7.0V
2.0V
4.5V
0V
Vsig waveform
7. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and
Wi (i = 1 to 4) around a black window (Vsig = 4.5 V/1V).
W2
W1 W1'
W2'
Cross talk value CTK = Wi' – Wi × 100 [%]
Wi
W4
W4'
W3 W3'
– 15 –
LCX017DLT
Viewing angle characteristics (Typical Value)
90
AA
AAAA
AAAA
AA
CR = 5
10
Phi
20
50
100
180
150
0
250
10
200
30
50
70
Theta
270
θ0°
Z
Marking
θ
φ90°
φ
φ180°
X
φ270°
– 16 –
Y
φ0°
Measurement method
– 17 –
4 dots
Photo-Shielding
Gate SW
Active area
1032dots
1024 dots (Effective 36.86mm)
Gate SW
4 dots
2 dots
768 dots (Effective 27.65mm)
2 dots
1. Dot Arrangement
The dots are arranged in a stripe. The shaded area is used for the dark border around the display.
LCX017DLT
772 dots
LCX017DLT
2. LCD Panel Operations
[Description of basic operations]
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 768 gate lines sequentially in a single horizontal scanning period. (XGA mode)
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 1024 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn
on to apply a video signal to the dot. The same procedures lead to the entire 768 × 1024 dots to display a
picture in a single vertical scanning period.
• The data and video signals shall be input with the 1H-inverted system.
[Description of operating mode]
This LCD panel can change the active area by displaying a black frame to support various computer or video
signals. The active area is switched by HB, VB and BLK. However, the center of the screen is not changed.
The active area setting modes are shown below.
∗1
∗2
HB
VB
BLK
Screen aspect ratio
H
H
H
4:3
1024 × 768
L
H
H
5:4∗2
960 × 768
H
L
∗1
8:5
1024 × 640
Input BLK pulse (refer to drive waveform and vertical blanking period of PC98 made).
For only aspect ratio 5:4 mode, set Psig and COM voltage as shown below. The value of PsigG and COM
voltage is typical value. It is necessary to optimize the voltage for each set construction.
VVC + 4.5 [V]
VVC + 1.0 [V]
VVC
Psig
Psig B
Psig G
VVC – 1.0 [V]
VVC – 4.5 [V]
PRG∗3
VCOM + 2.0
VCOM
COM
VCOM – 2.0
∗3 PRG shows the time of the 1st step of Psig signal, and it is not input to the panel.
– 18 –
LCX017DLT
This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are
shown below.
RGT
Mode
DWN
Mode
H
Right scan
H
Down scan
L
Left scan
L
Up scan
Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin
block upside.
To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for
both the H and V systems must be varied. The phase relationship between the start pulse and the clock for
each mode is shown below.
(1) Vertical direction display cycle
(DWN = H, L)
(1.1) XGA, SXGA
VD
VST
VCK
1
2
3
4
765 766 767 768
Vertical display cycle 768H
(1.2) PC98
VD
VST
VCK
1
2
3
4
637 638 639 640
Vertical display cycle 640H
– 19 –
LCX017DLT
(2) Horizontal direction display cycle
(2.1.1) XGA, PC98 (RGT = H)
HD
HST
HCK1
1
2
3
4
HCK2
83
84
85
86
Horizontal display cycle
(2.1.2) XGA, PC98 (RGT = L)
HD
HST
HCK1
1
2
3
HCK2
4
83
84
85
86
Horizontal display cycle
(2.2.1) SXGA (RGT = H)
HD
HST
HCK1
1
2
3
HCK2
4
77
78
79
80
78
79
80
Horizontal display cycle
(2.2.2) SXGA (RGT = L)
HD
HST
HCK1
HCK2
1
2
3
4
77
Horizontal display cycle
– 20 –
LCX017DLT
(3) Vertical blanking cycle of PC98 mode
The input waveforms of PCG, PRG∗1 and PSIG should be changed as shown below when BLK pulse is input.
Vertical blanking cycle
BLK
VCK
ENB
PCG
PRG∗1
PSIG
∗1
PRG shows the period of PSIG black level, it is not input to the panel.
– 21 –
LCX017DLT
3. 12-dot Simultaneous Sampling
The horizontal shift register samples signals VSIG1 to VSIG12 simultaneously. This requires phase
matching between signals VSIG1 to VSIG12 to prevent the horizontal resolution from deteriorating. Thus,
phase matching between each signal is required using an external signal delaying circuit before applying
the video signal to the LCD panel.
VSIG1
S/H
CK1
VSIG2
S/H
CK2
VSIG3
S/H
CK3
VSIG4
S/H
CK4
VSIG5
S/H
CK5
VSIG6
S/H
CK6
VSIG7
S/H
S/H
3
VSIG1
S/H
4
VSIG2
S/H
5
VSIG3
S/H
6
VSIG4
S/H
7
VSIG5
S/H
8
VSIG6
S/H
9
VSIG7
S/H
10
VSIG8
S/H
11
VSIG9
S/H
12
VSIG10
S/H
13
VSIG11
S/H
14
VSIG12
CK7
VSIG8
VSIG9
S/H
CK8
S/H
CK9
VSIG10
S/H
CK10
S/H
VSIG11
CK11
VSIG12
CK12
– 22 –
LCX017DLT
The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following
phase relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT =
Low level), the phase settings for signals VSIG1 to VSIG12 are exactly reversed.
LCX017DLT
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK1
CK2
CK3
CK4
CK5
CK6
CK7
CK8
CK9
CK10
CK11
CK12
– 23 –
LCX017DLT
Display System Block Diagram
An example of display system is shown below.
CXA3512R
S/H Driver
6
CXA3512R
S/H Driver
6
CXA3512R
S/H Driver
6
LCX017
R
G
B
CXA2111R
Gamma
LCX017
CXA3512R
S/H Driver
6
CXA3512R
S/H Driver
6
PRG, CLP
L.P.F.
CXD3503R
Color Shading Correction
VST
LCX017
HSYNC
CXA3512R
S/H Driver
CXA3106AQ
PLL
ENB, PRG,
FRP
MCLK/2
DSYNC
VSYNC
6
CXD3500R
Timing Generator
– 24 –
Timing Pulses
LCX017DLT
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in a clean environment.
b) When delivered, the panel surface (glass panel) is covered by a protective sheet. Peel off the protective
sheet carefully so as not to damage the glass panel.
c) Do not touch the glass panel surface. The surface is easily scratched. When cleaning, use a cleanroom wiper with isopropyl alcohol. Be careful not to leave a stain on the surface.
d) Use ionized air to blow dust off the glass panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop the panel.
c) Do not twist or bend the panel or panel frame.
d) Keep the panel away from heat sources.
e) Do not dampen the panel with water or other solvents.
f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel
damages.
g) Minimum radius of bending curvature for a flexible substrate must be 1mm.
h) Torque required to tighten screws on a panel must be 0.294N · m or less.
i) Use appropriate filter to protect a panel.
j) Do not pressure the portion other than mounting hole (cover).
– 25 –
LCX017DLT
Package Outline
Unit: mm
5.4 ± 0.1
4
16.5 ± 0.05
Thickness of the connector 0.3 ± 0.05
2.35 ± 0.1
Incident light
Polarizing Axis
2
3
5
6
107.6 ± 1.4
50.0 ± 0.1
3-φ2.3 ± 0.05
C0.8
56.0 ± 0.15
3.0
4-R
(51.6)
1
7
Incident
light
Output light
Polarizing Axis
Active Area
9
3.0 ± 0.1
25.0 ± 0.25
(36.9)
(27.6)
2.2 ± 0.1
8
φ2.2 ± 0.1
25.0 ± 0.25
40.0 ± 0.1
No
5.0 ± 0.1
50.0 ± 0.15
P 0.5 ± 0.02 × 31 = 15.5 ± 0.03
0.5 ± 0.1
0.35 ± 0.03
PIN1
4.0 ± 0.4
0.5 ± 0.15
1
PIN32
Description
F P C
2
Molding material
3
Outside frame
4
Reinforcing board
5 Reinforcing material
electrode (enlarged)
The rotation angle of the active area relative to H and V is ± 1°.
6
Glass 1
7
Glass 2
8
Cover 1
9
Cover 2
Mass 25g
– 26 –
Sony Corporation