LCX021AM
4.1cm (1.6-inch) LCD Panel (with microlens)
For the availability of this product, please contact the sales office.
Description
The LCX021AM is a 4.1cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral driving
circuit. This panel allows full-color representation
without color filters through the use of a microlens.
The striped arrangement suitable for data projectors
is capable of displaying fine text and vertical lines.
The adoption of an advanced on-chip black matrix
realizes high picture quality by incorporating a high
luminance screen, cross-talk free and ghost free
circuits.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing and
control signals.
The panel contains an active area variable circuit
which supports SVGA 4:3/PC98∗1 8:5 data signals
by changing the active area according to the type of
input signal.
∗1 "PC98" is a trademark of NEC Corporation.
Features
• The number of active dots: 1,456,000 (1.6-inch; 4.1cm in diagonal)
• Supports SVGA (804 × 3 × 604) and PC98∗1 (804 × 3 × 500)
• Effective aperture ratio: 70% (reference value)
• Built-in cross talk free and ghost free circuits
• High contrast ratio with normally white mode: 150 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• Up/down and/or right/left inverse display function
Element Structure
• Dots: 804 × 3 (H) × 604 (V) = 1,456,848
• Built-in peripheral driver using polycrystalline silicon super thin film transistors
Applications
• Liquid crystal data projectors
• Liquid crystal projectors
• Liquid crystal rear projection TV, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98501A94-PS
PSIGR
5
PSIGG
4
PSIGB
3
Block Diagram
Up/Down and/or Right/Left
Inversion Control Circuit
28 30
27
Input Signal
Level
Shifter Circuit
HCK2
HCK1
HST
DWN
34 26
V Shift Register
(Bidirectional Scanning)
Black Frame Control Circuit
RGT
25
Precharge
Control Circuit
–2–
BLK
ENB
VCK
MODE
36
PCG
33 35
VST
6
HVDD
SIGB1
TEST
24 37 29 38
H Shift Register (Bidirectional Scanning)
31 32
7
8
COM
PAD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 39
Black Frame Control Circuit
V Shift Register
(Bidirectional Scanning)
VVDD
VSS
SIGB2
SIGB3
SIGB4
SIGB5
SIGB6
SIGG1
SIGG2
SIGG3
SIGG4
SIGG5
SIGG6
SIGR1
SIGR2
SIGR3
SIGR4
SIGR5
SIGR6
COM
LCX021AM
LCX021AM
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage
HVDD
• V driver supply voltage
VVDD
• Common pad voltage
COM
• H shift register input pin voltage HST, HCK1, HCK2,
RGT
• V shift register input pin voltage VST, VCK, PCG,
BLK, ENB, DWN, MODE
• Video signal input pin voltage
SIGB1, SIGB2, SIGB3, SIGB4,
SIGB5, SIGB6, SIGG1, SIGG2,
SIGG3, SIGG4, SIGG5, SIGG6,
SIGR1, SIGR2, SIGR3, SIGR4,
SIGR5, SIGR6, PSIGB, PSIGG,
PSIGR
• Operating temperature
Topr
• Storage temperature
Tstg
–1.0 to +20
–1.0 to +20
–1.0 to +17
–1.0 to +17
V
V
V
V
–1.0 to +17
V
–1.0 to +15
V
–10 to +70
–30 to +85
°C
°C
Operating Conditions (VSS = 0V)
• Supply voltage
HVDD
15.5 ± 0.5V
VVDD
15.5 ± 0.5V
• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)
Vin
5.0 ± 0.5V
–3–
LCX021AM
Pin Description
Pin
No.
Symbol
Description
Pin
No.
Symbol
Description
1
NC
Leave this pin open.
21
SIGR4
Video signal R4 to panel
2
NC
Leave this pin open.
22
SIGR5
Video signal R5 to panel
3
PSIGB
Blue uniformity improvement
signal
23
SIGR6
Video signal R6 to panel
4
PSIGG
Green uniformity improvement
signal
24
HVDD
Power supply for H driver
5
PSIGR
Red uniformity improvement
signal
25
RGT
Drive direction pulse for V shift
register (H: normal, L: reverse)
6
SIGB1
Video signal B1 to panel
26
HST
Start pulse for H shift register
drive
7
SIGB2
Video signal B2 to panel
27
HCK1
Clock pulse 1 for H shift register
drive
8
SIGB3
Video signal B3 to panel
28
HCK2
Clock pulse 2 for H shift register
drive
9
SIGB4
Video signal B4 to panel
29
VSS
GND (H, V drivers)
10
SIGB5
Video signal B5 to panel
30
BLK
Black frame display pulse
11
SIGB6
Video signal B6 to panel
31
ENB
Enable pulse for gate selection
12
SIGG1
Video signal G1 to panel
32
VCK
Clock pulse for V shift register
drive
13
SIGG2
Video signal G2 to panel
33
VST
Start pulse for V shift register
drive
14
SIGG3
Video signal G3 to panel
34
DWN
Drive direction pulse for V shift
register (H: normal, L: reverse)
15
SIGG4
Video signal G4 to panel
35
PCG
Improvement pulse for uniformity
16
SIGG5
Video signal G5 to panel
36
MODE
Display area switching
(H: SVGA, L: PC98)
17
SIGG6
Video signal G6 to panel
37
VVDD
Power supply for V driver
18
SIGR1
Video signal R1 to panel
38
TEST
Test; Open
19
SIGR2
Video signal R2 to panel
39
COM
Common voltage of panel
20
SIGR3
Video signal R3 to panel
40
NC
Leave this pin open.
Note) RGB video signals of Pins 6 to 23 is an example. The order of RGB can be changed.
–4–
LCX021AM
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except video signal inputs. All pins are connected to VSS with a high
resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.)
(1) SIGB1, SIGB2, SIGB3, SIGB4, SIGB5, SIGB6, SIGG1, SIGG2, SIGG3, SIGG4, SIGG5, SIGG6,
SIGR1, SIGR2, SIGR3, SIGR4, SIGR5, SIGR6, PSIGB, PSIGG, PSIGR
HVDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
Input
Level conversion circuit
(2-phase input)
1MΩ
250Ω
(3) RGT
250Ω
1MΩ
HVDD
2.5kΩ
2.5kΩ
Level conversion circuit
(single-phase input)
Input
1MΩ
(4) HST
HVDD
250Ω
250Ω
Level conversion circuit
(single-phase input)
Input
1MΩ
(5) PCG, VCK
VVDD
250Ω
250Ω
Level conversion circuit
(single-phase input)
Input
1MΩ
(6) VST, BLK, ENB, DWN, MODE
VVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(7) COM
VVDD
Input
LC
1MΩ
–5–
LCX021AM
Input Signals
1. Input signal voltage conditions (Vss = 0V)
Item
Symbol
Min.
Typ.
Max.
Unit
H shift register input voltage (Low)
HST, HCK1, HCK2, RGT
(High)
VHIL
–0.5
0.0
0.4
V
VHIH
4.5
5.0
5.5
V
V shift register input voltage (Low)
MODE, BLK, VST, VCK,
(High)
PCG, ENB, DWN
VVIL
–0.5
0.0
0.4
V
VVIH
4.5
5.0
5.5
V
Video signal center voltage
Video signal input range∗1
VVC
6.8
7.0
7.2
V
Vsig
VVC – 4.5
7.0
VVC + 4.5
V
Common voltage of panel∗2
Vcom
VVC – 0.5
VVC – 0.4
VVC – 0.3
V
Uniformity improvement signal input
voltage (PSIGB, PSIGG, PSIGR)∗3
Vpsig
VVC ± 4.3
VVC ± 4.5
VVC ± 4.7
V
∗1 Video input signal shall be symmetrical to VVC.
∗2 The typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the
typical value is lowered, the maximum and minimum values may lower.
∗3 Input a uniformity improvement signals PSIGB, PSIGG and PSIGR in the same polarity with video signals
SIGB1 to 6, SIGG1 to 6 and SIGR1 to 6 and which is symmetrical to VVC. Also, the rising and falling of
PSIGB, PSIGG and PSIGR are synchronized with the rising of PCG pulse, and the rise time trPSIG and fall
time tfPSIG are suppressed within 800ns (as shown in a diagram below).
PSIGB, PSIGG and PSIGR may change its suitable input voltage according to the drive conditions.
Uniformity Improvement Signals PSIGB, PSIGG and PSIGR Input Waveform
90%
VVC
PSIGB, G, R
10%
trPSIG
tfPSIG
PCG
Level Conversion Circuit
The LCX021AM has a built-in level conversion circuit in the clock input unit on the panel. The input signal level
increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
–6–
LCX021AM
2. Clock timing conditions (Ta = 25°C)
(SVGA mode: fHCKn = 4.0MHz, fVCK = 24.0kHz)
Item
HST
HCK
VST
VCK
ENB
PCG
BLK
Symbol
Min.
Typ.
Max.
Hst rise time
trHst
—
—
30
Hst fall time
tfHst
—
—
30
Hst data set-up time
tdHst
50
60
70
Hst data hold time
Hckn rise time∗4
thHst
50
60
70
trHckn
—
—
30
Hckn fall time∗4
tfHckn
—
—
30
Hck1 fall to Hck2 rise time
to1Hck
–15
0
15
Hck1 rise to Hck2 fall time
to2Hck
–15
0
15
Vst rise time
trVst
—
—
100
Vst fall time
tfVst
—
—
100
Vst data set-up time
tdVst
5
10
15
Vst data hold time
thVst
5
10
15
Vck rise time
trVck
—
—
100
Vck fall time
tfVck
—
—
100
Enb rise time
trEnb
—
—
100
Enb fall time
tfEnb
—
—
100
Vck rise/fall to Enb rise time
toEnb
400
500
—
Horizontal video period completed to Enb fall time
tdEnb
900
1000
—
Enb fall to Pcg rise time
toPcg
630
700
—
Pcg rise time
trPcg
—
—
30
Pcg fall time
tfPcg
—
—
30
Pcg rise to Vck rise/fall time
toVck
0
1000
1100
Pcg pulse width
twPcg
1100
1200
1300
Blk rise time
trBlk
—
—
100
Blk fall time
tfBlk
—
—
100
Blk fall to Vst rise time
toVst
1
—
2
Blk pulse width
twBlk
1
—
—
∗4 Hckn means Hck1 and Hck2.
–7–
Unit
ns
µs
ns
line
LCX021AM
<Horizontal Shift Register Driving Waveform>
Item
Hst rise time
Symbol
Waveform
90%
trHst
Hst
Hst fall time
HST
tfHst
tdHst
90%
10%
10%
trHst
∗5
Hst data set-up time
Conditions
tfHst
50%
50%
Hst
Hck1
Hst data hold time
50%
50%
thHst
tdHst
Hckn rise time∗3
∗3
Hckn fall time∗3
tfHckn
Hck1 fall to Hck2 rise time
to1Hck
10%
trHckn
∗5
HCK
90%
10%
Hckn
50%
tfHckn
50%
Hck1
50%
50%
Hck2
Hck1 rise to Hck2 fall time
to2Hck
to2Hck
to1Hck
∗5 Definitions: The right-pointing arrow (
) means +.
The left-pointing arrow (
) means –.
The black dot at an arrow (
) indicates the start of measurement.
–8–
• Hckn∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
thHst
90%
trHckn
• Hckn∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
• Hckn∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
LCX021AM
<Vertical Shift Register Driving Waveform>
Item
Vst rise time
Symbol
Waveform
90%
trVst
Vst
Vst fall time
VST
Conditions
90%
10%
tfVst
10%
trVst
tfVst
∗5
Vst data set-up time
tdVst
Vst data hold time
thVst
50%
50%
Vst
50%
50%
Vck
Vck rise time
trVck
Vck fall time
thVst
90%
90%
10%
Vck
VCK
tdVst
10%
tfVck
trVckn
Enb rise time
90%
trEnb
tfVckn
10%
10%
90%
Enb
Enb fall time
ENB
Vck rise/fall to Enb rise
time
tfEnb
tfEn
Horizontal
video period Horizontal blanking period
toEnb
Vck
50%
50%
Enb
Enb pulse width
trEn
twEnb
∗5
toEnb
50%
toPcg
tdEnb
Pcg
Pcg rise time
trPcg
Pcg fall time
tfPcg
Vck
toVck
PCG∗6 Pcg rise to Vck rise/fall
time
toVck
Pcg pulse width
trPcg
Blk rise time
twBlk
Blk fall time
tfBlk
Blk fall to Vst rise time
toVst
Blk pulse width
twBlk
BLK
50%
50%
Pcg
∗5
50%
twPcg
Vst
Blk 50%
∗5
50%
50%
twBlk
toVst
∗6 Input the pulse obtained by taking the OR of the above pulse (PCG) and BLK to the PCG input pin.
–9–
LCX021AM
Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V)
1. Horizontal drivers
Item
Input pin capacitance
Input pin current
Symbol
Min.
Typ.
Max.
Unit
Conditions
HCKn
CHckn
—
12
17
pF
HST
CHst
—
12
17
pF
HCK1
–500
–250
—
µA
HCK1 = GND
HCK2
–1000 –300
—
µA
HCK2 = GND
HST
–500
–150
—
µA
HST = GND
RGT
–150
–30
—
µA
RGT = GND
Video signal input pin capacitance
Csig
—
120
170
pF
Current consumption
IH
—
15.0
20.0
mA
HCKn: HCK1, HCK2 (4.0MHz)
Min.
Typ.
Max.
Unit
Conditions
2. Vertical drivers
Symbol
Item
Input pin capacitance
Input pin current
VCK
CVck
—
12
17
pF
VST
CVst
—
12
17
pF
–1000 –150
—
µA
VCK = GND
–150
–30
—
µA
PCG, VST, ENB, DWN,
BLK, MODE = GND
—
3.0
6.0
mA
VCK: (24.0kHz)
Symbol Min.
Typ.
Max.
Unit
PWR
—
250
400
mW
Symbol
Min.
Typ.
Max.
Unit
Rpin
0.4
1
—
MΩ
Symbol
Min.
Typ.
Max.
Unit
—
10
15
nF
VCK
PCG, VST, ENB, DWN, BLK, MODE
Current consumption
IV
3. Total power consumption of the panel
Item
Total power consumption of the
panel (SVGA)
4. Pin input resistance
Item
Pin – VSS input resistance
5. Uniformity improvement signal
Item
Input pin capacitance for uniformity
CPSIGo
improvement signal
– 10 –
LCX021AM
Electro-optical Characteristics
(SVGA mode)
Item
Symbol Measurement method Min.
Typ.
Max.
Unit
Contrast ratio
25°C
CR
1
100
150
—
—
Effective apeature ratio
25°C
Teff
2
—
70
—
%
RV90-25
1.3
1.6
2.0
GV90-25
1.4
1.8
2.2
BV90-25
1.5
1.9
2.3
RV90-60
1.3
1.6
1.9
GV90-60
1.3
1.7
2.0
BV90-60
1.4
1.8
2.2
RV50-25
1.7
2.0
2.3
GV50-25
1.8
2.1
2.4
1.9
2.2
2.5
RV50-60
1.7
1.9
2.2
GV50-60
1.7
2.0
2.3
BV50-60
1.8
2.1
2.4
RV10-25
2.3
2.6
2.9
GV10-25
2.4
2.7
3.0
BV10-25
2.5
2.8
3.1
RV10-60
2.3
2.5
2.8
GV10-60
2.3
2.6
2.9
BV10-60
2.3
2.7
3.0
0°C
ton0
—
30
80
25°C
ton25
—
12
40
0°C
toff0
—
100
200
25°C
toff25
—
30
70
Flicker
60°C
F
5
—
–65
–40
dB
Image retention time
25°C
YT60
6
—
—
—
s
Cross talk
25°C
CTK
7
—
—
5
%
25°C
V90
60°C
25°C
V-T
characteristics
BV50-25
V50
60°C
25°C
V10
60°C
ON time
Response time
OFF time
3
4
V
ms
Reflection Preventive Processing
When a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a
polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. This
prevents characteristic deterioration caused by luminous reflection.
– 11 –
LCX021AM
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(6) Optical measurement systems
(1) Driving voltage
HVDD = 15.5V, VVDD = 15.5V,
• Measurement system I
VVC = 7.0V, Vcom = 6.6V
(2) Measurement temperature
25°C unless otherwise specified.
G
B R
Relay lens system
(3) Measurement point
Dichroic mirrors
One point in the center of the screen
unless otherwise specified.
(4) Measurement systems
LCD panel
Two types of measurement systems
Fresnel lens
are used as shown below.
Elliptic mirror
(5) Video input signal voltage (Vsig)
Vsig = 7.0 ± VAC [V]
(VAC: signal amplitude)
Relative light intensity
100W lamp angle distribution
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.0
Projection lenses
Screen
1.0
2.0
3.0
3.5
4.0
Panel incident light dispersion angle [ ° ]
• Measurement system II
Optical fiber
Light receptor lens
Light Detector
Measurement
Equipment
LCD panel
Drive Circuit
Light
Source
1. Contrast ratio
Contrast Ratio (CR) is given by the following formula (1).
L (White)
CR = L (Black) ... (1)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V
L (Black): Surface luminance of the panel at VAC = 4.5V
Both luminosities are measured by System I.
– 12 –
LCX021AM
2. Effective aperture ratio
Measure the luminances below on the screen in System I, and calculate the effective aperture ratio using
the following formula (2).
Luminance for panel without microlens
× (TFT aperture ratio) × 100 [%] ... (2)
3. V-T characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
correspond to the voltages which define 90%, 50%,
and 10% of transmittance respectively.
The angles of incidence for R, G and B are as shown in
the diagram below.
Red: Center: Vertical
Green: Left:
6.0 ± 0.5°
Blue: Right: 6.0 ± 0.5°
Transmittance [%]
Luminance for panel with microlens
90
50
10
V90
V50 V10
VAC – Signal amplitude [V]
Left
Center
Right
Optimum angle of incidence
6.0 ± 0.5°
Optimum angle of incidence
6.0 ± 0.5°
Pad
4. Response time
Response time ton and toff are defined by
formulas (3) and (4) respectively.
ton = t1 – tON ...(3)
toff = t2 – tOFF ...(4)
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
Input signal voltage (Waveform applied to the measured pixels)
4.5V
0.5V
7.0V
0V
Optical transmittance output waveform
100%
90%
10%
0%
tON
t1
ton
– 13 –
tOFF
t2
toff
LCX021AM
5. Flicker
Flicker (F) is given by the formula (5). DC and AC (SVGA:30Hz, rms) components of the panel output signal
for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in system II.
F [dB] = 20log
∗ Each input signal voltage for gray raster mode
is given by Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives
50% of transmittance in V-T characteristics.
component
{ AC
} ...(5)
DC component
6. Image retention time
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 7.0 ± VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention,
measure the time till the residual image becomes indistinct.
∗ Monoscope signal conditions:
Vsig = 7.0 ± 4.5 or ± 2.0 [V]
(shown in the right figure)
Vcom = 6.6V
Black level
4.5V
White level
2.0V
7.0V
2.0V
4.5V
0V
Vsig waveform
7. Cross talk
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and
Wi (i = 1 to 4) around a black window (Vsig = 4.5V/1V).
W2
W2'
W1 W1'
Cross talk value CTK = Wi' – Wi × 100 [%]
Wi
W4
W4'
W3 W3'
– 14 –
LCX021AM
Viewing Angle Characteristics (Typical Value)
90
Phi
0
180
10
30
50
70
Theta
270
θ0°
Z
θ
φ90°
Marking
φ
φ180°
X
φ270°
– 15 –
Y
φ0°
Measurement method
G1
G1
G1
G1
G1
G1
G1
G1
G1
G1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
G2
G2
G2
G2
G2
G2
G2
G2
G2
G2
B4
B4
B4
G4
G4
G4
R2
R2
R2
R2
R2
B3
B3
B3
B3
B3
G3
G3
G3
G3
G3
B4
B4
B4
B4
B4
18 dots
R3
R3
R3
R3
R3
G4
G4
G4
G4
G4
G4
R3
R3
R3
R3
B2
R3 G3 R3 area
B4
Photo-shielding
G3
G3
G3
G3
G4
B3
B3
B3
B3
B4
R2
R2
R2
R2
Gate SW
R4
R4
R4
R4
R4
R4
R4
R4
R4
R4
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
G5
G5
G5
G5
G5
G5
G5
G5
G5
G5
R5
R5
R5
R5
R5
R5
R5
R5
R5
R5
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
G6
G6
G6
G6
G6
G6
G6
G6
G6
G6
R6
R6
R6
R6
R6
R6
R6
R6
R6
R6
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
G1
G1
G1
G1
G1
G1
G1
G1
G1
G1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
G2
G2
G2
G2
G2
G2
G2
G2
G2
G2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
G3
G3
G3
G3
G3
G3
G3
G3
G3
G3
R3
R3
R3
R3
R3
R3
R3
R3
R3
R3
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
G4
G4
G4
G4
G4
G4
G4
G4
G4
G4
R4
R4
R4
R4
R4
R4
R4
R4
R4
R4
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
R5
R5
R5
R5
2448 dots
B6
B6
B6
B6
G6
G6
G6
G6
G5
G5
G5
G5
G5
R5
R5
R5
R5
R5
B6
B6
B6
B6
B6
G6
G6
G6
G6
G6
G5 Active
B5 area
R6
G6
G5
G5
G5
G5
2412 dots (effective 32.56mm)
Gate SW
R6
R6
R6
R6
R6
R6
R6
R6
R6
R6
R4
R4
R4
R4
R4
R4
R4
R4
R4
R4
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
G5
G5
G5
G5
G5
G5
G5
G5
G5
G5
R5
R5
R5
R5
R5
R5
R5
R5
R5
R5
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
G6
G6
G6
G6
G6
G6
G6
G6
G6
G6
R6
R6
R6
R6
R6
R6
R6
R6
R6
R6
G1
G1
G1
G1
G1
B1
B1
B1
B1
G1
B1
B1
G1
B1
G1
G1
B1
B1
G1
B1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
G2
G2
G2
G2
G2
G2
G2
G2
G2
G2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
G3
G3
G3
G3
G3
G3
G3
G3
G3
G3
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
18 dots
R3
R3
R3
R3
R3
R3
R3
R3
R3
R3
Gate SW
G4
G4
G4
G4
G4
G4
G4
G4
G4
G4
R4
R4
R4
R4
R4
R4
R4
R4
R4
R4
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
G5
G5
G5
G5
G5
G5
G5
G5
G5
G5
R5
R5
R5
R5
R5
R5
R5
R5
R5
R5
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
G6
G6
G6
G6
G6
G6
G6
G6
G6
G6
R6
R6
R6
R6
R6
R6
R6
R6
R6
R6
1 dot
604 dots (effective 24.46mm)
606 dots
Note) This RGB pixel arrangement agree with the items mentioned in the Pin Description. This RGB arrangement can be changed according to input signals.
– 16 –
1 dot
1. Dot arrangement
The dots are arranged in a stripe. The shaded area is used for the dark border around the display.
LCX021AM
LCX021AM
2. LCD panel operations
[Description of basic operations]
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 604 gate lines sequentially in a single horizontal scanning period (in SVGA mode).
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 804 × 3 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• Vertical and horizontal shift registers address one pixel, and then turn on Thin Film Transistors (TFTs; two
TFTs) to apply a video signal to the dot. The same procedures lead to the entire 604 × 804 × 3 dots to
display a picture in a single vertical scanning period.
• The data and video signals shall be input with the 1H-inverted system.
[Description of operating mode]
This LCD panel can change the active area by displaying a black frame to support various computer or video
signals. The active area is switched by MODE. However, the center of the screen is not changed. The active
area setting modes are shown below.
MODE
Display mode
H
SVGA
804 × 3 × 604
L
PC98
804 × 3 × 500
This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are
shown below:
RGT
Mode
DWN
Mode
H
Right scan
H
Down scan
L
Left scan
L
Up scan
Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin
block upside.
To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for
both the H and V systems must be varied. The phase relationship between the start pulse and the clock for
each mode is shown on the following pages.
– 17 –
LCX021AM
(1) Vertical direction display cycle
(1.1) SVGA
VD
VST (DWN = H)
VST (DWN = L)
1
VCK
2
3
4
601 602 603 604
Vertical display cycle 604H
(1.2) PC98
VD
VST (DWN = H)
VST (DWN = L)
1
VCK
2
3
4
497 498 499 500
Vertical display cycle 500H
(2) Horizontal direction display cycle
(2.1) SVGA/PC98, RGT = H
HD
HST
HCK1
1
2
3
HCK2
4
130 131 132 133 134
Horizontal display cycle
(2.2) SVGA/PC98, RGT = L
HD
HST
HCK1
1
2
HCK2
3
4
130 131 132 133 134
Horizontal display cycle
– 18 –
LCX021AM
3. 18-dot simultaneous sampling
The horizontal shift register samples SIGB1 to SIGB6, SUGG1 to SIGG6 and SIGR1 to SIGR6 signals
simultaneously. This requires phase matching between signals SIGB1 to SIGB6, SIGG1 to SIGG6 and SIGR1
to SIGR6 to prevent the horizontal resolution from deteriorating. Thus phase matching between each signal is
required using an external signal delaying circuit before applying the video signal to the LCD panel.
SIGB1, SIGG1, SIGR1
SIGB2, SIGG2, SIGR2
S/H
CK1
S/H
S/H
SIGB1, SIGG1, SIGR1
S/H
SIGB2, SIGG2, SIGR2
S/H
SIGB3, SIGG3, SIGR3
S/H
SIGB4, SIGG4, SIGR4
S/H
SIGB5, SIGG5, SIGR5
S/H
SIGB6, SIGG6, SIGR6
CK2
SIGB3, SIGG3, SIGR3
SIGB4, SIGG4, SIGR4
S/H
CK3
S/H
CK4
SIGB5, SIGG5, SIGR5
SIGB6, SIGG6, SIGR6
S/H
CK5
CK6
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK1
CK2
CK3
CK4
CK5
CK6
– 19 –
LCX021AM
The block diagram of the delaying procedure using simple-and-hold method is as follows. The following phase
relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT = Low
level), the phase settings for signals SIGB1 to SIGB6, SIGG1 to SIGG6 and SIGR1 to SIGR6 are exactly
reversed.
LCX021AM
Display System Block Diagram
An example of display system is shown below.
R
CXA2112R
R
G
G
CXA2111R
CXA2112R
LCX021AM
B
B
CXA2112R
HSYNC
PLL
MCK
FRP
CXD2464R
TIMING PULSE
VSYNC
– 20 –
LCX021AM
Optical Characteristics
1. Microlens outline
The LCX021AM has a single built-in microlens on the substrate side facing the TFT for the three TFT panel
picture elements. This microlens serves the following purposes.
(1) The microlens converges the incident light striking the LCD panel to the dot aperture in order to improve
the effective aperture ratio and increase the display brightness.
(2) The microlens provides a color representation by distributing the light flux for each of the three primary
colors R, G and B which strike the panel at different angles to the dot apertures corresponding to each
color.
This allows the light utilization efficiency to be improved by eliminating the light absorption by the color filter,
which had been unavoidable with conventional single panel projectors.
2. Recommended lighting conditions
In order to bring out the full light converging effects of the microlens and provide a color representation with
high color purity, the following lighting is recommended.
(1) The incident light angle of the three primary colors should be as shown in the figure below. The center
light should strike the panel from the panel normal direction, and the left and right light from angles
inclined to the right and left of the panel normal direction. The design optimal angle of incidence is the
range of 6.0 ± 0.5°. However, the optimal angle of incidence may be altered slightly depending on the
panel. Be sure to allow adjustment of the mutual angles of the dichroic mirrors so that the angle of
incidence can be varied within the range of 6.0 ± 0.5°.
Left
Center
Right
Optimum angle of incidence
6.0 ± 0.5°
Optimum angle of incidence
6.0 ± 0.5°
Pad
(2)
Effective light: The normal direction (center light), left light and right light noted above should strike the
panel at an angle of ±3.5° or less. Light with a dispersion angle greater than this value will
strike adjoining dot apertures and cause the color purity to worsen. (See the incident angle
distribution for System Ι.)
3. Recommended projection optical system
The maximum egress light angle for light passing through the LCD is approximately ±17°. Therefore, setting
the F stop of the projection lens to about 1.7 is recommended in order to maximize the light converging effects
of the microlens and provide a representation with excellent color balance. If the projection lens F stop is larger
than this value, the right and left light are kicked accordingly by the projection lens, thereby reducing the
egress light flux to the screen and the same time shifting the white balance.
– 21 –
LCX021AM
Notes on Operation
(1) Lighting spectrum and intensity
Use only visible light with a wavelength λ = 415 to 780nm as a light source. Light with a wavelength λ >
780nm (infrared light) will produce unwanted temperature rises. Light with a wavelength λ < 415nm
(ultraviolet light) will produce irreversible changes in the display characteristics. To prevent this, be sure to
mount UV/IR cut filters between the LCX021AM and the light source as necessary depending on the light
source.
The lighting intensity should be 1 million lx or less, and the panel surface temperature should not exceed
55°C.
(2) Lighting optical system
Care should be taken for the following points concerning the optical system mounted on the LCX021AM.
1) Light reflected from the optical system to the panel should be 20,000 lx or less.
2) Particular care should be taken for the panel incident angle distribution when designing optical systems
for use with the LCX021AM.
3) The panel surface temperature distribution should not exceed 10°C.
4) Light should shine only on the effective display area within the LCD panel and not on other unnecessary
locations. Leakage light may produce unwanted temperature rises.
– 22 –
LCX021AM
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in a clean environment.
b) When delivered, a surface of a panel (glass panel) is covered by a protective sheet.
Peel off the protective sheet carefully not to damage the glass panel.
c) Do not touch the surface of the glass panel. The surface is easily scratched. When cleaning, use a
clean-room wiper with isopropyl alcohol. Be careful not to leave a stain on the surface.
d) Use ionized air to blow off dust at the glass panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel
damages.
g) Minimum radius of bending curvature for a flexible substrate must be 1mm.
h) Torque required to tighten screws on a panel must be 3kg · cm or less.
i) Use appropriate filter to protect a panel.
j) Do not pressure the portion other than mounting hole (cover).
– 23 –
LCX021AM
Package Outline
Unit: mm
(5.1)
Thickness of the connector 0.3 ± 0.05
3
50.9 ± 0.7
2
(32.56)
57.0 ± 0.2
62.0 ± 0.2
(24.46)
32.0 ± 0.2
46.5 ± 0.2
5
6
6
Incident
light
P 8.0 × 4 =
(28.5)
13.23 ± 0.25
Active Area
4
3
Polarizing
Axis
7
2.5H9 × 3.0
φ2.5H9
8-φ2.5 ± 0.1
51.0 ± 0.2
5.5 ± 0.2
12.22 ± 0.25
2.5 ± 0.2
3.0 ± 0.2
5.1 ± 0.2
9.2 ± 0.2
9.7 ± 0.4
(1.0)
4R
1.
0
1
0.5 ± 0.15
P 0.5 × 39 = 19.5 ± 0.1
0.5 ± 0.1
+ 0.04
0.35 – 0.03
PIN1
PIN40
4.0 ± 0.4
No
1
F P C
2
Reinforcing board
3
Molding material
4
Reinforcing material
5
Outside frame
6
electrode (enlarged)
Description
7
Glass
Polarizing film
The rotation angle of the active area relative to H and V is ± 1°.
weight 48g
– 24 –