LCX034ALT
1.8cm (0.7 Type) Black-and-White LCD Panel
Description
The LCX034ALT is a 1.8cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with a built-in peripheral
driving circuit. Use of three LCX034ALT panels
provides a full-color representation. The striped
arrangement suitable for data projectors is capable
of displaying fine text and vertical lines.
The adoption of DMS∗1 structure and high light
resistance structure realizes a high luminance
screen. And cross talk free circuit and ghost free
circuit contribute to high picture quality.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing and
control signals.
The panel contains an active area variable circuit
which supports SVGA/VGA/PC98∗2 data signals by
changing the active area according to the type of
input signal. In addition, double-speed processed
NTSC/PAL can also be supported.
∗1 Dual Metal Shield
∗2 “PC98” is a treadmark of NEC Corporation.
Features
• Number of active dots: 485,000 (0.7 Type, 1.8cm in diagonal)
• Accepts the computer requirements of SVGA (804 × 604), VGA (644 × 484) and PC98 (644 × 404) platforms
• Supports NTSC (644 × 484) and PAL (762 × 572) by processing the video signal at double speed
• High optical transmittance: 13% (typ.)
• Built-in cross talk free circuit and ghost free circuit
• High contrast ratio with normally white mode
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• Up/down and/or right/left inverse display function
• Dust-proof glass used
Element Structure
• Dots: 804 (H) × 604 (V) = 485,616
• Built-in peripheral driver using polycrystalline silicon super thin film transistors
Applications
• Liquid crystal data projectors
• Liquid crystal projectors, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99665A04
Precharge Control
Circuit
RGT
VST
VCK
PCG
DWN
ENB
MODE1
MODE2
MODE3
HVDD
VVDD
Vss
SIG1
20
19
21
22 18
12
11 10
8
23
16
7
–2–
5
3
2
4
6 24
COM
PAD
COM
SIG6
BLK
9
SIG5
HCK2
17
SIG4
HCK1
14 15
SIG2
HST
13
SIG3
PSIG
1
V Shift Register
(Bidirectional Scanning)
Input Signal
Level Shifter
Circuit
Black Frame Control Circuit
Black Frame Control Circuit
V Shift Register
(Bidirectional Scanning)
Up/Down and/or Right/Left
Inversion Control Circuit
LCX034ALT
Block Diagram
H Shift Register (Bidirectional Scanning)
Black Frame Control Circuit
LCX034ALT
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage
HVDD
• V driver supply voltage
VVDD
• Common pad voltage
COM
• H shift register input pin voltage HST, HCK1, HCK2,
RGT
• V shift register input pin voltage VST, VCK, PCG,
BLK, ENB, DWN
MODE1, MODE2, MODE3
• Video signal input pin voltage
SIG1, SIG2, SIG3, SIG4,
SIG5, SIG6, PSIG
• Operating temperature∗
Topr
• Storage temperature
Tstg
∗ Panel temperature inside the antidust glass
–1.0 to +20
–1.0 to +20
–1.0 to +17
–1.0 to +17
V
V
V
V
–1.0 to +17
V
–1.0 to +15
V
–10 to +70
–30 to +85
°C
°C
Operating Conditions (VSS = 0V)
• Supply voltage
HVDD
15.5 ± 0.5V
VVDD
15.5 ± 0.5V
• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)
Vin
5.0 ± 0.5V
Pin Description
Pin
No.
Symbol
Description
Pin
No.
Symbol
Description
1
PSIG
Uniformity improvement signal
13
HST
Start pulse for H shift register
drive
2
SIG4
Video signal 4 to panel
14
HCK1
Clock pulse for H shift register
drive
3
SIG3
Video signal 3 to panel
15
HCK2
Clock pulse for H shift register
drive
4
SIG5
Video signal 5 to panel
16
Vss
GND (H, V drivers)
5
SIG2
Video signal 2 to panel
17
BLK
Black Frame display pulse
6
SIG6
Video signal 6 to panel
18
ENB
Enable pulse for gate selection
7
SIG1
Video signal 1 to panel
19
VCK
Clock pulse for V shift register
drive
8
HVDD
Power supply for H driver
20
VST
Start pulse for V shift register
drive
9
RGT
Drive direction pulse for H shift
register (H: normal, L: reverse)
21
PCG
Improvement pulse for uniformity
10
MODE3
Display area switching 3
22
DWN
Drive direction pulse for V shift
register (H: normal, L: reverse)
11
MODE2
Display area switching 2
23
VVDD
Power supply for V driver
12
MODE1
Display area switching 1
24
COM
Common voltage of panel
–3–
LCX034ALT
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a
high resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.)
(1) SIG1, SIG2, SIG3, SIG4, SIG5, SIG6, PSIG
HVDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
Input
Level conversion circuit
(2-phase input)
250Ω
1MΩ
1MΩ
250Ω
(3) RGT, MODE1, MODE2, MODE3
HVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(4) HST
HVDD
250Ω
250Ω
Input
1MΩ
–4–
Level conversion circuit
(single-phase input)
LCX034ALT
(5) PCG, VCK
VVDD
250Ω
250Ω
Input
Level conversion circuit
(single-phase input)
1MΩ
(6) VST, BLK, ENB, DWN
VVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(7) COM
VVDD
Input
1MΩ
–5–
LC
LCX034ALT
Input Signals
1. Input signal voltage conditions (VSS = 0V)
Item
Symbol
Min.
Typ.
Max.
Unit
H shift register input voltage (Low)
HST, HCK1, HCK2, RGT
(High)
VHIL
–0.5
0.0
0.4
V
VHIH
4.5
5.0
5.5
V
V shift register input voltage (Low)
MODE1, MODE2, MODE3,
BLK, VST, VCK, PCG,
(High)
ENB, DWN
VVIL
–0.5
0.0
0.4
V
VVIH
4.5
5.0
5.5
V
Video signal center voltage
Video signal input range∗1
VVC
6.8
7.0
7.2
V
Vsig
VVC – 4.5
7.0
VVC + 4.5
V
Vcom
VVC – 0.6
VVC – 0.5
VVC – 0.4
V
VpsigB
VVC ± 4.4
VVC ± 4.5
VVC ± 4.6
VpsigG
VVC ± 1.8
VVC ± 1.9
VVC ± 2.0
Common voltage of panel∗2
Uniformity improvement signal
input voltage (PSIG)∗3
V
∗1 Input video signal shall be symmetrical to VVC.
∗2 The typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value.
When the typical value is lowered, the maximum and minimum values may lower.
∗3 Input a uniformity improvement signal PSIG in the same polarity with video signals VSIG1 to VSIG6 and
which is symmetrical to VVC. PSIG wave form is 2 steps like below, in the upper chart, lower shows signal
level of the 1st step, upper shows signal level of the 2nd step. Also, the rising and falling of PSIG are
synchronized with the rising of PRG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed
within 450ns (as shown in a diagram below).
The optimum input voltage of PSIG may be changed according as drive conditions of the drive side.
Input waveform of uniformity improvement signal PSIG
90%
PsigB
PsigG
VVC
PSIG
10%
trPSIG, tfPSIG
PCG
PRG∗4
∗4 PRG shows the time of the 1st step of PSIG signal, and it is not input to the panel.
Level Conversion Circuit
The LCX034ALT has a built-in level conversion circuit in the clock input unit on the panel. The input signal
level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
–6–
LCX034ALT
2. Clock timing conditions (Ta = 25°C)
(SVGA mode: fHCKn = 4.0MHz, fVCK = 24.0kHz)
Item
HST
HCK
VST
VCK
ENB
PCG
PRG
Symbol
Min.
Typ.
Max.
Hst rise time
trHst
—
—
30
Hst fall time
tfHst
—
—
30
Hst data set-up time
tdHst
50
60
70
Hst data hold time
Hckn rise time∗5
thHst
50
60
70
trHckn
—
—
30
Hckn fall time∗5
tfHckn
—
—
30
Hck1 fall to Hck2 rise time
to1Hck
–15
0
15
Hck1 rise to Hck2 fall time
to2Hck
–15
0
15
Vst rise time
trVst
—
—
100
Vst fall time
tfVst
—
—
100
Vst data set-up time
tdVst
5
10
15
Vst data hold time
thVst
5
10
15
Vck rise time
trVck
—
—
100
Vck fall time
tfVck
—
—
100
Enb rise time
trEnb
—
—
100
Enb fall time
tfEnb
—
—
100
Vck rise/fall to Enb rise time
toEnb
300
500
—
Horizontal video period completed to Enb fall time
tdEnb
900
1000
—
Enb fall to Pcg rise time
toPcg
630
700
—
Pcg rise time
trPcg
—
—
30
Pcg fall time
tfPcg
—
—
30
Pcg rise to Prg rise time
toPrgr
300
500
—
Pcg rise to Prg rise time
toPrgf
200
250
—
Prg rise to Pcg fall time
toPcg
1050
1100
—
Pcg fall to horizontal video period start time
toVideo
300
350
—
Pcg pulse width
twPcg
1350
1600
—
Prg rise to Vck rise/fall time
toVck
0
1000
—
trBlk
—
—
100
tfBlk
—
—
100
toVst
32
—
—
Blk rise time
∗
6
BLK
Blk fall time
Blk fall to Vst rise time
∗5 Hckn means Hck1 and Hck2.
∗6 Blk is set to positive polarity pulse for other than SVGA mode ; Low level for SVGA mode.
–7–
Unit
ns
µs
ns
µs
LCX034ALT
<Horizontal Shift Register Driving Waveform>
Item
Hst rise time
Symbol
Waveform
90%
trHst
Hst
HST
Hst fall time
tfHst
Hst data set-up time
tdHst
Conditions
90%
10%
10%
trHst
∗7
tfHst
50%
50%
Hst
Hck1
Hst data hold time
50%
50%
thHst
tdHst
Hckn rise time∗3
∗5
Hckn fall time∗3
tfHckn
Hck1 fall to Hck2 rise time
to1Hck
10%
trHckn
∗7
HCK
90%
10%
Hckn
50%
to2Hck
tfHckn
50%
Hck1
50%
Hck1 rise to Hck2 fall time
50%
Hck2
to2Hck
to1Hck
∗7 Definitions: The right-pointing arrow (
) means +.
The left-pointing arrow (
) means –.
The black dot at an arrow (
) indicates the start of measurement.
–8–
• Hckn∗5
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
thHst
90%
trHckn
• Hckn∗5
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
• Hckn∗5
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
LCX034ALT
<Vertical Shift Register Driving Waveform>
Item
Vst rise time
Symbol
Waveform
90%
trVst
Vst
Vst fall time
VST
Conditions
90%
10%
tfVst
10%
trVst
tfVst
∗7
Vst data set-up time
tdVst
50%
50%
Vst
50%
50%
Vck
Vst data hold time
Vck rise time
thVst
trVck
Vck fall time
tfVck
Enb rise time
trEnb
thVst
90%
90%
10%
Vck
VCK
tdVst
10%
trVckn
tfVckn
90%
90%
10%
10%
Enb
ENB
Enb fall time
tfEnb
Vck rise/fall to
Enb rise time
toEnb
Horizontal video period
completed to Enb fall time
tfEnb
trEnb
∗7
50%
Vck
H. video period
toEnb
H. blanking period
tdEnb
50%
Enb
50%
tdEnb
Pcg
Enb fall to Pcg rise time
50%
toPcg
toPcg
–9–
LCX034ALT
Item
Pcg rise time
Symbol
Waveform
trPcg
90%
Pcg
PCG∗8
Pcg fall time
tfPcg
Pcg rise to Prg rise time
toPrgr
90%
10%
10%
tfEnb
trEnb
∗7
H. blanking period
Pcg fall to Prg fall time
toPrgf
Prg rise to Pcg fall time
toPcg
Pcg fall to horizontal
video period start time
toVideo
Pcg pulse width
Conditions
H. video period start
toVideo
twPcg
Pcg
50%
50%
toPrgf
toPrgr
Prg
50%
twPcg
50%
toPcg
∗7
Prg
PRG
Prg rise to
Vck rise/fall time
50%
toVck
toVck
Vck
BLK
Blk rise time
trBlk
Blk fall to Vst rise time
tfBlk
50%
∗7
Vst
50%
Blk 50%
Blk fall time
toVst
50%
toVst
∗8 Input the pulse obtained by taking the OR of the above pulse (PCG) and BLK to the PCG input pin.
– 10 –
LCX034ALT
Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V)
1. Horizontal drivers
Item
Input pin capacitance
Input pin current
Symbol
Min.
Typ.
Max.
Unit
Condition
HCKn
CHckn
—
7
12
pF
HST
CHst
—
7
12
pF
HCK1
–500
–250
—
µA
HCK1 = GND
HCK2
–1000 –300
—
µA
HCK2 = GND
HST
–500
–150
—
µA
HST = GND
RGT
–150
–30
—
µA
RGT = GND
Video signal input pin capacitance
Csig
—
130
200
pF
Current consumption
IH
—
10.0
15.0
mA
HCKn: HCK1, HCK2 (4.0MHz)
Min.
Typ.
Max.
Unit
Condition
2. Vertical drivers
Item
Input pin capacitance
Input pin current
Symbol
VCK
CVck
—
7
12
pF
VST
CVst
—
7
12
pF
–1000 –150
—
µA
VCK = GND
–150
–30
—
µA
PCG, VST, ENB, DWN,
BLK, MODE1, MODE2,
MODE3 = GND
—
3.0
6.0
mA
VCK: (24.0kHz)
Symbol Min.
Typ.
Max.
Unit
PWR
—
200
300
mW
Symbol
Min.
Typ.
Max.
Unit
Rpin
0.4
1
—
MΩ
Symbol
Min.
Typ.
Max.
Unit
—
8
12
nF
VCK
PCG, VST, ENB, DWN, BLK, MODE1,
MODE2, MODE3
Current consumption
IV
3. Total power consumption of the panel
Item
Total power consumption of the
panel
4. Pin input resistance
Item
Pin – VSS input resistance
5. Uniformity improvement signal
Item
Input pin capacitance for uniformity
CPSIGo
improvement signal
– 11 –
LCX034ALT
Electro-optical Characteristics
(SVGA mode)
Item
Symbol Measurement method Min.
Typ.
Max.
Unit
Contrast ratio
25°C
CR
1
120
150
—
—
Optical transmittance
25°C
T
2
11
13
—
%
RV90-25
1.0
1.3
1.7
GV90-25
1.1
1.5
1.9
BV90-25
1.2
1.6
2.0
RV90-60
1.0
1.3
1.6
GV90-60
1.0
1.4
1.7
BV90-60
1.1
1.5
1.9
RV50-25
1.4
1.7
2.0
GV50-25
1.5
1.8
2.1
1.6
1.9
2.2
RV50-60
1.4
1.6
1.9
GV50-60
1.4
1.7
2.0
BV50-60
1.5
1.8
2.1
RV10-25
1.9
2.2
2.5
GV10-25
2.0
2.3
2.6
BV10-25
2.1
2.4
2.7
RV10-60
1.9
2.1
2.4
GV10-60
1.9
2.2
2.5
BV10-60
1.9
2.3
2.6
0°C
ton0
—
30
80
25°C
ton25
—
12
40
0°C
toff0
—
100
200
25°C
toff25
—
30
70
Flicker
60°C
F
5
—
–65
–40
dB
Image retention time
25°C
YT60
6
—
—
0
s
Cross talk
25°C
CTK
7
—
—
5
%
25°C
V90
60°C
25°C
V-T
characteristics
BV50-25
V50
60°C
25°C
V10
60°C
ON time
Response time
OFF time
3
4
V
ms
Reflection Preventive Processing
When a retardation film which rotates the polarization axis is used to adjust to the polarization direction of a
polarization screen or prism, use a retardation film with reflection preventive processing on the surface. This
prevents characteristic deterioration caused by luminous reflection.
– 12 –
LCX034ALT
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 15.5V, VVDD = 15.5V
VVC = 7.0V, Vcom = 6.5V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Two types of measurement systems are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.0 ± VAC [V]
(VAC = signal amplitude)
• Measurement system I
Approx. 2000mm
Screen
Luminance
Meter
Measurement
Equipment
LCD Projector
Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or equivalent
Projection lens: Focal distance 80mm, F1.9
Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500)
(× 24, Sensor area: 7mmφ)
Polarizer: Side of incidence – Nitto Denko’s EG-1224DU or Polatechno’s SKN-1824ZT or equivalent
Side of output light – Polatechno's SHC-128 or equivalent
• Measurement system II
Optical fiber
Light receptor lens
Drive Circuit
Light Detector
Measurement
Equipment
LCD panel
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
CR =
L (White)
L (Black)
... (1)
L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the center of the screen at VAC = 4.5V.
Both luminosities are measured by System I.
– 13 –
LCX034ALT
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
T=
White luminance
Luminance of light source
× 100 [%] ... (2)
3. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
correspond to the voltages which define 90%, 50%,
and 10% of transmittance respectively.
Transmittance [%]
"White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V
on Measurement System I.
90
50
10
V90
V50 V10
VAC – Signal amplitude [V]
4. Response Time
Response time ton and toff are defined by
formulas (5) and (6) respectively.
ton = t1 – tON ...(5)
toff = t2 – tOFF ...(6)
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
Input signal voltage (Waveform applied to the measured pixels)
4.5V
0.5V
7.0V
0V
Optical transmittance output waveform
100%
90%
10%
0%
tON
t1
ton
– 14 –
tOFF
t2
toff
LCX034ALT
5. Flicker
Flicker (F) is given by formula (7). DC and AC (SVGA/VGA/PC98/NTSC: 30Hz, rms, PAL: 25Hz, rms)
components of the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum
analyzer in System II.
F [dB] = 20log
∗ Each input signal voltage for gray raster mode
is given by Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives
50% of transmittance in V-T characteristics.
AC component
{ DC
} ...(7)
component
6. Image Retention Time
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 7.0 ± VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention,
measure the time till the residual image becomes indistinct.
∗ Monoscope signal conditions:
Vsig = 7.0 ± 4.5 or ± 2.0 [V]
(shown in the right figure)
Vcom = 6.6V
Black level
4.5V
White level
2.0V
7.0V
2.0V
4.5V
0V
Vsig waveform
7. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and
Wi (i = 1 to 4) around a black window (Vsig = 4.5 V/1V).
W2
W1 W1'
W2'
Cross talk value CTK = Wi' – Wi × 100 [%]
Wi
W4
W4'
W3 W3'
– 15 –
LCX034ALT
Viewing angle characteristics (Reference Value)
90
Phi
0
180
10
30
50
70
Theta
270
θ0°
Z
θ
φ
φ180°
X
φ270°
– 16 –
φ90°
Y
φ0°
Measurement method
LCX034ALT
Optical transmittance of LCD panel (Reference Value)
Trans. [%]
20
10
0
400
500
600
700
Wavelength [nm]
Measurement method: Measurement system ΙΙ
– 17 –
LCX034ALT
1. Dot Arrangement
The dots are arranged in a stripe. The shaded area is used for the dark border around the display.
Gate SW
Gate SW
6 dots
804 dots (Effective 14.47mm)
816 dots
– 18 –
6 dots
612 dots
Active area
4 dots
Photo-Shielding
604 dots (Effective 10.87mm)
4 dots
Gate SW
LCX034ALT
2. LCD Panel Operations
[Description of basic operations]
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 604 gate lines sequentially in a single horizontal scanning period. (in SVGA mode)
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 804 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn
on to apply a video signal to the dot. The same procedures lead to the entire 604 × 804 dots to display a
picture in a single vertical scanning period.
• The data and video signals shall be input with the 1H-inverted system.
[Description of operating mode]
This LCD panel can change the active area by displaying a black frame to support various computer or video
signals. The active area is switched by MODE1, 2 and 3. However, the center of the screen is not changed.
The active area setting modes are shown below.
MODE1
MODE2
MODE3
Display mode
L
L
H
SVGA
804 × 604
L
H
L
PAL
762 × 572
L
H
H
VGA/NTSC
644 × 484
H
L
L
PC98
644 × 404
This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are
shown below.
RGT
Mode
DWN
Mode
H
Right scan
H
Down scan
L
Left scan
L
Up scan
Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin
block upside.
To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for
both the H and V systems nust be varied. The phase relationship between the start pulse and the clock for
each mode is shown on the following pages.
– 19 –
LCX034ALT
(1) Vertical direction display cycle
(1.1) SVGA
VD
VST (DWN = H)
VST (DWN = L)
1
VCK
2
601 602 603 604
Vertical display cycle 604H
(1.2) PAL
VD
VST (DWN = H)
VST (DWN = L)
VCK
1
2
569 570 571 572
Vertical display cycle 572H
(1.3) VGA/NTSC
VD
VST (DWN = H)
VST (DWN = L)
1
VCK
2
481 482 483 484
Vertical display cycle 484H
(1.4) PC98
VD
VST (DWN = H)
VST (DWN = L)
VCK
1
2
401 402 403 404
Vertical display cycle 404H
– 20 –
LCX034ALT
(2) Horizontal direction display cycle
(2.1.1) SVGA, RGT = H
HD
HST
HCK1
1
2
3
4
131 132 133 134
Horizontal display cycle
HCK2
(2.1.2) SVGA, RGT = L
HD
HST
HCK1
1
2
3
4
131 132 133 134
Horizontal display cycle
HCK2
(2.2.1) PAL, RGT = H
HD
HST
HCK1
1
2
3
4
125 126 127 128
Horizontal display cycle
HCK2
(2.2.2) PAL, RGT = L
HD
HST
HCK1
HCK2
1
2
3
4
125 126 127 128
Horizontal display cycle
– 21 –
LCX034ALT
(2.3.1) VGA/NTSC/PC98, RGT = H
HD
HST
HCK1
1
2
3
HCK2
4
105 106 107 108
Horizontal display cycle
(2.3.2) VGA/NTSC/PC98, RGT = L
HD
HST
HCK1
1
2
3
HCK2
4
105 106 107 108
Horizontal display cycle
– 22 –
LCX034ALT
3. 6-dot Simultaneous Sampling
The horizontal shift register samples signals SIG1 to SIG6 simultaneously. This requires phase matching
between signals SIG1 to SIG6 to prevent the horizontal resolution from deteriorating. Thus, phase matching
between each signal is required using an external signal delaying circuit before applying the video signal to
the LCD panel.
SIG1
SIG2
S/H
CK1
S/H
S/H
7
SIG1
S/H
5
SIG2
S/H
3
SIG3
S/H
2
SIG4
S/H
4
SIG5
S/H
6
SIG6
CK2
SIG3
S/H
CK3
SIG4
S/H
CK4
S/H
SIG5
CK5
SIG6
CK6
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK1
CK2
CK3
CK4
CK5
CK6
– 23 –
LCX034ALT
The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following
phase relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT =
Low level), the phase settings for signals SIG1 to SIG6 are exactly reversed.
LCX034ALT
Display System Block Diagram
An example of display system is shown below.
S/H Driver
CXA2112R
R-IN
Pre Driver
CXA2111R
G-IN
6
LCX034
R
B-IN
CLP, PRG
Timing
Generator
CXD3500R
Vsync
Hsync
S/H Driver
CXA2112R
6
S/H Driver
CXA2112R
6
FRP, S/H Control
PLL
CXA3106Q
MCK1
HST, HCK, VST, VCK, PCG, ENB
– 24 –
LCX034
G
LCX034
B
LCX034ALT
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in a clean environment.
b) When delivered, the panel surface (glass panel) is covered by a protective sheet. Peel off the protective
sheet carefully so as not to damage the glass panel.
c) Do not touch the glass panel surface. The surface is easily scratched. When cleaning, use a cleanroom wiper with isopropyl alcohol. Be careful not to leave a stain on the surface.
d) Use ionized air to blow dust off the glass panel.
(3) Light resistance
Orientation film and organic matter such as liquid crystal used inside of the LCD panel deteriorate by the
light chemical reaction. As a result, its indication characteristic may irreversible change. The progress of its
chemical reaction is influenced by short wavelength side's light (characteristics of UV cut filter) and
temperature when quantitiy of light is constant. To control its progress, attach suitable UV cut filter between
light source and LCD panel. (Sharp characteristic's filter of λ > 425nm is recommended.) Also, use suitable
IR cut filter to lower the temperature of LCD panel and cool the panel carefully.
(4) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop the panel.
c) Do not twist or bend the panel or panel frame.
d) Keep the panel away from heat sources.
e) Do not dampen the panel with water or other solvents.
f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel
damages.
g) Minimum radius of bending curvature for a flexible substrate must be 1mm.
h) Torque required to tighten screws on a panel must be 0.098N · m (measurement screw : JCIS Type 1,
M1.7 flat head screw) or less.
i) Do not pressure the portion other than mounting hole (cover).
– 25 –
LCX034ALT
Package Outline
Unit: mm
4.9 ± 0.2
0.3 ± 0.05 Thickness of the connector
12.5 ± 0.05
2.2 ± 0.1
4
(75.5)
1
2
3
23.0 ± 0.1
26.0 ± 0.15
101.5 ± 1.4
0
1.
R
8-
5-φ1.8 ± 0.05
Incident light
Polarizing Axis
7
8
9
(14.47)
12.5 ± 0.15
2.0 ± 0.1
Output light
Polarizing Axis
No
1
0.5 ± 0.15
4.0 ± 0.4
21.0 ± 0.1
25.0 ± 0.15
Incident
light
12.0 ± 0.15
1.5 ± 0.1
(10.87)
Active Area
5
6
P 0.5 ± 0.02 × 23 = 11.5 ± 0.03
0.5 ± 0.1
0.35 ± 0.03
Description
F P C
2
Molding material
3
Outside frame
4
Reinforcing board
PIN24
PIN1
5 Reinforcing material
electrode (enlarged)
The rotation angle of the active area relative to H and V is ± 1°.
6
Glass 1
7
Glass 2
8
Cover 1
9
Cover 2
weight 5.6g
– 26 –
Sony Corporation