LCX033ANB 1.4cm (0.44 Type) NTSC/PAL Color LCD Panel Description The LCX033ANB is a 1.1cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. This panel provides full-color representation in NTSC/PAL mode. RGB dots are arranged in a delta pattern featuring high picture quality of no fixed color patterns, which is inherent in vertical stripes and mosaic pattern arrangements. Features • The number of active dots: 180,000 (0.44 Type; 1.1cm in diagonal) • Horizontal resolution: 400 TV lines • High optical transmittance: 4.0% (typ.) • High contrast ratio with normally white mode: 200 (typ.) • Built-in H and V drivers (built-in input level conversion circuit, TTL drive possible) • High quality picture representation with RGB delta arranged color filters • Full-color representation • NTSC/PAL compatible • Up/down and/or right/left inverse display function • 4:3 and 16:9 aspect switching function • Power save mode (Through current reduction by stop of level shifter and scanner during power supply cutoff) Element Structure • Dots Total dots : 827 (H) × 228 (V) = 188,556 Active dots: 800 (H) × 225 (V) = 180,000 • Built-in peripheral driver using polycrystalline silicon super thin film transistors. Applications • Viewfinders • Super compact liquid crystal monitors etc. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00776 LCX033ANB VDD VSS VST VCK STB EN DWN RGT HST HCK2 HCK1 BLK BLUE RED GREEN COM Block Diagram 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 H Level Conversion Circuit H Shift Register V Shift Register V Level Conversion Circuit CS LC COM Pad –2– LCX033ANB Absolute Maximum Ratings (VSS = 0V) • H and V driver supply voltages VDD • Common pad voltage COM • H driver input pin voltage HST, HCK1, HCK2 RGT • V driver input pin voltage VST, VCK EN, BLK, DWN • Power save mode input pin voltage STB • Video signal input pin voltage GREEN, RED, BLUE • Operating temperature Topr • Storage temperature Tstg –1.0 to +17 –1.0 to +17 –1.0 to +17 V V V –1.0 to +17 V –1.0 to +17 –1.0 to +15 –10 to +70 –30 to +85 V V °C °C Operating Conditions (VSS = 0V) Supply voltage VDD 11.4 to 14.0 V Input pulse voltage (Vp-p of all input pins except video signal input pins) Vin 2.6V (more than) Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 COM Common voltage of panel 9 RGT Drive direction pulse for H shift register (H: normal, L: reverse) 2 GREEN Video signal (G) to panel 10 DWN Drive direction pulse for V shift register (H: normal, L: reverse) 3 RED Video signal (R) to panel 11 EN Enable pulse for gate selection 4 BLUE Video signal (B) to panel 12 STB For power save mode control (L-power save mode) 5 BLK Top/bottom block display pulse 13 VCK Clock pulse for V shift register drive 6 HCK1 Clock pulse for H shift register drive 14 VST Start pulse for V shift register drive 7 HCK2 Clock pulse for H shift register drive 15 Vss GND (H, V drivers) 8 HST Start pulse for H shift register drive 16 VDD Power supply for H and V drivers –3– LCX033ANB Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supply. In addition, protective resistors are added to all pins except video signal input. All pins are connected to Vss with a high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.) (1) Video signal input From H driver VDD Input 1MΩ Signal line (2) HCK1, HCK2 VDD 250Ω 250Ω HCK1 250Ω 250Ω 1MΩ 1MΩ HCK2 Level conversion circuit (2-phase input) (3) HST VDD 250Ω 250Ω Input Level conversion circuit (singlephase input) 1MΩ (4) RGT, VST, EN, VCK, BLK, DWN, STB VDD 2.5kΩ 2.5kΩ Input Level conversion circuit (singlephase input) 1MΩ (5) COM VDD Input 1MΩ –4– LC LCX033ANB Level Conversion Circuit The LCX033ANB has a built-in level conversion circuit in the clock input unit located inside the panel. The circuit voltage is stepped up to VDD inside the panel. This level conversion circuit meets the specifications of a 3.0V power supply of the externally-driven IC. (For a single-phase input unit) An example of the I/O voltage characteristics of a level conversion circuit is shown in the figure to the right. The input voltage value that becomes half the output voltage (after voltage conversion) is defined as Vth. The Vth value varies depending on the VDD voltage. The Vth values under standard conditions are indicated in the table below. (HST, VST, EN, RGT, VCK, BLK, DWN and STB in the case of a singlephase input) Output voltage (inside panel) 1. I/O characteristics of level conversion circuit VDD Example of single-phase I/O characteristics VDD 2 Vth Input voltage [V] VDD = 12.0V Vth voltage of circuit Symbol Min. Typ. Max. Unit Vth 0.35 1.50 2.60 V (For a differential input unit) An example of I/O voltage characteristics of a level conversion circuit for a differential input is shown in the figure to the right. Although the characteristics, including those of the Vth voltage, are basically the same as those for a single-phased input, the twophased input phase is defined. (Refer to clock timing conditions.) Output voltage (inside panel) Item VDD Example of differential I/O characteristics VDD 2 Vth Input voltage [V] 2. Current characteristics at the input pin of level conversion circuit VDD A slight pull-in current is generated at the input pin of the level conversion circuit. (The equivalent circuit is shown to the right.) The current volume increases as the voltage at the input pin decreases, and is maximized when the pin is grounded. (Refer to electrical characteristics.) 0 Input pin voltage [V] 10 output Input pin current 0 HCK1 input HCK2 input Max. value Level conversion equivalent circuit Pull-in current characteristics at the input pin –5– LCX033ANB Input Signals 1. Input signal voltage conditions (VSS = 0V, VDD = 11.4 to 14.0V) Item Symbol Min. Typ. Max. Unit H driver input voltage (HST, HCK1, HCK2, RGT) (Low) VHIL –0.35 0.0 0.35 V (High) VHIH 2.6 3.0 3.5 V V driver input voltage (VST, VCK, EN, BLK, DWN) (Low) VVIL –0.35 0.0 0.35 V (High) VVIH 2.6 3.0 3.5 V Common voltage of panel VCOM Item Symbol VVC – 0.45 VVC – 0.3 VVC – 0.15 Min. Video signal input range Vsig VSS + 1.3 Video signal input white level VsigL 0.5 Typ. V Max. Unit VDD – 1.8 V V Note) Video signal shall be symmetrical to video signal center voltage VVC. Supplement1) Video signal input range is set within the range shown below for VDD and VSS. Also, video signal white level is defined for VVC as shown below. VDD VDD – 1.8 VsigL White level VVC VsigL VSS + 1.3 VSS AAAAA AAAAA AAAAA AAAAA AAAAA Video signal input range Max. VDD – 1.8 [V] Min. VSS + 1.3 [V] Supplement2) When power save mode is used, use video signal and COM pin within the condition ±0.15V to prevent DC applying to LCD. –6– LCX033ANB 2. Clock timing conditions (Ta = 25°C, Input voltage = 3.0V, VDD = 12.0V) Item HST HCK VST VCK EN BLK∗3 Symbol Min. Typ. Max. Hst rise time trHst 30 Hst fall time tfHst 30 Hst data set-up time tdHst –100 60 130 Hst data hold time Hckn∗2 rise time thHst –200 –120 –50 trHckn 30 Hckn∗2 fall time tfHckn 30 Hck1 fall to Hck2 rise time to1Hck –15 0 15 Hck1 rise to Hck2 fall time to2Hck –15 0 15 Vst rise time trVst 100 Vst fall time tfVst 100 Vst data set-up time tdVst –50 32 50 Vst data hold time thVst –50 –32 –20 Vck rise time trVck 100 Vck fall time tfVck 100 En rise time trEn 100 En fall time tfEn 100 En fall time to Vck rise/fall time toVck 100 3000 3500 Vck rise/fall to En rise time tdVck 100 500 1000 Blk rise time trBlk 100 Blk fall time tfBlk 100 Blk pulse width twBlk Blk fall to En rise time tdEnb 1.0 600 ∗2 Hckn means Hck1, Hck2. (fHckn = 2.75MHz, fVckn = 7.865kHz) ∗3 BLK pulse is used only for 16:9 mode. For 4:3 mode, connect to VSS. –7– 700 Unit ns µs ns ms 800 ns LCX033ANB <Horizontal Shift Register Driving Waveform> Item Hst rise time Symbol Waveform 90% trHst HST Hst fall time HST Conditions 90% 10% tfHst 10% trHst tfHst ∗4 Hst data set-up time tdHst HST 50% 50% HCK1 50% Hst data hold time 50% thHst tdHst Hckn∗2 rise time trHckn ∗2 Hckn∗2 fall time to1Hck 10% trHckn ∗4 Hck1 fall to Hck2 rise time 90% 10% tfHckn 50% tfHckn • Hckn∗2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tdHst = 135ns thHst = –135ns 50% HCK1 50% Hck1 rise to Hck2 fall time • Hckn∗2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns thHst 90% HCKn HCK • Hckn∗2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns 50% HCK2 to2Hck to2Hck –8– to1Hck • tdHst = 135ns thHst = –135ns LCX033ANB <Vertical Shift Register Driving Waveform> Item Symbol Vst rise time Waveform 90% trVst VST Vst fall time VST Conditions 90% 10% tfVst 10% trVst • VCK duty cycle 50% tfVst ∗4 Vst data set-up time 50% tdVst 50% VST 50% 50% • VCK duty cycle 50% Vst data hold time VCK thVst tdVst Vck rise time 10% VCK Vck fall time tfVck En rise time trEn 90% 90% trVck VCK thVst • VCK duty cycle 50% tdVst = 32µs thVst = –32µs 10% trVck 90% tfVck 10% 90% 10% • VCK duty cycle 50% EN En fall time tfEn tfEn trEn ∗4 EN En fall to Vck rise/fall time toVck VCK EN Vck rise/fall to En rise time Blk rise time 50% 50% 50% 50% 50% 50% • VCK duty cycle 50% tdVck toVck 90% trBlk toVck tdVck 90% 10% Blk fall time tfBlk Blk pulse width twBlk BLK tdVck 10% trBlk tfBlk ∗4 BLK 50% twBlk 50% 50% EN Blk fall to En rise time tdEnb tdEnb ∗4 Definitions: The right-pointing arrow ( The left-pointing arrow ( The black dot at an arrow ( ) means +. ) means –. ) indicates the start of measurement. –9– LCX033ANB Electrical Characteristics (Ta = 25°C, VDD = 12.0V, Input voltage = 3.0V) 1. Horizontal drivers Item Input pin capacitance Input pin current Symbol Min. Typ. Max. Unit Condition HCKn CHckn 5 10 pF HST CHst 5 10 pF HCK1 IHck1 –500 –130 µA HCK1 = GND HCK2 IHck2 –500 –150 µA HCK2 = GND HST IHst –300 –20 µA HST = GND RGT IRgt –100 –15 µA RGT = GND STB Istb –100 –15 µA STB = GND 50 pF Video signal input pin capacitance Csig 2. Vertical drivers Item Input pin capacitance Symbol Min. Typ. Max. Unit VCK CVck 5 10 pF VST CVst 5 10 pF VST EN DWN VCK BLK IVst IEn IDwn IVck IBlk –100 –15 µA 3. Total power consumption of the panel Item Total power consumption of the panel (NTSC) Symbol Min. PWR Power consumption during power save (NTSC) Typ. Max. Unit 30 50 mW 0.6 mW 4. VCOM input resistance, video signal input resistance Item Symbol Min. Typ. Max. Unit VCOM – Vss input resistance Rcom 0.5 1 1.2 MΩ 0.5 1 1.2 MΩ Video signal – Vss input resistance Rsig – 10 – Condition VST, EN, DWN, VCK, BLK = GND LCX033ANB Electro-optical Characteristics (Ta = 25°C, NTSC mode) Symbol Item Contrast ratio VDD = 12.0V Vsig = 6.0 ± 4.0V Optical transmittance R Chromaticity G B V90 V-T characteristics V50 V10 Half tone color reproduction range ON time Response time OFF time Flicker Image retention time 60°C CR4.060 25°C CR4.025 60°C T Measurement method 1 2 Min Typ. Max. 70 200 — 70 200 — 3.2 4.0 — X Rx 0.580 0.620 0.660 Y Ry 0.300 0.340 0.380 X Gx 0.250 0.290 0.330 Y Gy 0.550 0.590 0.630 X Bx 0.105 0.140 0.175 Y By 0.070 0.110 0.150 3 Unit — % CIE standards 25°C V90-25 1.1 1.6 2.2 60°C V90-60 1.0 1.5 2.1 25°C V50-25 1.5 2.0 2.5 60°C V50-60 1.4 1.9 2.4 25°C V10-25 2.2 2.6 3.2 60°C V10-60 2.1 2.5 3.1 R vs. G V50RG — –0.10 –0.25 B vs. G V50BG — 0.07 0.45 0°C ton0 — 30 100 25°C ton25 — 20 40 0°C toff0 — 65 150 25°C toff25 — 20 60 60°C F 7 — — –40 dB YT60 8 — — 20 s 60 min. 4 5 6 – 11 – V V ms LCX033ANB <Electro-optical Characteristics Measurement> Basic measurement conditions (1) Driving voltage VDD = 12.0V VVC = 6.0V, VCOM = 5.70V (2) Measurement temperature 25°C unless otherwise specified. (3) Measurement point One point in the center of screen unless otherwise specified. (4) Measurement systems Two types of measurement system are used as shown below. (5) RGB input signal voltage (Vsig) Vsig = 6.0 ± VAC [V] (VAC: signal amplitude) ∗ Measurement system I Back Light 3.5mm Measurement Equipment Luminance Meter Back light: color temperature 8500K, +0.004uV (25°C) ∗ Back light spectrum (reference) is listed on another page. LCD panel ∗ Measurement system II Optical fiber Light receptor lens Drive Circuit Light Detector Measurement Equipment LCD panel Light Source 1. Contrast Ratio Contrast Ratio (CR4.0) is given by the following formula (1). CR4.0 = L4.0 (White) ...(1) L4.0 (Black) L4.0 (White): Surface luminance of the TFT-LCD panel at VDD = 12.0V, VVC = 6.0V, VCOM = 5.70V and the RGB signal amplitude VAC = 0.5V. L4.0 (Black): Surface luminance of the panel at VAC = 4.0V. – 12 – LCX033ANB 2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). T= L (White) × 100 [%] ...(2) Luminance of Back Light L (White) is the same expression as defined in the "Contrast Ratio" section. 3. Chromaticity Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. System I uses Chromaticity of x and y on the CIE standards here. Raster Signal amplitudes (VAC) supplied to each input R input G input B input R 0.5 4.0 4.0 G 4.0 0.5 4.0 B 4.0 4.0 0.5 4. V-T Characteristics V-T characteristics, the relationship between signal amplitude and the transmittance of the panels, are measured by System II. V90, V50 and V10 correspond to the each voltage which defines 90%, 50% and 10% of transmittance respectively. (Transmittance at VAC = 0.5V is 100%.) Transmittance [%] (Unit: V) 90 50 10 V90 and V50B respectively. V50RG and V50BG, the voltage differences between V50R and V50G, V50B and V50G, are simply given by the following formulas (3) and (4) respectively. VAC – Signal amplitude [V] 100 Transmittance [%] 5. Half Tone Color Reproduction Range Half tone color reproduction range of the LCD panels is characterized by the differences between the V-T characteristics of R, G and B. The differences of these V-T characteristics are measured by System II. System II defines signal voltages of each R, G, B raster modes which correspond to 50% of transmittance, V50R, V50G V50 V10 V50RG V50BG 50 G raster R raster B raster 0 V50R V50B V50G V50RG = V50R – V50G ...(3) V50BG = V50B – V50G ...(4) VAC – Signal amplitude [V] – 13 – LCX033ANB 6. Response Time Response time ton and toff are defined by the formulas (5) and (6) respectively. Input signal voltage (waveform applied to the measured pixels) 4.0V ton = t1 – tON ...(5) toff = t2 – tOFF ...(6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. 0.5V 6.0V 0V Optical transmittance output waveform 100% 90% The relationships between t1, t2, tON and tOFF are shown in the right figure. 10% 0% tON t1 ton tOFF t2 toff 7. Flicker Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in System II. F (dB) = 20log AC component ...(7) { DC component } ∗ R, G, B input signal condition for gray raster mode is given by Vsig = 6.0 ± V50 (V) where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics. 8. Image Retention Time Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 6.0 ± VAC (VAC: 3 to 4V), judging by sight at VAC that hold the maximum image retention, measure the time till the residual image becomes indistinct. ∗ Monoscope signal conditions: Vsig = 6.0 ± 4.0 or 6 ± 2.0 (V) (shown in the right figure) VCOM = 5.70V Black level 4.0V White level 2.0V 6.0V 2.0V 4.0V 0V Vsig waveform – 14 – LCX033ANB 9. Method of Measuring the Optimum Vcom There are two methods of measuring the optimum Vcom using the photoelectric element. 9-1. Method of Measuring Flicker In the field invert drive mode, adjust the flicker level of the half tone (Vsig = 1.5 to 2.5V) using the photoelectric element and oscilloscope so that its 30Hz component becomes minimum. The Vcom value at this time is taken to be the optimum Vcom. 9-2. Method of Measuring Contrast In the normal 1H invert drive mode, adjust the optical output voltage of the half tone (Vsig = 1.5 to 2.5V) so that it becomes minimum. The Vcom value at this time is taken to be the optimum Vcom. Example of Back Light Spectrum (Reference) 0.6 0.4 0.2 0 380 480 580 Wave length 380 – 780 [nm] – 15 – 680 780 LCX033ANB Description of Operation 1. Color Coding Color filters are coded in a delta arrangement. The shaded area is used for the dark border around the display. Gate SW dummy1 to 4 R G B Gate SW R G B Gate SW R G B Gate SW dummy5 to 8 Gate SW R G B R G B R 2 B Gate SW G B R B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G R G B R G B R B R G R G B B R Photo-shielding B R G G B R G B R B G B R G R B R G B G R G B R B G B R G R G B R G B R G B R B G B R G R B R G B G R G B R B G B R G R B R G B G R G B R R G 1 R G 225 Active area R 827 14 800 – 16 – 13 228 R LCX033ANB 2. LCD Panel Operations • A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 225 gate lines sequentially in every horizontal scanning period. A vertical shift register scans the gate lines from the top to bottom of the panel at DWN = High level. • The selected pulse is delivered when the enable pin turns to High level. PAL mode images are displayed by controlling the enable and VCK pin. The enable pin should be High when not in use. • A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits applies selected pulses to every 800 signal electrodes sequentially in a single horizontal scanning period. • Through current of the level shifter during power supply cutoff can be reduced by STB pin. (power save mode) Power save mode is set at STB = Low level. • Vertical and horizontal drivers address one pixel and then turn on Thin Film Transistors (TFTs; two TFTs) to apply a video signal to the dot. The same procedures lead to the entire 225 × 800 dots to display a picture in a single vertical scanning period. • Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned with 1.5-dot shifted against adjacent horizontal line. 1.5-dot shift of a horizontal driver output pulse against horizontal synchronized signal is required to apply a video signal to each dot properly. 1H reversed displaying mode is required to apply video signal to the panel. • The video signal shall be input with polarity-inverted system in every horizontal cycle. • Timing diagrams of the vertical and the horizontal right-direction scanning (RGT = High level) display cycle are shown below: – 17 – LCX033ANB • This LCD panel provides the following functions. • Right/left inverse mode • Up/down inverse mode These modes are controlled by two signals, RGT and DWN. RGT Mode DWN Mode H Right scan H Down scan L Left scan L Up scan HCK1 and HCK2 should be inverted to display the left-direction horizontal scanning (RGT = Low level). This inversion enables the center of the image to be fixed by eliminating offsets. (When an example of system mentioned on this data sheet is used, TG performs this operation automatically.) (1) Vertical display cycle VD VST VCK 2 1 224 225 Vertical display cycle 225H (14.3ms) (2) Horizontal display cycle (right scan) BLK HST 270 HCK1 1 2 3 4 5 6 271 HCK2 Horizontal display cycle (48.4µs) The horizontal display cycle consists of 800/3 = 267 clock pulses because of RGB simultaneous sampling. ∗ Refer to Description of Operation "3. RGB Simultaneous Sampling." – 18 – LCX033ANB 3. RGB Simultaneous Sampling Horizontal driver samples R, G and B signal simultaneously, which requires the phase matching between R, G and B signals to prevent horizontal resolution from deteriorating. Thus phase matching between each signal is required using an external signal delaying circuit before applying video signal to the LCD panel. Two methods are applied for the delaying procedure: Sample and hold and Delay circuit. These two block diagrams are as follows. The LCX033ANB has the right/left inverse function. The following phase relationship diagram indicates the phase setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be inverted between B and G signals. B S/H S/H CKB CKG R G S/H S/H CKR CKG S/H AC Amp 4 BLUE AC Amp 3 RED AC Amp 2 GREEN LCX033ANB (1) Sample and hold (right scan) CKG <Phase relationship of delaying sample-and-hold pulses> (right scan) HCKn CKB CKR CKG B R Delay Delay AC Amp 4 BLUE Delay AC Amp 3 RED AC Amp 2 GREEN G – 19 – LCX033ANB (2) Delay circuit (right scan) LCX033ANB Example of Color Filter Spectrum (Reference) 100 Color Filter Spectrum R 80 G B Transmittance [%] 60 40 20 0 400 500 600 Wavelength [nm] – 20 – 700 LCX033ANB Color Display System Block Diagram An example of single-chip display system is shown below. +12V +3V +12V RED GREEN RGB BLUE Y/color difference VCOM BLK CXA3503R HST HCK1 HCK2 VST VCK EN STB DWN Serial control RGT Control circuit (microcomputer, etc.) – 21 – LCD panel NTSC/PAL LCX033ANB LCX033ANB Notes on Handling (1) Static charge prevention Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mat on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in clean environment. b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the protective sheet carefully not to damage the panel. c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stain on the surface. d) Use ionized air to blow off dust at a panel. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop a panel. c) Do not twist or bend a panel or a panel frame. d) Keep a panel away from heat source. e) Do not dampen a panel with water or other solvents. f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel damages. – 22 – LCX033ANB Package Outline Unit: mm 12.5 ± 0.3 Thickness of the connector 0.3 ± 0.05 8.5 ± 0.05 1.2 ± 0.3 1 R 4- 56.1 ± 0.9 (40.7) 4 5 2 0 1. 3 15.4 ± 0.15 6 Active Area Incident light (0.4) 6.1 ± 0.25 (6.66) 6 (1.9) 2.7 ± 0.15 (8.96) 8.0 ± 0.25 16.0 ± 0.15 No PIN 16 4.0 ± 0.5 0.5 ± 0.1 3.0 ± 0.3 0.35 +0.04 -0.03 PIN 1 1 × 15 = 7.5 ± 0.03 0.5 ± 0.15 P 0.5 ± 0.02 Description F P C 2 Molding material 3 Outside frame 4 Reinforcing board 5 Reinforcing material 6 Polarizing film Mass 0.9g Electrode(enlarged) – 23 – Sony Corporation