LCX012BL
3.3cm (1.3-inch) Black-and-White LCD Panel
Description
The LCX012BL is a 3.3cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral
driving circuit. Use of three panels in combination
with the LCX012BL provides a full-color representation. The striped arrangement suitable for data
projectors is capable of displaying fine text and
vertical lines.
The adoption of advanced on-chip black matrix
realizes high picture quality without cross talk by
incorporating high luminance screen and cross talk
free circuit.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing and
control signals.
Using Sony’s timing generator “CXD2442Q” sends
timing signal necessary for LCD panel drive by
identificating computer supporting VGA automatically, and supports double-speed processed
NTSC/PAL.
Features
• The number of active dots: 312,000 (1.3-inch; 3.3cm in diagonal)
• Accepts the computer requirements of VGA platform (640 x 480)
• High optical transmittance: 25% (typ.)
• Supports NTSC/PAL by processing the video signal at double speed
• Built-in cross talk free circuit
• High contrast ratio with normally white mode: 250 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• Up/down and/or right/left inverse display function
Element Structure
• Dots: 644 (H) × 484 (V) = 311,696
• Built-in peripheral driver using polycrystalline silicon super thin film transistors.
Applications
• Liquid crystal data projectors
• Liquid crystal projectors, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96512-ST
Uniformity Improvement
Signal Control Circuit
V Shift Register
(Bidrectional Scanning)
V Shift Register
(Bidrectional Scanning)
Up/Down or Right/Left
Inversion
HCK2
NC
RGT
VST
VCK
PCG
DWN
ENB
CLR
12
13
17
10
19
18
21
20
16
15
Input Signal
Level
Shifter
–2–
22
14
8
COM
PAD
5
4
3 23
H Shift Register (Bidrectional Scanning)
COM
SIG6
6
SIG4
7
SIG5
SIG2
9
SIG3
SIG1
HCK1
11
Vss
HST
2
VVDD
PSIG
1
HVDD
NC
LCX012BL
Block Diagram
LCX012BL
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage
HVDD
• V driver supply voltage
VVDD
• Common pad voltage
COM
• H shift register input pin voltage
HST, HCK1, HCK2,
RGT
• V shift register input pin voltage
VST, VCK, PCG,
CLR, ENB, DWN
• Video signal input pin voltage
SIG1, SIG2, SIG3, SIG4,
SIG5, SIG6, PSIG
• Operating temperature
Topr
• Storage temperature
Tstg
–1.0 to +20
–1.0 to +20
–1.0 to +17
–1.0 to +17
V
V
V
V
–1.0 to +17
V
–1.0 to +15
V
–10 to +70
–30 to +85
°C
°C
Operating Conditions (VSS = 0V)
Supply voltage
HVDD
15.5 ±0.5 V
VVDD
15.5 ±0.5 V
Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)
Vin
5.0 ±0.5 V
Pin Description
Pin
No.
Symbol
Description
Pin
No.
Symbol
Description
1
NC
NC; Open
13
HCK2
Clock pulse for H shift register
drive
2
PSIG
Uniformity improvement signal
14
VSS
GND (H, V drivers)
3
SIG6
Video signal 6 to panel
15
CLR
Improvement pulse (1) for
uniformity
4
SIG5
Video signal 5 to panel
16
ENB
Enable pulse for gate selection
5
SIG4
Video signal 4 to panel
17
NC
NC; Open
6
SIG3
Video signal 3 to panel
18
VCK
Clock pulse for V shift register
drive
7
SIG2
Video signal 2 to panel
19
VST
Start pulse for V shift register
drive
8
SIG1
Video signal 1 to panel
20
DWN
Drive direction pulse for V shift
register (H: normal, L: reverse)
9
HVDD
Power supply for H driver
21
PCG
Improvement pulse (2) for
uniformity
10
RGT
Driver direction pulse for H shift
register (H: normal, L: reverse)
22
VVDD
Power supply for V driver
11
HST
Start pulse for H shift register
drive
23
COM
Common voltage of panel
12
HCK1
Clock pulse for H shift register
drive
24
TEST
Test; Open
–3–
LCX012BL
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. All pins are connected to VSS with a high
resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.)
(1) SIG1, SIG2, SIG3, SIG4, SIG5, SIG6, PSIG
HVDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
Input
Level conversion circuit
(2-phase input)
1MΩ
250Ω
(3) RGT
250Ω
1MΩ
HVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(4) HST
HVDD
250Ω
250Ω
Input
Level conversion circuit
(single-phase input)
1MΩ
(5) PCG, VCK
VVDD
250Ω
250Ω
Input
Level conversion circuit
(single-phase input)
1MΩ
(6) VST, CLR, ENB, DWN
VVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(7) COM
VVDD
Input
1MΩ
–4–
LC
LCX012BL
Input Signals
1. Input signal voltage conditions
(VSS = 0V)
Item
Symbol
Min.
Typ.
Max.
Unit
(Low)
VHIL
–0.5
0.0
0.4
V
(High)
VHIH
4.5
5.0
5.5
V
(Low)
VVIL
–0.5
0.0
0.4
V
(High)
VVIH
4.5
5.0
5.5
V
VVC
Video signal center voltage
Video signal input range∗1 (SIG1 to 6) Vsig
6.8
7.0
7.2
V
VVC – 4.5
7.0
VVC + 4.5
V
Common voltage of panel∗2
Vcom
VVC – 0.5
VVC – 0.4
VVC – 0.3
V
Uniformity improvement signal
input voltage (PSIG)∗3
Vpsig
VVC ± 3.3
VVC ± 3.5
VVC ± 3.7
V
H driver input voltage
V driver input voltage
∗1 input signal shall be symmetrical to VVC.
∗2 The typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the
typical value is lowered, the maximum and minimum values may lower.
∗3 Input a uniformity improvement signal PSIG in the same polarity with video signals SIG1 to 6 and which is
symmetrical to VVC. Also, the rising and falling of PSIG are synchronized with the rising of PCG pulse, and
the rise time trPSIG and fall time tfPSIG are suppressed within 800ns (as shown in a diagram below).
Input waveform of uniformity improvement signal PSIG
90%
VVC
PSIG
10%
trPSIG
tfPSIG
PCG
Level Conversion Circuit
The LCX012BL has a built-in level conversion circuit in the clock input unit on the panel. The input signal level
increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
–5–
LCX012BL
2. Clock timing conditions
(Ta = 25°C) (VGA mode: fHCKn = 2.5MHz, fVCK = 15.7kHz)
Item
HST
HCK
CLR
VST
VCK
ENB
PCG
Symbol
Min.
Typ.
Max.
Hst rise time
trHst
—
—
30
Hst fall time
tfHst
—
—
30
Hst data set-up time
tdHst
30
100
170
Hst data hold time
Hckn rise time∗4
thHst
30
100
170
trHckn
—
—
30
Hckn fall time∗4
tfHckn
—
—
30
Hck1 fall to Hck2 rise time
to1Hck
–15
0
15
Hck1 rise to Hck2 fall time
to2Hck
–15
0
15
Clr rise time
trClr
—
—
100
Clr fall time
tfClr
—
—
100
Vck rise/fall → Clr fall time
Tdclr
–100
0
100
Clr pulse width
twClr
2400
2500
2600
Vst rise time
trVst
—
—
100
Vst fall time
tfVst
—
—
100
Vst data set-up time
tdVst
5
15
25
Vst data hold time
thVst
5
15
25
Vck rise time
trVck
—
—
100
Vck fall time
tfVck
—
—
100
Enb rise time
trEnb
—
—
100
Enb fall time
tfEnb
—
—
100
Vck rise/fall to Enb rise time
toEnb
400
500
600
Enb pulse width
twEnb
2400
2500
2600
Pcg rise time
trPcg
—
—
30
Pcg fall time
tfPcg
—
—
30
Pcg rise to Vck rise/fall time
toVck
500
800
1000
Pcg pulse width
twPcg
900
1000
1100
∗4 Hckn means Hck1 and Hck2.
–6–
Unit
ns
µs
ns
LCX012BL
<Horizontal Shift Register Driving Waveform>
Item
Hst rise time
Symbol
Waveform
90%
trHst
Hst
Hst fall time
HST
Conditions
90%
10%
tfHst
10%
trHst
tfHst
O Hckn∗4
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
∗5
Hst data set-up time
tdHst
50%
50%
Hst
Hck1
Hst data hold time
50%
50%
thHst
tdHst
Hckn rise time∗4
Hckn fall time∗4
trHckn
thHst
90%
90%
∗4
Hckn
10%
trHckn
∗5
Hck1 fall to Hck2 rise time
O Hckn∗4
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
10%
tfHckn
HCK
to1Hck
O Hckn∗4
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
tfHckn
50%
50%
Hck1
50%
50%
Hck2
Hck1 rise to Hck2 fall time
to2Hck
to2Hck
Clr rise time
trClr
to1Hck
90%
90%
Clr
10%
10%
Clr fall time
tfClr
Clr pulse width
twClr
trClr
tfClr
CLR
Vck
50%
50%
Clr 50%
Vck rise/fall → Clr fall time tdClr
∗5
twClr
tdClr
∗5 Definitions: The right-pointing arrow (
) means +.
The left-pointing arrow (
) means –.
The black dot at an arrow (
) indicates the start of measurement.
–7–
O Hckn∗4
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
LCX012BL
<Vertical Shift Register Driving Waveform>
Item
Vst rise time
Symbol
Waveform
90%
trVst
Vst
Vst fall time
Conditions
90%
10%
tfVst
10%
trVst
tfVst
∗5
VST
Vst data set-up time
tdVst
50%
50%
Vst
50%
50%
Vck
Vst data hold time
Vck rise time
thVst
trVck
Vck fall time
tfVck
Enb rise time
trEnb
thVst
90%
90%
10%
Vck
VCK
tdVst
10%
trVckn
90%
tfVckn
10%
10%
90%
Enb
ENB
Enb fall time
tfEnb
Vck rise/fall to
Enb rise time
tdEnb
Enb pulse width
tfEn
trEn
Vck
twEnb
50%
Enb
50%
∗5
twEnb
50%
tdEnb
to3Vck
Pcg rise time
90%
trPcg
10%
Pcg
Pcg fall time
10%
tfPcg
trPcg
PCG
Pcg rise to Vck rise/fall
time
toVck
Vck
50%
toVck
50%
Pcg pulse width
90%
twPcg
Pcg
∗5
–8–
50%
twPcg
tfPcg
LCX012BL
Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V)
1. Horizontal drivers
Item
Input pin capacitance
Input pin current
Symbol
Min.
Typ.
Max. Unit
Condition
HCKn
CHckn
—
10
15
pF
HST
CHst
—
10
15
pF
HCK1
–500
–250
—
µA
HCK1 = GND
HCK2
–1000 –300
—
µA
HCK2 = GND
HST
–500
–150
—
µA
HST = GND
RGT
–150
–25
—
µA
RGT = GND
Video signal input pin capacitance
Csig
—
100
150
pF
Current consumption
IH
—
4.0
6.0
mA
Min.
Typ.
HCKn: HCK1, HCK2 (2.5MHz)
2. Vertical drivers
Item
Input pin capacitance
Input pin current
Symbol
Max. Unit
Condition
VCK
CVck
—
10
15
pF
VST
CVst
—
10
15
pF
–1000 –150
—
µA
VCK = GND
–150
–25
—
µA
PCG, VST, ENB, CLR,
DWN = GND
—
2.0
3.0
mA VCK: (15.7kHz)
Min.
Typ.
Max. Unit
—
100
150
mW
Min.
Typ.
Max.
Unit
0.4
1
—
MΩ
Symbol
Min.
Typ.
CPSIGon
—
6.5
VCK
PCG, VST, ENB, CLR, DWN
Current consumption
IV
3. Total power consumption of the panel
Item
Total power consumption of the
panel (VGA)
Symbol
PWR
4. Pin input resistance
Item
Pin – VSS input resistance
Symbol
Rpin
5. Uniformity improvement signal
Item
Input pin capacitance for
uniformity improvement signal
–9–
Max. Unit
7.0
nF
LCX012BL
Electro-optical Characteristics
(Ta = 25°C, VGA mode)
Item
Symbol
Measurement method
Min.
Typ.
Max.
Unit
Contrast ratio
25°C
CR
1
150
250
—
—
Optical transmittance
25°C
T
2
22
25
—
%
RV90-25
1.1
1.5
1.8
GV90-25
1.2
1.7
2.0
BV90-25
1.3
1.8
2.1
RV90-60
1.0
1.4
1.7
GV90-60
1.1
1.5
1.8
BV90-60
1.1
1.6
1.9
RV50-25
1.5
1.9
2.2
GV50-25
1.6
2.0
2.3
1.7
2.1
2.4
RV50-60
1.5
1.8
2.1
GV50-60
1.5
1.9
2.2
BV50-60
1.6
2.0
2.3
RV10-25
2.0
2.4
2.7
GV10-25
2.1
2.5
2.8
BV10-25
2.1
2.5
2.8
RV10-60
2.1
2.3
2.6
GV10-60
2.1
2.4
2.7
BV10-60
2.2
2.5
2.8
0°C
ton0
—
36
80
25°C
ton25
—
14
40
0°C
toff0
—
106
200
25°C
toff25
—
30
70
Flicker
60°C
F
5
—
–74
–40
dB
Image retention time
25°C
YT60
6
—
0
0
s
Cross talk
25°C
CTK
7
—
—
5
%
25°C
V90
60°C
25°C
V-T
characteristics
BV50-25
V50
60°C
25°C
V10
60°C
ON time
Response time
OFF time
3
4
V
ms
Reflection Preventive Processing
When a phase substrate which rotates polarization axis is used to adjust to the polarization direction of
polarization screen or prism, use the phase substrate with reflection preventive processed on the surface.
This prevents characteristic deterioration caused by luminous reflection.
– 10 –
LCX012BL
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HV DD = 15.5V, VVDD = 15.5V
VVC = 7.0V, Vcom = 6.6V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of screen unless otherwise specified.
(4) Measurement systems
Two typed of measurement system are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.0 ±V AC [V] (VAC: signal amplitude)
• Measurement system I
approx. 2000mm
Screen
Luminance
Meter
Measurement
Equipment
LCD Projector
Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or an equivalent
Projection lens: The focal distance 80mm, F1.9
Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500)
(× 24, Sensor area: 7mmφ)
Polarizer: Nitto Denko’s EG-1224DU or Polatechno’s SKN-18242T or equivalent
• Measurement system II
Optical fiber
Light receptor lens
Light Detector
Measurement
Equipment
LCD panel
Drive Circuit
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
CR =
L (White) ...
(1)
L (Black)
L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the center of the screen at VAC = 4.5V.
Both luminosities are measured by System Ι.
– 11 –
LCX012BL
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
T=
White luminance
x 100 [%] ... (2)
Luminance of light source
3. V-T Characteristics
V-T characteristics, the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II. V90, V50, and V10 correspond
to the each voltage which defines 90%, 50%, and 10%
of transmittance respectively.
Transmittance [%]
"White luminance" means the maximum luminance at the input signal amplitude VAC = 0.5V on Mesurement
System II.
90
50
10
V90
V50 V10
VAC – Signal amplitude [V]
4. Respons Time
Response time ton and toff are defined by
the formula (5) and (6) respectively.
Input signal voltage (Waveform applied to the measured pixels)
4.5V
ton = t1 – tON ... (5)
toff = t2 – tOFF ... (6)
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
0.5V
7.0V
0V
Optical transmittance output waveform
100%
90%
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
10%
0%
tON
t1
ton
– 12 –
tOFF
t2
toff
LCX012BL
5. Flicker
Flicker (F) is given by the formula (7). DC and AC (NTSC VGA: 30Hz, rms, PAL: 25Hz, rms) components of
the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analizer in
System II.
F [dB] = 20log { AC component } ... (7)
DC component
∗ Each input signal condition for gray raster mode is given by
Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives 50% of
transmittance in V-T characteristics.
6 Image Retention Time
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 7.0 ± VAC (VAC: 3 to 4V), judging by sight at VAC that hold the maximum image retention, measure
the time till the residual image becomes indistinct.
∗ Monoscope signal conditions:
Black level
Vsig = 7.0 ± 4.5 or ± 2.0 [V]
(shown in the right figure)
Vcom = 6.6V
4.5V
White level
2.0V
7.0V
2.0V
4.5V
0V
Vsig waveform
7. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented Wi' and Wi (i =
1 to 4) around black window (Vsig = 4.5V/1V)
W1
W1’
W2
W4
W2’
W4’
W3
Cross talk value CTK =
W3’
– 13 –
Wi' – Wi
× 100 [%]
Wi
LCX012BL
Viewing angle characteristics (Typical Value)
90
Phi
0
180
10
30
50
70
Theta
270
θ0°
Z
θ
φ90°
Marking
φ
φ180°
X
φ270°
– 14 –
Y
φ0°
Measurement method
LCX012BL
Optical transmittance of LCD panel (Typical Value)
30
Trans. [%]
20
10
0
400
500
600
700
Wavelength [nm]
Measurement method: Measurement system II
– 15 –
LCX012BL
1. Dot Arrangement
The dots are arranged in a stripe. The shaded area is used for the dark border around the display.
Gate SW
Gate SW
1 dot
Gate SW
1 dot
5 dots
644 dots
654 dots
– 16 –
5 dots
486 dots
Active area
484 dots
Photo-shielding
LCX012BL
2. LCD Panel Operations
[Description of basic operations]
The basic operations of the LCD panel are shown below based on the VGA mode.
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 484 gate lines sequentially in every horizontal scanning period. Two lines of horizontal electrodes
are sequentially selected in NTSC/PAL mode.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 644 signal electrodes sequentially in a single horizontal scanning period.
• Vertical and horizontal shift registers address one pixel, and then Thin film Transistors (TFTs; two TFTs) turn
on to apply a video signal to the dot. The same procedures lead to the entire 484 × 644 dots to display a
picture in a single vertical scanning period.
• To change the combination of the horizontal electrode in NTSC/PAL mode, the phase of VCK need to be
inverted. Normally, switching every field maximizes vertical resolution.
• The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While
maintaining the CLR at High level, the VVDD potential drops to approximately 9.5V. This pin shall be
grounded when not in use.
• The video signal shall be input with 1H-inverted system.
• Timing diagrams of the vertical for VGA mode and NTSC/PAL mode and the horizontal display cycle are
shown below:
(1) Vertical display cycle (VGA)
VD
VST
(DWN = High level)
VST
(DWN = Low level)
VCK
1
2
Vertical display cycle 480H
(2) Horizontal display cycle
HD
HST
108
HCK1
1
2
3
4
5
6
109
HCK2
Horizontal display cycle
– 17 –
480
LCX012BL
[Description of operating mode]
The LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
These modes are controlled by two signals (RGT and DWN). The setting mode is shown below.
RGT
Mode
DWN
Mode
H
Right scan
H
Down scan
L
Left scan
L
Up scan
The direction of the right/left and/or up/down mean when Pin 1 marking is located at right side with the pin
block upside.
• To improve uniformity, the analog signals PSIG shall be input by synchronizing with SIG1 to SIG6.
• When the up-scan mode (DWN = Low level) is set, the phase of VST shall be inverted
3. 6-dot Simultaneous Sampling and Dot-inverted Drive
SIG1
SIG2
S/H
CK1
S/H
S/H
AC Amp
8
SIG1
S/H
AC Amp
7
SIG2
S/H
AC Amp
6
SIG3
S/H
AC Amp
5
SIG4
S/H
AC Amp
4
SIG5
S/H
AC Amp
3
SIG6
CK2
SIG3
S/H
CK3
SIG4
S/H
CK4
SIG5
S/H
SIG6
CK5
CK6
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK1
CK2
CK3
CK4
CK5
CK6
– 18 –
LCX012BL
Horizontal driver samples SIG1 to SIG6 signal simultaneously. Which requires the phase matching between
SIG1 to SIG6 signals to prevent horizontal resolution from deteriorating. Thus phase matching between each
signal is required using an external signal delaying circuit before applying video signal to the LCD panel.
The block diagram of the delaying procedure using sample-and-hold method is as follows.
The following phase relationship diagram indicates the phase setting for the right scan (RGT = High level). For
the left scan (RGT = Low level), the phase setting shall be inverted between SIG1 to SIG6 signals.
LCX012BL
Display System Block Diagram
An example of display system is shown below.
Discrete Buff.
R
G
RGB Driver
CXA1853Q
S/H
CXA2504N
LCX012BL
R
S/H
CXA2504N
LCX012BL
S/H
CXA2504N
LCX012BL
B
FRP
HD
VD
TG
CXD2442Q
SH
C.SYNC
HCK, VCK
– 19 –
G
B
LCX012BL
Notes on Handling
(1) Static charge prevention
Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mat on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionozed air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in clean environment.
b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet.
Peel off the protective sheet carefully not to damage the panel.
c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stain on the surface.
d) Use ionized air to blow off dust at a panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or a panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel
damages.
g) Minimum bent radius rating for flexible substrates is 1mm.
h) Panel screw torque should not exceed 3kg · cm.
– 20 –
LCX012BL
Package Outline
Unit: mm
3.7 ± 0.1
Thickness of the connector 0.3 ± 0.05
25.0 ± 0.15
1.8 ± 0.1
4
2.
R
4-
(62.0)
1
37.0 ± 0.1
42.0 ± 0.15
104.0 ± 1.4
5
3-φ2.3 ± 0.05
C0.8
Active Area
3
2
5
6
Incident
light
Polarizing
Axis
(26.65)
30.0 ± 0.1
38.0 ± 0.15
(20.03)
21.0 ± 0.25
2.5 ± 0.1
2.1 ± 0.05
7
φ2.1 ± 0.05
19.0 ± 0.25
4.0 ± 0.1
No
0.5 ± 0.15
4.0 ± 0.4
P 1.0 × 23 = 23.0 ± 0.1
1.0 ± 0.15
0.6 ± 0.05
PIN1
PIN24
1
Description
F P C
2
Molding material
3
Outside frame
4
Reinforcing board
5 Reinforcing material
electrode (enlarged)
6
Polarizing film
7
Cover
weight 7.5g
The rotation angle of the active area relative to H and V is ± 1°.
– 21 –