UC1841 UC2841 UC3841 Programmable, Off-Line, PWM Controller FEATURES DESCRIPTION • All Control, Driving, Monitoring, and Protection Functions Included • Low-current, Off-line Start Circuit • Voltage Feed Forward or Current Mode Control • Guaranteed Duty Cycle Clamp • The UC1841 family of PWM controllers has been designed to increase the level of versatility while retaining all of the performance features of the earlier UC1840 devices. While still optimized for highly-efficient bootstrapped primary-side operation in forward or flyback power converters, the UC1841 is equally adept in implementing both low and high voltage input DC to DC converters. Important performance features include a low-current starting circuit, linear feed-forward for constant volt-second operation, and compatibility with either voltage or current mode topologies. PWM Latch for Single Pulse per Period • Pulse-by-Pulse Current Limiting Plus Shutdown for Over-Current Fault • No Start-up or Shutdown Transients • Slow Turn-on Both Initially and After Fault Shutdown • Shutdown Upon Over- or Under-Voltage Sensing 1. Fault latch reset is accomplished with slow start discharge rather than recycling the input voltage to the chip. • Latch Off or Continuous Retry After Fault 2. The External Stop input can be used for a fault delay to resist shutdown from short duration transients. • PWM Output Switch Usable to 1A Peak Current 3. The duty-cycle clamping function has been characterized and specified. • 1% Reference Accuracy • 500kHz Operation • The UC1841 is characterized for -55°C to +125°C operation while the UC2841 and UC3841 are designed for -25°C to +85°C and 0°to +70°C, respectively. 18 Pin DIL Package In addition to start-up and normal regulating PWM functions, these devices include built in protection from over-voltage, under-voltage, and over-current fault conditions with the option for either latch-off or automatic restart. While pin compatible with the UC1840 in all respects except that the polarity of the External Stop has been reversed, the UC1841 offers the following improvements: BLOCK DIAGRAM Note: Positive true logic, latch outputs high with set, reset has priority. 6/93 UC1841 UC2841 UC3841 ABSOLUTE MAXIMUM RATINGS Supply Voltage, +VIN (Pin 15) (Note 2) Voltage Driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +32V Current Driven, 100mA maximum . . . . . . . . . . . . Self-limiting PWM Output Voltage (Pin 12) . . . . . . . . . . . . . . . . . . . . . . . 40V PWM Output Current, Steady-State (Pin 12) . . . . . . . . . 400mA PWM Output Peak Energy Discharge . . . . . . . . . . . . 20µJoules Driver Bias Current (Pin 14) . . . . . . . . . . . . . . . . . . . . . -200mA Reference Output Current (Pin 16) . . . . . . . . . . . . . . . . -50mA Slow-Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . 20mA VIN Sense Current (Pin 11). . . . . . . . . . . . . . . . . . . . . . . . 10mA Current Limit Inputs (Pins 6 & 7) . . . . . . . . . . . . . -0.5 to +5.5V Stop Input (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +5.5V Comparator Inputs (Pins 1, 7, 9-11, 16) . . . . . . . . . . . . Internally clamped at 12V Power Dissipation at TA = 25°C (Note 3) . . . . . . . . . . . 1000mW Power Dissipation at TC = 25°C (Note 3) . . . . . . . . . . . 2000mW Operating Junction Temperature . . . . . . . . . . -55°C to +150°C Storage Temperature Range. . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Note 1: All voltages are with respect to ground, Pin 13. Currents are positive-into, negative-out of the specified terminal. Note 2: All pin numbers are referenced to DIL-18 package. Note 3: Consult Packaging Section of Databook for thermal limitations and considerations of package. PLCC-20, LCC-20 (TOP VIEW) Q or L Package PACKAGE PIN FUNCTIONS FUNCTION PIN Comp Start/UV OV Sense Stop Reset CUR Thresh CUR Sense Slow Start RT/CT Ramp VIN Sense PWM Out Ground Drive Bias +VIN Supply 5.0V REF Inv. Input N.I. Input CONNECTION DIAGRAMS DIL-18, SOIC-18 (TOP VIEW) J or N, DW Package 1 2 3 4 5 7 8 9 10 11 12 13 14 15 17 18 19 20 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the UC1841, -25°C to +85°C for the UC2841, and 0°C to +70°C for the UC3841; VIN = 20V, RT = 20kΩ, CT = .001mfd, RR = 10kΩ, CR = .001mfd, Current Limit Threshold = 200mV, TA = TJ. UC1841 / UC2841 PARAMETER TEST CONDITIONS MIN TYP MAX 4.5 6 UC3841 MIN UNITS TYP MAX 4.5 6 mA Power Inputs Start-Up Current VIN = 30V, Pin 2 = 2.5V Operating Current VIN = 30V, Pin 2 = 3.5V 10 14 10 14 mA Supply OV Clamp IIN = 20mA 33 40 45 33 40 45 V Reference Voltage TJ = 25°C 4.95 5.0 5.05 4.9 5.0 5.1 V Line Regulation VIN = 8 to 30V 10 15 10 20 mV Load Regulation IL = 0 to 10mA 10 20 10 30 mV 5.15 V -80 -100 -80 -100 mA 50 53 50 55 kHz Reference Section Temperature Stability Over Operating Temperature Range Short Circuit Current VREF = 0, TJ = 25°C 4.9 5.1 4.85 Oscillator Nominal Frequency TJ = 25°C 47 Voltage Stability VIN = 8 to 30V Temperature Stability Over Operating Temperature Range Maximum Frequency RT = 2kΩ, CT = 330pF 0.5 45 500 2 45 1 55 0.5 43 500 1 % 57 kHz kHz UC1841 UC2841 UC3841 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the UC1841, -25°C to +85°C for the UC2841, and 0°C to +70°C for the UC3841; VIN = 20V, RT = 20kΩ, CT = .001mfd, RR = 10kΩ, CR = .001mfd, Current Limit Threshold = 200mV, TA = TJ. PARAMETER TEST CONDITIONS UC1841 / UC2841 MIN TYP MAX -11 -14 -0.9 -.95 0.3 0.4 3.9 4.2 0.5 UC3841 UNITS MIN TYP MAX -11 -14 -0.9 -.95 0.6 0.3 0.4 0.6 V 4.5 3.9 4.2 4.5 V 5 2 10 mV 2 1 5 µA 0.5 µA Ramp Generator Ramp Current, Minimum ISENSE = -10µA Ramp Current, Maximum ISENSE = 1.0mA Ramp Valley Ramp Peak Clamping Level µA mA Error Amplifier Input Offset Voltage VCM = 5.0V Input Bias Current 0.5 Input Offset Current 0.5 Open Loop Gain ∆VO= 1 to 3V 60 Output Swing (Max. Output ≤ Ramp Peak - 100mV) Minimum Total Range 0.3 CMRR VCM = 1.5 to 5.5V 70 80 PSRR VIN = 8 to 30V 70 80 Short Circuit Current VCOMP = 0V Gain Bandwidth* TJ = 25°C, AVOL = 0dB Slew Rate* TJ = 25°C, AVCL = 0dB 66 -4 1 60 3.5 80 70 80 -4 1 0.8 dB 3.5 70 -10 2 66 0.3 V dB dB -10 mA 2 MHz 0.8 V/µs PWM Section Continuous Duty Cycle Range* (other than zero) Minimum Total Continuous Range, Ramp Peak < 4.2V 4 50% Duty Cycle Clamp RSENSE to VREF = 10k 42 Output Saturation 95 4 47 52 42 IOUT = 20mA 0.2 0.4 0.2 0.4 V IOUT = 200mA 1.7 2.2 1.7 2.2 V 47 95 % 52 % Output Leakage VOUT = 40V 0.1 10 0.1 10 µA Comparator Delay* Pin 8 to Pin 12, TJ = 25°C, RL = 1kΩ 300 500 300 500 ns 3.0 3.2 3.0 3.2 V Sequencing Functions Comparator Thresholds Pins 2, 3, 5 2.8 2.8 Input Bias Current Pins 3, 5 = 0V -1.0 -4.0 -1.0 -4.0 µA Input Leakage Pins 3, 5 = 10V 0.1 2.0 0.1 2.0 µA Start/UV Hysteresis Current Pin 2 = 2.5V 170 200 220 170 200 230 µA Ext. Stop Threshold Pin 4 0.8 1.6 2.4 0.8 1.6 2.4 V Error Latch Activate Current Pin 4 = 0V, Pin 3 > 3V -120 -200 -120 -200 µA 2 3 2 3 V µA Driver Bias Saturation Voltage, IB = -50mA VIN - VOH Driver Bias Leakage VB = 0V -0.1 -10 -0.1 -10 Slow-Start Saturation IS = 10mA 0.2 0.5 0.2 0.5 V Slow-Start Leakage VS = 4.5V 0.1 2.0 0.1 2.0 µA Current Control Current Limit Offset Current Shutdown Offset Input Bias Current 370 Pin 7 = 0V Common Mode Range* 0 5 400 430 -2 -5 200 400 -0.4 Current Limit Delay* TJ = 25°C, Pin 7 to 12, RL = 1k * These parameters are guaranteed by design but not 100% tested in production. 3 3.0 360 0 10 mV 400 440 mV -2 -5 µA 3.0 V 200 400 ns -0.4 UC1841 UC2841 UC3841 FUNCTIONAL DESCRIPTION PWM CONTROL 1. Oscillator Generates a fixed-frequency internal clock from an external RT and CT. Frequency = KC RTCT where KC is a first order correction factor ≈ 0.3 log (CT X 1012). 2. Ramp Generator Develops a linear ramp with a slope defined externally by 3. Error Amplifier 4. Reference Generator 5. PWM Comparator 6. PWM Latch 7. PWM Output Switch SEQUENCING FUNCTIONS 1. Start/UV Sense 2. Drive Switch 3. Driver Bias 4. Slow Start PROTECTION FUNCTIONS 1. Error Latch 2. Current Limiting 3. External Stop dv sense voltage = RRCR dt CR is normally selected ≤ CT and its value will have some effect upon valley voltage. Limiting the minimum value for ISENSE will establish a maximum duty cycle clamp. CR terminal can be used as an input port for current mode control. Conventional operational amplifier for closed-loop gain and phase compensation. Low output impedance; unity-gain stable. The output is held low by the slow start voltage at turn on in order to minimize overshoot. Precision 5.0V for internal and external usage to 50mA. Tracking 3.0V reference for internal usage only with nominal accuracy of ± 2%. 40V clamp zener for chip OV protection, 100mA maximum current. Generates output pulse which starts at termination of clock pulse and ends when the ramp input crosses the lowest of two positive inputs. Terminates the PWM output pulse when set by inputs from either the PWM comparator, the pulse-by-pulse current limit comparator, or the error latch. Resets with each internal clock pulse. Transistor capable of sinking current to ground which is off during the PWM on-time and turns on to terminate the power pulse. Current capacity is 400mA saturated with peak capacitance discharge in excess of one amp. With an increasing voltage, it generates a turn-on signal and releases the slow-start clamp at a start threshold. With a decreasing voltage, it generates a turn-off command at a lower level separated by a 200µA hysteresis current. Disables most of the chip to hold internal current consumption low, and Driver Bias OFF, until input voltage reaches start threshold. Supplies drive current to external power switch to provide turn-on bias. Clamps low to hold PWM OFF. Upon release, rises with rate controlled by RSCS for slow increase of output pulse width. Can also be used as an alternate maximum duty cycle clamp with an external voltage divider. When set by momentary input, this latch insures immediate PWM shutdown and hold off until reset. Inputs to Error Latch are: a. OV > 3.2V (typically 3V) b. Stop > 2.4V (typically 1.6V) c. Current Sense 400mV over threshold (typical). Error Latch resets when slow start voltage falls to 0.4V if Reset Pin 5 < 2.8V. With Pin 5 > 3.2V, Error Latch will remain set. Differential input comparator terminates individual output pulses each time sense voltage rises above threshold. When sense voltage rises to 400mV (typical) above threshold, a shutdown signal is sent to Error Latch. A voltage over 1.2V will set the Error Latch and hold the output off. A voltage less than 0.8V will defeat the error latch and prevent shutdown. A capacitor here will slow the action of the error latch for transient protection by providing a typical delay of 13ms/µF. 4 UC1841 UC2841 UC3841 Start/UV Hysteresis PWM Output-Saturation Voltage Oscillator Frequency PWM Output Minimum Pulse Width Error Amplifier Open Loop Gain and Phase Shutdown Timing 5 UC1841 UC2841 UC3841 OPEN-LOOP TEST CIRCUIT Nominal Frequency = 1 = 50 kHz RTCT R1 + R2 + R3 Start Voltage = 3 +0.2R1 = 12V R2 + R3 R1 + R2 + R3 UV Fault Voltage = 3 = 8V R2 + R3 R1 + R2 + R3 OV Fault Voltage = 3 = 32V R3 FLYBACK APPLICATION (A) Current Limit = 200mV Current Fault Voltage = 600mV Duty Cycle Clamp = 50% Not shown, are protective snubbers or additional interface circuitry which may be required by the choice of the highvoltage switch, Qs, or the application; however, one example of power transistor interfacing is provided on the following page. In this application (see Figure A, next page), complete control is maintained on the primary side. Control power is provided by RIN and CIN during start-up, and by a primary-referenced low voltage winding, N2, for efficient operation after start. The error amplifier loop is closed to regulate the DC voltage from N2 with other outputs following through their magnetic coupling − a task made even easier with the UC1841’s feed−forward line regulation. REGULATOR APPLICATION (B) With the addition of a level shifting transistor, Q1, the UC1841 is an ideal control circuit for DC to DC converters such as the buck regulator shown in Figure B opposite. In addition to providing constant current drive pulses to the PIC661 power switch, this circuit has full fault protection and high speed dynamic line regulation due to its feedforward capability. An additional feature is the ability to An extension to this application for more precise regulation would be the use of the UC1901 Isolated Feedback Generator for direct closed-loop control to an output. 6 UC1841 UC2841 UC3841 Figure A. UC1841 Programmable PWM Controller In A Simplified Flyback Regulator Figure B. Overall Schematic For A 300 Watt, Off-line Power Converter Using The UC3841 For Control 7 UC1841 UC2841 UC3841 PROGRAMMABLE SOFT START AND RESTART DELAY CIRCUIT ERROR LATCH INTERNAL CIRCUITRY The Error Latch consists of Q5 and Q6 which, when both on, turns off the PWM Output and pulls the Slow-Start pin low. This latch is set by either the Over-Voltage or Current Shutdown comparators, or by a high signal on Pin 4. Reset is accomplished by either the Reset comparator or a low signal on Pin 4. An activation time delay can be provided with an external capacitor on Pin 4 in conjunction with the ≈ 100µA collector current from Q4. CURRENT MODE CONTROL VOLTAGE FEED-FORWARD COMBINED WITH MAXIMUM DUTY-CYCLE CLAMP In this circuit, R1 is used in conjunction with CR (not shown) to establish a minimum ramp charging current such that the ramp voltage reaches 4.2V at the required maximum output pulse width. The purpose of Q1 is to provide an increasing ramp current above a threshold established by R2 and R3 such that the duty cycle is further reduced with increasing VIN. Since Pin 10 is a direct input to the PWM comparator, this point can also serve as a current sense port for current mode control. In this application, current sensing is ground referenced through RCS. Resistor R1 sets a 400mV offset across R2 (assuming R2 > RCS) so that both the Error Amplifier and Fault Shutdown can force the current completely to zero. R2 is also used along with CF as a small filter to attenuate leadingedge spikes on the load current waveform. In this mode, current limiting can be accomplished by divider R3/R4 which forms a clamp overriding the output of the Error Amplifier. The minimum ramp current is: lR(MIN) = VREF − VIN SENSE 4V ≈ R1 R1 The threshold where VIN begins to add extra ramp current is: R2 + R3 VIN ≈ 5.6V R3 Above the threshold, the ramp current will be: VIN − 5.6 5.6 4 l R (VARIAB ) ≈ + − R1 R2 R3 UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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