MICROSEMI LX1691IPW

LX1691
Enhanced Multi-Mode CCFL Controller
®
TM
P RODUCTION D ATA S HEET
KEY FEATURES
DESCRIPTION
Microsemi’s proven and patented
Direct Drive architecture works with
system voltages from 3 volts to more
than 50 volts, limited only by the
external power FET’s that drive the high
voltage transformer.
The LX1691 includes the Microsemi
proven and patented strike method that
allows significant efficiency gains while
guaranteeing strong striking power at all
operating temperatures. Our method
sweeps strike frequency smoothly up to
the unloaded resonant frequency of the
lamp and high voltage transformer.
This, coupled with the LX1691’s active
high output voltage regulation, produces
just enough strike voltage without
generating unpredictable high voltage
spikes that cause arcing and component
failures. Competitive devices that
simply switch to a higher frequency for
striking do not have this “real time”
control over output voltage, and require
much more attention to transformer
design.
ƒ Simultaneous Amplitude And
Duty Cycle Dimming Modes
ƒ Resistor Programmable Min and
Max Lamp Currents
ƒ Digital Dimming Can Synch To
External Or Internal Clocks
ƒ 100 ms Power On Delay
ƒ Open Or Shorted Lamp
Regulation & Shutdown
ƒ “On Chip” Full Wave Lamp
Current & Voltage Rectifiers
ƒ 16 Pin TSSOP Package
ƒ Very Stable Oscillator with OnChip Timing Capacitor
ƒ Soft Start-Up Striking
ƒ Enhanced Digital Dimming
Resolution
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Microsemi’s LX1691 is a cost
reduced, enhanced feature set, Direct
Drive CCFL (Cold Cathode Fluorescent
Lamp) Controller. Its architecture is
based on the very popular LX1689. By
limiting VDDP to 5.5V and using
advanced processing, die size and
package pin count is decreased while
improving dimming precision.
LX1691 based inverter modules can
be designed for virtually any CCFL
appliance from digital cameras and
PDA’s to big screen monitors and
driver viewable automotive displays.
New versatile dimming circuitry can
accept digital and analog control inputs
and provides six different dimming
modes that control both lamp current
amplitude and duty cycle, either simultaneously or separately. Designers can
select normal or reverse polarity
dimming and precisely program minimum and maximum lamp currents with
resistors. The LX1691 fault shutdown
feature is enhanced to include regulation and shutdown for over voltage
and over current conditions.
BENEFITS
ƒ Low Component Count / Module
Cost / And Size
ƒ High “Nits/Watt” Efficiency
ƒ Operates Directly From a Single
Li-Ion Cell
ƒ Industries Safest And Highest
Performing Strike Voltage
Generation (Patented)
ƒ Tight Operating Frequency
Tolerance For Easier System
Level RFI Control
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
PRODUCT HIGHLIGHT
Traditional Analog
Lamp Current (mA)
_
T2
VDC
T1
Internal Digital
Lamp Current (mA)
+
BRITE_IN
_
T = 512 / DD_CLK Frequency
Direct PWM (Analog)
T
Lamp Current (mA)
+
BRITE_IN
DD_CLK
_
0
T1
T2
DD_CLK
T
T1
LX1691
T
DD_CLK
T
2
+3V
T = 512 / Lamp Frequency
+
VDC
VDC
2
Lamp Current (mA)
BRITE_IN
VDC
0
DD_CLK
T2
External Digital
2
+3V
0
T1
0
+
BRITE_IN
2
_
T2
Four of Six Dimming Modes
PACKAGE ORDER INFO
TA (°C)
MIN VDDP
MAX VDDP
-40 to +85
2.8V
5.5V
PW
Plastic TSSOP
16-PIN
LX1691IPW
Pb-free
Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1691IPWTR)
Copyright © 2003
Rev. 1.0, 7/16/2004
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 1
LX1691
®
TM
Enhanced Multi-Mode CCFL Controller
P RODUCTION D ATA S HEET
PACKAGE PIN OUT
Supply Voltage (VDDP) ..................................................................................................... 6V
Digital Input (ENABLE)....................................................................... -0.3V to VDDP +0.5V
Analog Inputs (I_SNS, OC_SNS, OV_SNS)clamped to +/- 10V. Max peak current +/-100mA
Analog Inputs (BRITE_IN)................................................................... -0.3V to VDDP +0.5V
DIM_MODE Input ................................................................................ -0.3V to VDDP +0.5V
DD_CLK Digital Input ........................................................................ 0.3V to VDDP +0.5V
Digital Output (AOUT, BOUT) .................................................................. -0.3V to VDDP +0.5V
Analog Outputs (BRITE_R, I_R, EA_OUT,BRITE_OUT) ....................... -0.3V to VDDP +0.5V
Operating Temperature Range ........................................................................ -55 to 125°C
Maximum Junction Temperature ...............................................................................150°C
Package Peak Temperature for Solder Reflow (40 Seconds Maximum Exposure) ......... 255°C (+5 -0)
Note:
GND
1
16
VDDP
AOUT
2
15
VDDA
BOUT
3
14
OP_SNS
DIM_CLK
4
13
VIN_SNS
DIM_MODE
5
12
I_SNS
BRITE_OUT
6
11
EA_OUT
BRITE_R
7
10
I_R
BRITE_IN
8
9
ENABLE
PW PACKAGE
(Top View)
Pb-free 100% Matte Tin Lead Finish
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ABSOLUTE MAXIMUM RATINGS
Exceeding these ratings could cause damage to the device. All voltages are with respect to
Ground. Currents are positive into, negative out of specified terminal.
THERMAL DATA
PW Plastic TSSOP 16-Pin
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
99°C/W
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
FUNCTIONAL PIN DESCRIPTION
PIN NAME
DESCRIPTION
Ground
VDDP
Voltage Input, 3.0 to 5.5V input range. VDDP is switched (see ENABLE) to remove power from chip. An LDO
regulator follows the switch and generates VDDA (see VDDA). The output driver stages are powered directly from
the VDDP input. Care must be taken in power distribution design to minimize transients and noise coupling from
VDDP to the VDDA output.
VDDA
Analog VDDA Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the on
chip VDDA LDO regulator. The input of the LDO is the switched VDDP supply. LDO output is normally 3.0V and is
used to drive all circuitry except the output buffers at AOUT and BOUT. Drop out voltage is typically 50mV (@
25°C) at 5mA, the average internal load. This output can supply up to a 5 mA external load. The output
capacitor recommended is <1000nF of the ceramic dielectric type.
AOUT
A buffer N-FET driver output. 10K internal pull down, ± 100 mA peak current with 3 VDC applied to VDDP pin.
BOUT
B buffer N-FET driver output. 10K internal pull down, ± 100 mA peak current with 3 VDC applied to VDDP pin.
DD_CLK*
Copyright © 2003
Rev. 1.0, 7/16/2004
Digital Dimming Clock / Dimming Polarity. An input pin that may be selected to control burst frequency for Digital
Dimming. This input can be forced to VDDA or VSS or any clock signal up to 1MHz. This pin is also used to
control the dimming polarity when operating in the internally clocked digital dimming mode*. If DIM_MODE is in
the open condition (Analog Dimming Mode) the DD_CLK input is tied to VDDA or open (internal pull-up) to select
conventional dimming polarity. It is tied to Ground for reverse polarity. Conventional polarity means that lamp
brightness increases with increasing voltage on the BRITE_IN pin. Reverse polarity means that brightness
decreases with increasing voltage. If DIM_MODE is open and a low frequency pulse is applied to DD_CLK, lamp
current amplitude is directly proportional to the voltage at BRITE_IN, and its duty cycle follows the DD_CLK
waveform, e.g., current flows when DD_CLK is high. In this mode pulse count should be greater than fault
count..
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
PACKAGE DATA
GND
LX1691
TM
®
Enhanced Multi-Mode CCFL Controller
P RODUCTION D ATA S HEET
PIN NAME
DIM_MODE*
DESCRIPTION
Dimming Mode Input. This three state input pin places the IC in Analog Dimming Mode, internal Digital Dimming
Mode, or external Digital Dimming Mode. If the input is left open or forced to VDDA / 2, Analog mode is selected.
If connected to VDDA, Digital Dimming mode with an external clock from the DD_CLK input controls the burst
timing generator. Burst frequency is the external clock frequency divided by 512. If DIM_MODE is connected
to Ground, Digital Dimming with an internal clock is selected. Burst frequency in internal clock mode is lamp
current frequency divided by 512, and burst duty cycle is directly proportional to the voltage at BRITE_IN.
OC_SNS
Over Current Sense Input. A full wave AC voltage input centered on ground that is proportional to total high
voltage transformer secondary winding current. The OC_SNS input is full wave rectified, and then applied to a
digital comparator with a 2V reference to cause peak voltages greater than 2V to establish another regulation
loop besides ISNS regulation loop. If an abnormal condition continues (>2V) then over current shut-off occurs.
Frequency range of the input signal is 10 KHz to 500KHz. Normal operating voltage is less than ± 2V, and
abnormal voltage can operate continuously as high as ± 7V peak under load fault conditions. Transients under
fault conditions can reach ± 10VPK. Input voltage greater than ± 3V peak but less than ± 10V peak may cause
saturation but will not cause malfunction, phase reversal, or reliability issues with the IC.
OV_SNS
Over Voltage Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp
voltage. The OV_SNS input will be full wave rectified, then applied to a digital comparator with a 2V reference to
cause peak voltage greater than 2V to digitally reset the PWM logic on a pulse by pulse basis.
Frequency range of the input signal is 10Khz to 500KHz. Normal operating voltage is less than ± 2V, and
abnormal voltage can operate continuously as high as ±7V peak under load fault conditions. Transients under
fault conditions can reach ± 10VPK. Input voltage greater than ± 3V peak but less than ± 10V peak may cause
saturation but will not cause malfunction, phase reversal, or reliability issues with the IC. The input has a 20K
±12K (max over temperature) pull down resistor that serves as a DC restorer to the external capacitor that
divides down lamp voltage.
I_SNS
Current Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp current.
The I_SNS input is full wave rectified and amplified, then presented to the inverting input of the current error
amplifier. During the strike mode the current sense input will regulate to 2V regardless of BRITE_IN setting.
Frequency range of the input signal is 10 KHz to 500KHz. Normal operating voltage is less than ± 2V, and
abnormal voltage can operate continuously as high as ± 7V peak under load fault conditions. Transient under
fault conditions can reach ± 10VPK. Input voltages of up to ± 3V peak are linearly rectified. Input voltage above
± 3V peak but less than ±10V peak may cause saturation but do not cause malfunction, phase reversal, or
reliability issues with the IC.
Error Amp Output. An external capacitor is connected from this pin to GND to adjust loop response of the
inverter module. This capacitor value can vary from 10pF to 5000pF in various applications.
BRITE_IN
Brightness Control Input. The input signal should be a DC voltage or a filtered high frequency pulse width
modulated digital signal. Active DC voltage range is 0.0 to 2.0V. On chip signal conditioning amplifiers clip
inputs above 2V.
ENABLE
Chip Enable Input. If logic high, all functions are enabled. If logic low, internal power is disconnected from the
VDDP pin, disabling all functions. Maximum current into VDDP when ENABLE < 0.3V, VDDP<5V, is 10µA. ENABLE
may be connected directly to VDDP if the disable function is not used.
I_R
Current Reference Resistor Input. Connects to an external resistor that determines the magnitude of internal
bias currents. The nominal lamp frequency can be adjusted by varying this resistor value in the range of 40K to
100K Ohms.
1.00V
II_R =
RI_R
*See dimming mode truth table for a summary of dimming operation with respect to DD_CLK & DIM_MODE inputs.
Copyright © 2003
Rev. 1.0, 7/16/2004
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
PACKAGE DATA
EA_OUT
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FUNCTIONAL PIN DESCRIPTION (CONTINUED)
LX1691
®
TM
Enhanced Multi-Mode CCFL Controller
P RODUCTION D ATA S HEET
PIN NAME
BRITE_OUT
DESCRIPTION
Brightness Reference Current Output. This variable current source is the mirror of BRITE_R current multiplied
by the BRITE_IN signal and becomes the reference voltage to the error amplifier when DIM_MODE is open or
½ VDDA. Connecting an additional resistor to VDDA determines minimum lamp current in order to prevent fault
condition. A light sensor (LX1970) may be used in conjunction with BRITE_OUT to change amplitude of lamp
current in response to ambient light intensity.
VBRITE_OUT = VBRITE_IN X BRITE_OUT/BRITE_R (When DD_CLK is connected to VDDA)
VBRITE_OUT = (2-VBRITE_IN) X BRITE_OUT/BRITE_R (When DD_CLK is connected to GND)
When DIM_MODE is GND or VDDA, then BRITE_OUT has to be biased with an external resistor.
BRITE_R
Dedicated bias resistor for BRITE_OUT current source when DIM_MODE is open or ½ VDDA. Connecting an
additional resistor to VDDA determines minimum Burst Duty Cycle in digital dimming. A light sensor (LX1970)
may be used in conjunction with BRITE_R to change Burst Duty Cycle in response to ambient light intensity.
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FUNCTIONAL PIN DESCRIPTION (CONTINUED)
DIMMING TABLE
DIM_
MODE
DESCRIPTION
Reversed Internal Digital
Dimming
Internally Clocked PWM
Burst Generator, External
Input to BRITE_IN
Conventional Internal
Digital Dimming
Internally clocked PWM
Burst Generator, External
Input to BRITE_IN
Conventional External
Digital Dimming
Externally clocked PWM
burst generator, external
input to BRITE_IN
Low
Voltage at BRITE_IN controls lamp current burst duty cycle. Duty cycle is inversely
proportional to voltage at BRITE_IN. Burst period is LX1691 oscillator frequency
divided by 1024 (lamp current frequency divided by 512). An external voltage
connected to the BRITE_OUT pin sets lamp current amplitude.
High
Voltage at BRITE_IN controls lamp current burst duty cycle. Duty cycle is directly
proportional to voltage at BRITE_IN. Burst period is LX1691 oscillator frequency
divided by 1024 (lamp current frequency divided by 512). An external voltage
connected to the BRITE_OUT pin sets lamp current amplitude
VDDA
Pulse
Voltage at BRITE_IN controls lamp current burst duty cycle. Duty cycle is directly
proportional to voltage at BRITE_IN. Burst period is DD_CLK input divided by 512. An
external voltage connected to the BRITE_OUT pin sets lamp current amplitude.
Low
High
½
VDDA
or open
Pulse
Voltage at BRITE_IN controls lamp current amplitude. Amplitude is inversely
proportional to voltage at BRITE_IN.
Voltage at BRITE_IN controls lamp current amplitude. Amplitude is directly proportional
to voltage at BRITE_IN.
Voltage at BRITE_IN controls lamp current amplitude. Amplitude is directly proportional
to voltage at BRITE_IN.
Burst period and duty cycle are directly proportional to signal at DD_CLK input pin. If
held low, duty cycle is 0% (Zero duty will cause a fault shut down. Minimum duty to
prevent fault shut down is lamp and temperature dependent. User must characterize
lamp to determine minimum duty cycle.). If held high, duty cycle is 100% (full
brightness).
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 4
PACKAGE DATA
Conventional Analog
Amplitude Dimming with
External Direct PWM
Control
CONDITIONS
0V
Reversed Analog
Amplitude Dimming
Conventional Analog
Amplitude Dimming
Copyright © 2003
Rev. 1.0, 7/16/2004
DD_
CLK
LX1691
Enhanced Multi-Mode CCFL Controller
®
TM
P RODUCTION D ATA S HEET
Parameter
Min
LX1691
Typ
Units
Max
Supply Voltage (VDDP)
2.8
5.5
Digital Input (ENABLE)
0
5.5
V
Analog Inputs (I_SNS, OC_SNS, OV_SNS)
-2
2
VPK
BRITE_IN Linear DC Voltage Range
0
BRITE_OUT, BRITE_R Maximum Source Current
V
2
V
100
µA
Digital Inputs (DIM_MODE, DD_CLK)
0
5.5
V
Internal Oscillator Frequency (I_R Resistor Range 42K to 175K)
60
250
KHz
20
nC
Maximum Output Gate Charge (AOUT, BOUT)
10
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, the following specifications apply over the operating ambient temperature -40°C ≤ TA ≤ 85°C except where
otherwise noted. Test conditions: VDDP =3.3 to 5.5 V, I_R =80.6KΩ, BRITE_R = BRITE_OUT = 20KΩ, OVSNS = OCSNS = 0V,
DD_CLK = DIM_MODE = Floating
Parameter
`
`
V_BATT
VDDA
VDROPOUT
IBB
IDD_SLEEP
Run Threshold
VTH_ENRUN
Shutdown Threshold
VTH_ENSHDN
LX1691
Typ
Max
Units
VDDP= 3.3 to 5.5V, I Load = 0 mADC
I Load = 0 mADC
CAOUT = CBOUT = 1000pF; fOSC = 130kHz
VENABLE = 0.8V, VDDP = 5.5V
2.8
2.85
3.0
50
10
10
5.5
3.15
150
15
V
V
mV
mA
µA
1.5
0.8
2.8
V
1.1
V
Input High Current
IIH_ENABLE
ENABLE = 2V
2
12
µA
Input High Current
IIH_ENABLE
ENABLE = 5V
35
80
µA
Input Low Current
IIL_ENABLE
ENABLE = 0V
0
1
µA
VTH_UVLO
Run Mode
2.55
2.8
V
-1
UNDER VOLTAGE LOCKOUT
UVLO Threshold
Shutdown Mode
UVLO Hysteresis
2.1
VH_UVLO
2.35
200
mV
V_IR
Pin I_R Max Source Current
Voltage Reference Voltage
(Internal node)
OUTPUT BUFFER BLOCK
80.6K
0.975
IMAX_IR
1.025
100
1.98
V2P0
V
µA
2.02
V
Output Sink Current
ISK_OUTBUF
VAOUT, VBOUT = VDDP
100
mA
Output Source Current
IS_OUTBUF
VAOUT, VBOUT = 0V
100
mA
Copyright © 2003
Rev. 1.0, 7/16/2004
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 5
ELECTRICALS
BIAS BLOCK
Voltage at Pin I_R
`
Min
ENABLE INPUT
Startup Threshold
`
Test Conditions
POWER
Power Supply Input Voltage
Regulator Output Voltage
VDDA Drop Out Voltage
VDDP Operating Current
Sleep Mode Current
`
Symbol
LX1691
Enhanced Multi-Mode CCFL Controller
®
TM
P RODUCTION D ATA S HEET
Parameter
`
Maximum Lamp Run Frequency
FRAMP_STK
250
262
63
65
67
KHz
61
65
69
KHz
Max
Units
3
KHz
FLAMP_RUN
Lamp Run Frequency
Lamp Run Frequency Regulation over
VDDP
Internal Digital Dimming
Burst Frequency
PWM BLOCK
FLAMP_RUN
Lamp is ignited, I_R = 80.6K, TA = 25°C
Lamp is ignited, I_R = 80.6K
FLAMP_REG
3.3 < VDDP < 5.5V
0.1
%
DIM_MODE = 0V, FLAMP_RUN / 512, I_R = 80.6K
127
Hz
Error Amp Transconductance
GM_EAMP
FBURST
150
µmho
Error Amp Output Source Current
IS_EAMP
100
µA
Error Amp Output Sink Current
ISK_EAMP
100
µA
Error Amp Output High Voltage
VH_EAMP
BRITE_OUT – EA_IN = 50mV
Error Amp Output Low Voltage
VL_EAMP
EA_IN – BRITE_OUT = 50mV
Error Amp Input Offset Voltage
VOS_EAMP
60
2.5
2.9
0.015
V
0.5
V
30
mV
DCMAX
47
%
Ramp Valley Voltage
RVV
100
mV
Ramp Peak Voltage
RPV
2.1
V
DD_CLK INPUT
To VDDA
50
Input High Threshold
VTH_DD_CLK
Conventional Dimming
1.6
Input Low Threshold
VTL_DD_CLK
Reverse Dimming
Input High Current
IIH_DD_CLK
DD_CLK = 5V; VDDP=5V
Input Low Current
IIL_DD_CLK
DD_CLK = 0V; VDDP=5V
0.4
KΩ
2.0
V
45
70
µA
-65
-100
µA
0.9
V
DIM_MODE INPUT
Low State
`
LX1691
Typ
Ratio to run frequency, I_SNS = OV_SNS = 0V
FRAMP_RUNMAX Lamp is ignited; I_R = 20K
Pull-up Resistance
`
Min
Lamp Run Frequency
Max Duty Cycle
`
Test Conditions
RAMP GENERATOR
Max Strike / Run Frequency Ratio
`
Symbol
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ELECTRICAL CHARACTERISTICS (CONTINUED)
]
VTL_TRI_
0.4
Floating State
VTF_TRI
1.2
High State
VTH_TRI
Input High Current
IIH_TRI
Input Low Current
IIL_TRI
0.85
V
1.35
1.8
V
2.35
2.8
V
DIM_MODE = 5V
70
120
µA
DIM_MODE = 0V
-25
-50
µA
1
µA
25
60
mV
ANALOG DIMMER BLOCK
BRITE_IN Input Current
BRITE_IN II BRITE_IN = 0 to 5V
Conventional Dimming
BRITE_OUT
0
BRITE_IN > 2.05V
1.9
2.0
2.10
V
BRITE_ IN < 0V
1.9
2.0
2.1
V
0
25
60
mV
BRITE_IN > 2.05V
Copyright © 2003
Rev. 1.0, 7/16/2004
-1
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 6
ELECTRICALS
BRITE_IN = 0V
LX1691
Enhanced Multi-Mode CCFL Controller
®
TM
P RODUCTION D ATA S HEET
Parameter
`
Symbol
Reverse Dimming
Duty Cycle
`
Min
LX1691
Typ
Max
Units
DIGITAL DIMMER BLOCK
Conventional Dimming
Duty Cycle
`
Test Conditions
TIMING GENERATOR BLOCK
Number of Lamp Return Current
Cycles before Run Mode
I_SNS Run Mode Checking Interval
NIGNITE
Minimum Duty Cycle; BRITE_IN = 0.1V
2
5
7
%
Maximum Duty Cycle; BRITE_IN =1.90V
90
95
100
%
Maximum Duty Cycle; BRITE_IN ≥ 2.05V
100
%
Maximum Duty Cycle; BRITE_IN = 0.0V
100
%
Maximum Duty Cycle; BRITE_IN = 0.1V
90
95
100
%
Minimum Duty Cycle; BRITE_IN = 1.95V
2
5
7
%
To switch to Run Mode
Lamp return current cycles
4
Cycles
2048
Cycles
Strike Validation Threshold
To switch to run mode, TA =25°C
700
mVPK
Fault Comparator Threshold Run
Number of Strike sweep Attempts
NSTRK_FAULT
Before Fault Shutdown
Power On Delay Before Strike
TD_PWRON
Number of Sweeping Strike Frequency
Steps per Attempt
Number of Output Pulses per Striking
Step
LAMP FEEDBACK CONDITIONING BLOCK
I_ SNS Open Lamp Fault Detect, TA =25°C
300
mVPK
I_SNS Input Current
I_SNSIIN
FLAMP Sweep Cycles, I_SNS = 0V_SNS = 0V
I_R = 80.6K
6
125
ms
512
Steps
16
Cycles
I_SNS = +2.5V
14
µA
I_SNS = -2.5V
-40
µA
OV_SNS Input High Threshold
VTH_OV_SNS
Active Over Voltage Protection
± 2.2
VPK
OV_SNS Input Low Threshold
VTL_OV_SNS
Inactive Over Voltage Protection
± 1.8
VPK
OV_SNS = +2.5V
140
µA
OV_SNS Input Current
OV_SNSIIN
OV_SNS = -2.5V
-170
µA
OC_SNS Input High Threshold
VTH_OC_SNS
Active Over Current Protection
± 2.2
VPK
OC_SNS Input Low Threshold
VTL_OC_SNS
Inactive Over Voltage Protection
± 1.8
VPK
OC_SNS Input Current
Full Wave Rectifiers RMS Transfer
I_SNSRMS
OC_SNS = 10V
14
µA
OC_SNS = -2.5V
-40
µA
I_SNS = 0.3VDC, TA = 25°C
0.3
V
I_SNS = 2.5VDC, TA = 25°C
2.5
V
I_SNS = -0.3VDC, TA = 25°C
0.3
V
I_SNS = -2.5VDC, TA = 25°C
2.5
V
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 7
ELECTRICALS
Copyright © 2003
Rev. 1.0, 7/16/2004
OC_SNSIIN
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ELECTRICAL CHARACTERISTICS (CONTINUED)
-
normal polarity
R
reverse polarity
A
B
DDCLK >>
high=normial
over current
+
Binary
Counter
over voltage
-
+
Binary
Counter
+
Binary
Counter
MUX
OUT
SEL
Binary
Counter
analog
dim
>>
digital dim,
internal
digital dim,
external
+
_
Q
B
A
SEL
OUT
MUX
QB
fault
D
CLK
Voltage
DAC
VDD >>
ignite
2V >>
BRITE_OUT >>
Ram Gen
+
Current
DAC
-
R
1V
-
+
-
2V
VREF
+
Binary
Counter
>> TBPER
>> digital dim, internal
analog dim
>> digital dim, external
TBPER>>
DDCLK >>
3.0V
0V
A/D 1.5V
>>2V
Full Wave
Rectifiers
Bias
+
_
+
_
VDD
analog dim >>
direct digital dim
R
CLK
D
Q
QB
BRITE_R
BRITE_OUT
BLOCK DIAGRAM
pwmgate
AOUT
BOUT
EAOUT
Microsemi
WWW . Microsemi .C OM
BRITE_IN
DDCLK
DIM_MODE
OCSNS
OVSNS
ISNS
VDDP
VDDA
I_R
ENABLE
GND
-
Enhanced Multi-Mode CCFL Controller
®
TM
Page 8
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Copyright © 2003
Rev. 1.0, 7/16/2004
-
LX1691
P RODUCTION D ATA S HEET
BLOCK DIAGRAM
FIGURE 1 – Simplified Block Diagram
+
+
LX1691
Enhanced Multi-Mode CCFL Controller
®
TM
P RODUCTION D ATA S HEET
WWW . Microsemi .C OM
TYPICAL APPLICATION
CN1
VIN
GND
BRITE
ENABLE
1
2
3
4
FDC6305N
R8
10 Ω
6
C6
100nF
50V, 20%
SGE2697-1
1
6
1
2
1
275VRMS
3.5mARMS
100KHz
4
3
3
C1
1.0µF 20%
6.3V
5
VDDP
AOUT
VDDA
3
VDDA
BOUT
OC_SNS
DD_CLK
OV_SNS
5
I_SNS
DIM_MODE
6
7
8
C7
2.0pF
16
GND
2
4
4,5
C5
22µF
10V 20%
2
C2
100nF
1
1:53
BRITE_OUT EA_OUT
BRITE_R
I_R
BRITE_IN
ENABLE
15
VDDA
14
13
12
R5
470
11
R6
200
10
9
R4
51.1K
C4
4.7nF
C9
2.2nF
LX1691IPW
R1
10K
R7
287
C8
1.5nF 5%
16V COG
VDDA
R3
21.0K
R2 C3
10K 100nF
Copyright © 2003
Rev. 1.0, 7/16/2004
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
APPLICATIONS
FIGURE 2 – LX1691 Inverter for PDA With Single Cell LI_ION Battery, Digital Dimming maximum current of
3.5mARMS @ 100KHz set to 1.33mA via R2/R3.
Lamp Current
R3
R7
mARMS
Brite Input Control Range (Linear DCV)
5.0
21.0K
200
Min. Brite ‘Lo’ = 150mV
4.5
21.0K
221
Max. Brite ‘Hi’ = 2.0V
4.0
21.0K
249
Burst Rate Frequency = 200 Hz
3.5
21.0K
287
Enable Input
3.0
32.4K
249
Off Logic ‘Lo’ <= 0.80V
2.5
32.4K
294
On Logic ‘Hi’ >= 1.7V
2.0
60.4K
226
1.5
60.4K
301
Page 9
LX1691
TM
®
Enhanced Multi-Mode CCFL Controller
P RODUCTION D ATA S HEET
FEATURE
On-Chip LDO Regulator
An LDO regulator keeps critical analog control circuits
operating optimally over the entire input voltage range. Brightness
control voltage and operating frequency are extremely stable.
Under Voltage Lockout
If the battery input voltage is too low for the controller to
function properly, it will turn itself off, preventing spurious
operation. If the battery voltage falls to less than 1V where UVLO
is no longer guaranteed, 10K pull down resistors on the AOUT and
BOUT pins insure the external power FETs cannot be biased on.
Power On Delay
A power up reset that delays AOUT and BOUT turn on for
approximately 100 milliseconds after power is applied. This give
extra time for the BRITE_IN source voltage to stabilize so the
lamp is not inadvertently powered up at high brightness and then
suddenly lowered, creating an undesirable light flash.
Enhanced BRITE Conditioning Circuitry
The BRITE_IN pin offers a high impedance input with a linear
control range of 0 to 2.0V The function of the pin depends on
which of six dimming modes the controller is programmed. (see
dimming table page 4) A new feature of the LX1691 allows the
DD_CLK input to control the burst frequency and duty cycle while
the BRITE_IN input controls the output current amplitude (see
additional information below).
Digital or Analog Dimming Modes
A DIM_MODE input pin selects either Analog or Digital mode.
In Analog mode DC voltage at BRITE_IN controls lamp current
amplitude. In Digital mode it controls digital dimming duty cycle.
When in Digital mode, the dimming burst frequency can be
synchronous to lamp current by selecting internal clocking, or to
an external clock. With an external clock source, burst frequency
will be the clocks frequency divided by 512. When using the
internal clock source the burst frequency will be the internal
oscillator divided by 1024 which is equivalent to lamp current
frequency divided by 512.
Strike Voltage Generation
Improved strike voltage generation circuits ramp strike voltage
slowly to programmed maximum potential and hold it there for
approximately 350mSec @65Hz operating frequency. This insures
a worst case lamp will strike at any temperature. Strike potential is
removed immediately when the lamp strikes or if the time limit is
reached.
Strike Detection
The LX1691 includes a new lamp strike detection scheme that
saves a package pin and three external components. Internal circuits
monitor lamp current pulses at the I_SNS input to determine if the
lamp strikes and if it stays ignited once operational.
Fault Time Out
If the lamp fails to ignite within approximately 350mSec, or if it
extinguishes after ignition, or if the clock signal at the DD_CLK pin
terminates when in external digital dim mode, the output drive is
shut down.
Fault mode will also be invoked if the lamp is short circuited or
left open for more than 350mSec.
On Chip Rectifiers
Integrating full wave rectifiers for each of three lamp inputs
significantly reduces lamp feedback component count. Current
Sense (I_SNS), Over Current Sense (OC_SNS) and Over Voltage
Sense (OV_SNS) signals are detected using only one external
scaling resistor or capacitor each. Rectification accuracy is
improved with high performance on chip rectifiers to provide better
lamp current and voltage regulation.
Complete Fault Protection
In addition to the lamp fault time out, maximum output voltage
and current under all fault conditions is regulated. Open circuit
voltage can never go higher than the preset maximum strike
potential and total current from the circuit is safely limited with a
scaling resistor. UL safety specifications can now be easily met in
any application.
Familiar Magnetics
The LX1691 can use the same magnetics as all other Direct Drive
controllers. Refer to Application Note 13 for transformer design
and power FET selection criteria.
Copyright © 2003
Rev. 1.0, 7/16/2004
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 10
DESCRIPTION
Brightness Polarity and Dual Mode Dimming Control
In Analog dimming mode the IC can be programmed to either
increase or decrease lamp current amplitude as a function of
increasing signal at the BRITE_IN pin by simply connecting the
DD_CLK input to VDDA or ground (see Dimming Table). If
simultaneous amplitude control and digital dimming is desired,
apply a PWM signal to DD_CLK. The lamp current waveform
will exactly follow DD_CLK (DD_CLK is not divided in this
mode); e.g., lamp current flows when DD_CLK is high and stops
when it is low.
REVIEW
In Digital dimming mode, lamp current duty cycle is either
directly or inversely proportional to DC input voltage at the
BRITE_IN pin, depending on the state of DD_CLK. If external
clock is selected, duty cycle will be directly proportional to voltage
at BRITE_IN and the burst period will be DD_CLK period X 512.
Lamp current amplitude can be set and varied by applying a
separate DC voltage at the BRITE_OUT pin. This voltage can
range from zero to 2.0 VDC. Zero volts will produce zero current
(and therefore a lamp fault). 2.0V will produce the maximum
current as defined by the value of the current sensing resistor from
ISNS to GND.
WWW . Microsemi .C OM
DETAILED DESCRIPTION
LX1691
®
TM
Enhanced Multi-Mode CCFL Controller
P RODUCTION D ATA S HEET
DETAILED DESCRIPTION (CONTINUED)
Four operating modes: Power On Delay, Strike, Run, and Fault
modes are employed by the LX1691. Upon power up or ENABLE
going true, Power On Delay is automatically invoked.
Immediately after termination of Power On Delay, or ENABLE
going true, strike mode is entered. After a successful strike, e.g.,
lamp is ignited, run mode is entered. If ignition is unsuccessful, or
if the lamp extinguishes while running, Fault mode is entered.
Lamp ignition is determined by monitoring the lamp current
feedback voltage at pin I_SNS. Lamp current cycles are counted
from the beginning of Strike mode. If 4 or more complete cycles
occur the lamp is declared ignited. If less than 4, the lamp is
considered not ignited and Strike mode continues until ignition is
detected or strike time out (approximately 350ms) is reached.
After run mode is entered lamp current pulse count is sampled
several times a second to determine that the lamp has not
inadvertently extinguished. If lamp current pulses are counted in
each sample, Run mode is maintained. Otherwise, Fault mode is
entered. Strike mode can be entered only once for each on/off cycle
of either VDDP or ENABLE. This insures that even intermittent
lamp failures cannot cause the module to continuously output
maximum strike voltage.
During strike, operating frequency is swept from the normal run
value approximately to 3X run frequency. This will excite the
unloaded resonant frequency of the transformer and lamp load to
generate the required lamp striking voltage. If the lamp has not
ignited after about 350mS, a fault is declared and the A & B
outputs are shut off.
If while strike frequency is sweeping, the over voltage set point
at OV_SNS is detected or overcurrent voltage set point at
OV_SNS is deteted the, strike frequency will hold at the frequency
value until either the lamp strikes or the timeout is reached. This
causes maximum strike potential to be continuously impressed
across the lamp for the entire strike period.
Also, if while strike frequency is sweeping, the over current set
point at OC_SNS is detected, strike frequency will hold at the
present value until either the lamp strikes or the timeout is reached.
This insures short circuit current regulation will be maintained, thus
enabling UL fault requirements to be easily met at the inverter
module level.
Strike Mode
Entered from Power On Delay, or upon an ENABLE sequence.
Control of the Ramp Generator frequency is switched to the DAC
output. Frequency is increased from its normal run value to up to
three times that value for up to 6 sweeps If while strike frequency is
sweeping, the set points at OV_SNS and / or OC_SNS are detected,
strike frequency will freeze at the present value until either the lamp
strikes or the timeout is reached. Strike Mode is terminated by
reaching 6 sweep counts or by detecting lamp ignition. If strike is
successful, Run Mode is entered. If unsuccessful, Fault mode is
entered.
Run Mode
Entered only by detection of a successful Strike. Frequency
control is immediately switched to a fixed reference that sets the
programmed run frequency. The lamp current cycle counter is
monitored to insure at least 4 current cycles received during each
period. If less than 4, the lamp is considered extinguished and the
Fault Mode is entered.
Fault Mode
Fault Mode may be entered from either Strike or Run Mode as
described above. In Fault Mode, the A & B output buffers are
forced low. Fault mode may be cleared by cycling ENABLE off
then on, or by removing and applying VDDP.
Design Procedure
Selecting the I_R resistor value
This resistor determines the value of several internal reference
currents that control timing. It must be chosen first, and will be in
the range of 40 to 120K ohms. We use an 80.6K, 1% low TCR
value in our designs to set nominal lamp current frequency to
65kHz. The output frequency is approximated by the following
formula: RI_R = 5.24E9 / FLAMPOUT/HZ.
Driving the BRITE_IN Input
The BRITE_IN input circuitry includes on-chip active voltage
clamps that ignore input voltage greater than 2.0V.
Input
impedance is very high so it can also be driven from a 100K
potentiometer with no offset error. BRITE_IN can be a DC voltage,
or a higher frequency externally filter PWM The BRITE_IN input
has a linear active range between 0.0 and 2.0V
DESCRIPTION
The only way to re-initiate the strike process is to either cycle
VDDP or ENABLE off and on.
If ignition is successful, ramp frequency immediately returns to
its programmed run value.
Power ON Delay Mode
All functions are activated except that AOUT and BOUT are
inhibited. Delay is in the 100mSec range and is determined by a
counter. Power on delay is activated at every VDDP power up
sequence and ENABLE sequence.
Copyright © 2003
Rev. 1.0, 7/16/2004
WWW . Microsemi .C OM
LX1691 Operation
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 11
LX1691
Enhanced Multi-Mode CCFL Controller
®
TM
P RODUCTION D ATA S HEET
VDDA OVER TEMPERATURE
2.990
7.4
VDDA Voltage (V)
IVDDP Current (mA)
7.6
7.2
7.0
6.8
6.6
3.15V
5.0V
5.5V
6.4
6.2
-40
-20
0
20
40
60
80
2.985
2.980
2.975
2.970
3.15V
5.0V
5.5V
2.965
-40
100
-20
20
40
60
80
100
IVDDP over Temperature
VDDA Over Temperature
VDDA DROPOUT VOLTAGE
I_R VOLTAGE OVER TEMPERATURE
150
1010
125
1005
I_R Voltage (V)
Dropout Voltage (V)
0
Ambient Temperature (°C)
Ambient Temperature (°C)
100
75
50
0m A
5m A
25
0
1000
995
990
80.6K
10K
985
980
-40
-20
0
20
40
60
80
100
-40
-20
Ambient Temperature (°C)
0
20
40
60
80
I_R Voltage over Temperature
ENABLE THRESHOLD OVER TEMP
UVLO THRESHOLD OVER TEMP
2.0
1.6
1.4
1.2
1.0
0.8
-40
-20
0
20
40
60
80
100
Ambient Temperature (°C)
2.7
2.6
2.5
2.4
VT Turn-on
VT Turn-off
2.3
2.2
-40
-20
0
20
40
60
80
100
Ambient Temperature (°C)
UVLO Threshold over Temperature
Enable Threshold over Temperature
Copyright © 2003
Rev. 1.0, 7/16/2004
2.8
CHARTS
Threshold Voltage (V)
VT Turn-on
VT Turn-off
1.8
100
Ambient Temperature (°C)
VDDA Dropout Voltage over Temperature
Threshold Voltage (mV)
WWW . Microsemi .C OM
IVDDP OVER TEMPERATURE
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 12
LX1691
Enhanced Multi-Mode CCFL Controller
®
TM
P RODUCTION D ATA S HEET
FWRECT TRANSFER OFFSET
75
Offset Voltage (mV)
Threshold Voltage (V)
66.5
66
65.5
65
64.5
N TC
P TC
64
63.5
-40
-20
0
20
40
60
80
50
25
0
-25
-50
EAIN
-75
-2.5
100
-1.5
Ambient Temperature (°C)
-0.5
0.5
1.5
2.5
ISNS Voltage (V)
Lamp Frequency over Temperature
FWRECT Transfer Offset
FAULT THRESHOLD OVER TEMP
STRIKING THRESHOLD OVER TEMP
698
285
Threshold Voltage (mV)
Threshold Voltage (mV)
WWW . Microsemi .C OM
LAMP FREQ OVER TEMPERATURE
280
275
270
265
260
RUN
255
-40
-20
0
20
40
60
80
100
695
692
689
686
683
STRIKE
680
-40
-20
0
20
40
60
80
100
Ambient Temperature (°C)
Ambient Temperature (°C)
Fault Threshold over Temperature
Striking Threshold over Temperature
VDAC PEAK OVER TEMPERATURE
VDAC VALLEY OVER TEMPERATURE
96.5
VDAC Valley Voltage (mV)
1.91
1.90
1.89
1.88
1.87
VTH
1.86
-40
-20
0
20
40
60
80
100
92.5
90.5
88.5
86.5
VTH
84.5
-40
-20
0
20
40
60
80
100
Ambient Temperature (°C)
Ambient Temperature (°C)
VDAC Valley over Temperature
VDAC Peak over Temperature
Copyright © 2003
Rev. 1.0, 7/16/2004
94.5
CHARTS
VDAC Peak Voltage (mV)
1.92
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 13
LX1691
Enhanced Multi-Mode CCFL Controller
®
TM
P RODUCTION D ATA S HEET
PW
WWW . Microsemi .C OM
MECHANICAL DRAWING
16-Pin Thin Small Shrink Outline (TSSOP)
P
E
1 23
F
D
A H
SEATING PLANE
B
Dim
MILLIMETERS
MIN
MAX
0.85
0.95
0.19
0.30
0.09
0.20
4.90
5.10
4.30
4.50
0.65 BSC
0.05
0.15
–
1.10
0.50
0.75
0°
8°
6.25
6.50
–
0.10
L
C
M
INCHES
MIN
MAX
0.033
0.037
0.007
0.012
0.0035 0.008
0.192
0.200
0.169
0.177
0.025 BSC
0.002
0.005
–
.0433
0.020
0.030
0°
8°
0.246
0.256
–
0.004
MECHANICALS
A
B
C
D
E
F
G
H
L
M
P
*LC
G
Note:
1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006”) on any side. Lead dimension shall not
include solder coverage.
Copyright © 2003
Rev. 1.0, 7/16/2004
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 14
LX1691
TM
®
Enhanced Multi-Mode CCFL Controller
P RODUCTION D ATA S HEET
WWW . Microsemi .C OM
NOTES
NOTES
PRODUCTION DATA – Information contained in this document is proprietary to
Microsemi and is current as of publication date. This document may not be modified in
any way without the express written consent of Microsemi. Product processing does not
necessarily include testing of all parameters. Microsemi reserves the right to change the
configuration and performance of the product and to discontinue product at any time.
Copyright © 2003
Rev. 1.0, 7/16/2004
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 15