PHILIPS NE5562D

Philips Semiconductors
Product specification
Switched-mode power supply control circuit
DESCRIPTION
NE/SE5562
PIN CONFIGURATION
The NE/SE5562 is a single-output control circuit for switched-mode
power supplies. This single monolithic IC contains all control and
protection features needed for full-featured switched-mode power
supplies.
D, F, N Packages
FEED FORWARD 1
The 100mA source/sink output is designed to drive power FETs
directly. The associated output logic is designed to prevent double
pulsing or cross-conduction current spiking on the output.
20 GROUND
CT 2
19 OUTPUT
RT 3
18 DEMAG OVERVOLT IN
EXTERNAL MOD IN 4
17 V
S
DUTY CYCLE CONTROL 5
All of the control and protect features work cycle-by-cycle up to the
maximum operating frequency of 600kHz.
16 C DELAY
REMOTE ON/OFF 6
VI
For ease of interface, all digital inputs are TTL or CMOS compatible.
15 OUT INVERT CONTROL
7
14 CURRENT SENSE
FEEDBACK VOLTAGE 8
The NE5562 is supplied in 20-pin glass/ceramic (Cerdip), plastic
DIP, and plastic SO packages. The NE grade part is characterized
and guaranteed over the commercial ambient temperature range of
0°C to +70°C and junction temperature range of 0°C to +85°C. The
SE5562 is supplied in the glass/ceramic (Cerdip) package. The SE
grade part is characterized and guaranteed over the ambient
temperature range of -55 to +125°C and junction temperature range
of -55 to +135°C.
VZ
13 AUX COMP HYSTERESIS
9
12 AUX COMP INPUT
ERROR AMP OUT 10
11 EXTERNAL SYNC IN
TOP VIEW
SL00388
Figure 1. Pin Configuration
• Auxiliary comparator, with adjustable hysteresis
• Loop fault protection
• Demagnetization/overvoltage protection
• Duty cycle adjust and clamp
• Feed-forward control
• External synchronization
• Total shutdown after adjustable number of overcurrent faults
• Soft-start
FEATURES
• Stabilized power supply
• Temperature-compensated reference source
• Sawtooth generator
• Pulse width modulator
• Remote on/off switching
• Current limiting (2 levels)
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
20-Pin Plastic Small Outline (SO) Package
0 to +70°C
NE5562D
1021B
20-Pin Plastic Dual In-Line Package (DIP)
0 to +70°C
NE5562N
SOT146-1
-55°C to +125°C
SE5562F
SOT146-1
20-Pin Ceramic Dual In-Line Package (CERDIP)
1994 Aug 31
1
DWG #
853-0811 13721
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
BLOCK DIAGRAM
FEEDFORWARD
1
11
EXTERNAL
SYNC IN
+
+
–
+
S
CLOCK
TIME
DELAY
OSC Q
LATCH
3
2
–
+
R
DELAYED
CLOCK
OFF
DEMAG/OV
IN
18
OSCILLATOR
0V
OFF
ON
3.80V
1.5V
REMOTE
ON/OFF
6
ON
NORM
–
+
ON/OFF
COMP
ERROR
AMP
OUT 10
S
+
–
–
–
+
–
ERROR
AMP
FEEDBACK 8
VOLTAGE
R
OC1
–
+
0.955V
POWR
OUTPUT
NOR
OUTPUT
INVERT
CONTROL
15
NORM
– +
LOOP FAULT
COMP
2k
OVERCURRENT 1
COMP
0.528V
EXTERNAL
MOD
4
IN
CURRENT
SENSE
14
0.645V
OVERCURRENT 2
COMP
– +
DUTY CYCLE
CONTROL 5
CLOCK
–
+
SLOW
OC1
START
0C2 COMP
1:1
3.80V
11µA
START/
STOP Q
LATCH
S
POWER
SUPPLY
CKTS
+V
–
+
0.528V
SHUT
DOWN
LATCH
NORM
S
0.645V
3.80V
LOW BULK
R
OC ACCUM
COMP
NORM
BULK
SENSE 3.80V +
–
COMP
– +
OC2
80µA
AUXILIARY
COMP
HYSTERESIS
AUXILIARY
COMP
INPUT
13
VS
17
VZ
9
LV STOP
TRIP
CDELAY
16
OC1
NORM
Q
1:1
+V
GND
20
R
OC1-2
LATCHES
OC CHARGE PUMPS
0.955V
OC2
0.955V
1µA
OUTPUT
19
OUTPUT Q
LATCH
PWM
COMP
3.80V
DEMAG/OV
COMP
VI
7
12 3.80V
SL00389
Figure 2. Block Diagram
1994 Aug 31
2
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Supply
VS
voltage-fed mode (Pin 17)
16
V
ICC
current-fed mode (Pin 7)
30
mA
100
mA
Sync (Pin 11)
VS
V
Duty cycle control (Pin 5)
VZ
V
Remote on/off (Pin 6)
VS
V
Output invert control (Pin 15)
VS
V
Feedback pin (Pin 8)
VZ
V
CDELAY (Pin 16)
VZ
V
External mod in (Pin 4)
VS
V
Feed-forward (Pin 1)
VS
V
Demag/overvoltage in (Pin 18)
VZ
V
Current sense (Pin 14)
VS
V
80Low supply sense and hysteresis
(Pins 12, 13)
VS
V
Output transistor
output current
FF
TJ
Operating junction temperature
TSTG
Storage temperature range
TSOLD
Lead soldering temperature (10sec)
135
°C
-65 to +150
°C
300
°C
NOTES:
1. Ground Pin 20 must always be the most negative pin.
2. For power dissipation, see the application section which follows.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
RATING
UNIT
Supply
TA
TJ
voltage-fed
10 to 16
V
current-fed
15
mA
NE grade
0 to +70
°C
SE grade
-55 to +125
°C
NE grade
0 to +85
°C
SE grade
-55 to +135
°C
Ambient temperature range
Junction temperature range
DC AND AC ELECTRICAL CHARACTERISTICS
VCC = 12V, specifications apply over temperature, unless otherwise specified.
SYMBOL
PARAMETER
TEST
PINS
TEST CONDITIONS
SE5562
NE5562
Min
Typ
Max
Min
Typ
Max
UNIT
Internal reference
VREF
Reference voltage
Internal
TA=25°C
3.76
3.80
3.84
3.76
3.80
3.84
VREF
Reference voltage
Internal
Over temp.
3.72
3.8
3.90
3.725
3.8
3.870
Temperature stability
Internal
30
30
ppm/°C
Long-term stability
Internal
0.5
0.5
µV/1000
hrs
1994 Aug 31
3
V
V
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
VCC = 12V, specifications apply over temperature, unless otherwise specified.
SYMBOL
PARAMETER
TEST
PINS
TEST CONDITIONS
SE5562
NE5562
UNIT
Min
Typ
Max
Min
Typ
Max
7.60
7.75
7.35
7.6
7.75
V
7.80
7.20
7.78
V
Reference
VZ
Zener voltage
9
IL=7mA,
TA=25°C
7.35
VZ
Zener voltage
9
IL=7mA,
Over temp.
7.25
∆VZ/ ∆T
Temperature stability
9
IL<1mA
Comparator threshold
voltage
Internal
TA=25°C
8.30
8.45
8.75
8.30
8.45
8.75
V
Comparator threshold
voltage
Internal
Over temp.
8.00
8.45
8.90
8.00
8.45
8.90
V
Hysteresis
Internal
25
50
8.00
25
50
800
mV
60
80
60
80
Hz
50
50
ppm/°C
Low supply shutdown
Oscillator
fMIN
Frequency range,
minimum
1, 2,
3, 11
RT=42.7kΩ,
CT=0.47µF
fMAX
Frequency range,
maximum
1, 2,
3, 11
RT=2.87kΩ,
CT=380pF
600
Initial accuracy
1, 2,
3, 11
fO=52kHz,
RT=16kΩ
and CT=0.0015µF,
TA=25°C
48.6
Voltage stability
1, 2, 3,
11, 17
10V<VS<18V
Temperature stability
Sawtooth peak voltage
Sawtooth valley voltage
1994 Aug 31
54
59.4
48.6
-215
1, 2,
3, 11
=25°C1
600
kHz
54
59.4
-215
300
500
kHz
ppm/V
300
500
ppm/°C
2, 3
TA
5.00
5.25
5.40
5.00
5.25
5.40
V
2, 3
Over temp.
4.80
5.25
5.60
4.80
5.25
5.60
V
2, 3
TA=25°C
1.25
1.70
2.00
1.25
1.70
2.00
V
2, 3
Over temp.
1.0
1.7
2.1
1.25
1.7
2.0
V
Sync. in high level
11
2.0
VZ
2.0
VZ
V
Sync. in low level
11
0.0
0.8
0.0
0.8
V
10.0
µA
19
%
22
%
(Sourced),
V11<0.8V
Sync. in bias current
11
0.50
10.0
0.50
Feed-forward ratio,
maximum
1
Feed-forward duty cycle
reduction
1
VFF=2VZ,
TA=25°C
11
13.5
19
11
1
Over temp.
6
13.5
22
8
2
2
13.5
Feed-forward reference
voltage
9
VZ
VS
VZ
VS
V
Feed-forward bias current
1
2.5
50.0
2.5
50.0
µA
4
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
VCC = 12V, specifications apply over temperature, unless otherwise specified.
SYMBOL
PARAMETER
TEST
PINS
TEST CONDITIONS
SE5562
Min
NE5562
Typ
Max
1.0
5.0
Min
Typ
Max
1.0
5.0
UNIT
Error amp
IBIAS
Input bias current
AVOL
DC open-loop gain
8, 10
RL>100kΩ
60
VOH
High output voltage
10
ISOURCE=1mA
5
VOL
Low output voltage
PSRR from VZ and VS
BW
8
10
ISINK=1mA
Internal
fO<300kHz
60
86
µA
dB
5
V
2.0
Small-signal gain bandwidth
product
Feedback resistor range
86
2.0
V
-40
-40
dB
8
8
MHz
240
kΩ
V8=V10=5V
10
10
mA
Output source current
V8=3V,
V10=1V
5
5
mA
Sawtooth feedthrough
AV=100,
0% duty cycle
ISINK
Output sink current
ISOURCE
1
240
1
200
200
mV
PWM comparator and modulator
Minimum duty cycle
19
@VCOMP<,
f=300kHz
0
Maximum duty cycle
19
@VCOMP>,
f=300kHz,
V15=0V
95
41
0
98
95
55
41
%
98
%
55
%
ACC
Duty cycle
10, 19
f=15kHz to
200kHz,
VIN=0.472 VZ
tPD
Propagation delay to
output
2, 19
V15=0
400
IBIAS
Bias current, external
modulator input
4
(Sourced)
0.20
20
0.20
20
µA
IBIAS
Bias current, duty cycle
control
5
(Sourced)
0.20
20
0.20
20
µA
Soft-start trip voltage
5
.910
0.955
0.990
0.922
0.955
0.988
V
Output enabled
6
0
0.80
0
0.80
V
Output disabled
6
2
VZ
2
VZ
V
IBIAS
Bias current
6
10
µA
VIN
Maximum input voltage
49
49
400
ns
Remote on/off (shutdown)
Delay to output(s)
1
6
10
VZ
6, 19
1
VZ
400
V
400
ns
Current limit comparator(s)
Shutdown, OC2
14
.593
0.645
.697
0.593
0.645
0.697
Minimum duty cycle, OC1
14
.486
0.528
.570
0.486
0.528
0.570
V
IBIAS
Bias current
14
0.5
50
0.5
50
µA
OC1
CDELAY charge current
16
-18.2
-13
-6.5
-18.2
-13
-7.8
µA
OC2
CDELAY charge current
16
-770
-550
-250
-770
-550
-330
µA
CDELAY
Discharge current
16
V12=VZ
0.4
1.4
4.0
0.8
1.4
2.0
µA
CDELAY
Shut off trip level
16
TA=25°C
3.75
3.86
3.97
3.75
3.86
3.97
V
1994 Aug 31
(Sourced)
5
V
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
VCC = 12V, specifications apply over temperature, unless otherwise specified.
TEST
PINS
TEST CONDITIONS
Bias current
12
(Sourced)
Threshold voltage
12
Discharge current
12
SYMBOL
PARAMETER
SE5562
NE5562
Min
Typ
Max
1
10
3.69
3.80
3.91
5
10
Max
UNIT
Min
Typ
1
10
3.69
3.80
3.91
5
10
mA
10
mV
Auxiliary comparator with shutdown
IBIAS
CDELAY
Hysteresis
VIN=3V
12, 13
10
µA
V
Demagnetization overvoltage comparator
IBIAS
Bias current
18
Threshold voltage
18
Hysteresis
18
3.62
2
10
3.80
3.91
3.69
10
2
10
3.80
3.91
10
µA
V
mV
Output stage
VOH
VOL
High output voltage
Low output voltage
19
ISOURCE=100mA
19
ISINK=2mA
VS-2.5
VS-1.9
0.16
0.4
VS-2.5
VS-1.9
0.16
0.4
V
19
ISINK=100mA,
TA=25°C
1.4
2.0
1.4
2.0
V
19
ISINK=100mA,
over temp.
2.25
V
2.25
V
ISINK max
19
100
100
ISOURCE max
19
100
100
mA
tR
Rise time
19
CL=2000pF
160
160
ns
tF
Fall time
19
CL=2000pF
80
80
ns
17
10V<VS<16V
(Voltage-fed mode),
VI<VS
9
15
7, 17
II=15mA,
(Current-fed mode)
VS=meter
15.3
16.7
mA
Supply current/voltage
ICC
Supply current
VS
Input voltage
14.2
14.2
9
15
mA
15.3
16.7
V
60
80
Hz
Operating frequency range for all functions but feed-forward working cycle-by-cycle
fMIN
Minimum frequency
All
RT=42.7kΩ,
CT=0.47µF
fMAX
Maximum frequency
All
RT=2.87kΩ,
CT=380pF
60
600
80
1000
600
1000
kHz
103
FREQUENCY (kHz)
TA = 25°C
RT = 2.5kΩ
102
RT = 5kΩ
RT = 10kΩ
RT = 20kΩ
101
100
102
RT = 40kΩ
5 x 102
103 5 x 103
CT (pF)
Figure 3. Frequency vs RT, CT NE/SE5562
1994 Aug 31
6
104
SL00390
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
–30
TA = 25°C
–60
PHASE
–90
–120
–150
40
GAIN (dB)
PHASE (DEG)
0
CLOSED-LOOP GAIN
–180
30
20
10
0
100
1k
10k
100k
1M
10M
FREQUENCY
SL00391
Figure 4. Error Amplifier Closed-Loop Response
100
VCC = 12V
90
TA = 25°C
DUTY CYCLE (%)
80
70
60
50
40
30
20
10
0
1
2
3
4
5
6
7
8
9
10
PWM INPUT VOLTAGE (V)
SL00392
Figure 5. Duty Cycle vs PWM Input Voltage
100
TA = 25°C
90
DUTY CYCLE (%)
80
70
60
50
40
30
20
10
0
5
6
7
8
9
10
11
12
13
FEED-FORWARD VOLTAGE (V)
Figure 6. Duty Cycle vs Feed-forward Voltage
1994 Aug 31
7
14
15
SL00393
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
SUPPLY CURRENT (PIN 17) (mA)
22
20
TA = 25°C
18
16
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
18
20
22
24
SUPPLY VOLTAGE (PIN 17)(V)
SL00394
Figure 7. Current-Feed Characteristics
SUPPLY CURRENT (PIN 17) (mA)
22
20
TA = 25°C
18
16
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (PIN 17)(V)
Figure 8. Voltage-Feed Characteristics
1994 Aug 31
8
20
22
24
SL00395
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
THE NE/SE5562 THEORY OF OPERATION
t
WHERE INTRODUCTION
SW
ON
PERIOD
L
SW
Switched-mode power conversion relies on the principle of pulsed
energy storage in an inductive or capacitive element. Capacitive
switched converters are typically used with low power systems for
which only tens of milliamperes are required. Medium and high
power converters tend to use inductive storage elements as shown
in Figures 9-11 with which a single switch may be moved around to
create step-up (flyback) positive or negative polarity and step-down
(forward or buck) conversion from a fixed-voltage source. The
relationship between input and output voltage in each case is
controlled by the switching on-to-off ratios, which is termed duty
cycle. Duty cycle modulation is the common factor in this basic type
of power control mechanism. By adding a high-gain operational
amplifier, having one input tied to a stable DC reference voltage,
configured in a negative feedback loop to maintain a constant output
voltage as shown in Figure 12, the switched-mode controller
becomes a dynamic voltage regulator. It is this single-switch
topology that is most readily adapted to the NE/SE5562 SMPS
Control IC.
T
+
+
DB
VIN
CO
RL
δ
COM
V
OUT
V IN
–
SL00398
Figure 11. Forward Converter (Single Inductor) Step Down
ISW
REGULATED
OUTPUT
L
+
+
VIN
UNREGULATED
DC
IL
PWM
C
RL
–
–
The ability to switch inductor currents at rates up to 600kHz with
state-of-the-art power FETs makes the design of small, efficient
switching power converters an attainable reality. Protective features
such as programmable slow-start and cycle-by-cycle current limiting
allow safe, maintenance-free power supplies to be mass-produced
at reduced cost to the manufacturer. Integrated technology makes
long-term reliability a predictably achievable goal.
+
VREF
A
R2
–
RF
SW
DO
R1
–
L
VIN
δ
CO
RL
V
OUT
SL00399
V IN
1
Figure 12. The Forward (Buck) Converter (VOUT = VIN(δ))
+
COM
SL00396
i
t
Figure 9. Negative Output Flyback Converter
SWITCH
CURRENT
L
E
L
MAGNETIZATION
CURRENT
LOAD CURRENT
DO
+
+
SW
VIN
δ
COM
CO
RL
V
OUT
DIODE
CURRENT
V IN
1
TOTAL
INDUCTOR
CURRENT
–
SL00400
SL00397
Figure 10. Positive Output Flyback Converter
1994 Aug 31
AVERAGE
INDUCTOR
CURRENT
Figure 13. PWM Switching Waveforms
9
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
FEEDFORWARD
EXT.
SYNC
1
11
+
ACTIVE LOW
0.8V
+
IO
VZ
+7.50V
(5.25V)
VH
R2
S
28k
3
2
–
+
1
TIME BASE
SIGNAL
FF
(1.70V)
R3
3k
CT
–
R
+
TO DELAY
CIRCUIT
CURRENT
STEERING
SAWTOOTH
GENERATOR
DISCH.
+3.80V
VOLTAGE
FEEDBACK 8
+
–
–
–
–
ERROR
AMP
10
PWM
COMPARATOR
OUTPUT TO
LATCH RESET
SL00401
Figure 14.
THE NE/SE5562 THEORY OPERATION
THE PULSE WIDTH MODULATOR AND ERROR
AMPLIFIER
The Sawtooth Oscillator
The PWM consists of a multi-input voltage comparator (Figure 15)
having its positive input tied to the sawtooth ramp voltage and the
various negative inputs referenced to ORed control signal nodes.
The primary control signal is the error amplifier output voltage node
which sets the active duty cycle termination point of the PWM output
waveform. As the error amplifier input signal derived from the power
supply load voltage varies, for instance in a negative direction, the
amplifier output moves upward, raising the PWM comparator toward
longer duty cycles at the output on Pin 19. The start-up sequence
begins with zero voltage at the input to the error amplifier. Since this
could signal an open feedback loop, the loop fault comparator on
Pin 8 clamps the PWM duty cycle until the feedback voltage
exceeds 0.955V. A second comparator monitors the duty cycle
control, Pin 5, with the same threshold level, inhibiting the output via
the start-stop latch (Figure 16).
The sawtooth oscillator consists of a gated charge-discharge
capacitor circuit with threshold comparators setting the peak and
valley voltages of the ramp. The resistor divider R1-3 is supplied
with a source voltage derived from either VZ (7.50V) minus two
diode drops, or, when feed-forward is in control, a voltage greater
than VZ and proportional to the main supply voltage. The nominal
upper threshold voltage is 5.25V and the lower threshold 1.70V.
These then determine the sawtooth peak and valley voltages,
respectively.
Operation
Beginning with the charge cycle, ramp voltage builds up on the
timing capacitor due to a constant current supplied to the node at
Pin 2. When capacitor voltage reaches the upper threshold,
comparator A switches, setting the latching flip-flop. The output of
the latch goes high, generating a clock pulse. The discharge
transistor is simultaneously turned on, reducing charge on the timing
capacitor to the point at which the lower threshold voltage, 1.70V, is
reached. The lower comparator is then activated, resetting the latch
and terminating the clock pulse. Note that the discharge transistor is
referenced to the same return diodes as the threshold resistor
divider and the discharge current is made to track with the charge
current. This charge and discharge tracking results in a true
sawtooth waveform even at extended frequencies. Figure 17 shows
a family of curves which explains the relationship between RT, CT,
and the frequency of the sawtooth generator. The data sheet shows
the initial accuracy of the oscillator at 60Hz and 600kHz.
1994 Aug 31
The charging of the slow-start capacitor provides a controlled
ramp-up of the output duty cycle and a resultant gradual increase in
energy fed to the output magnetics.
The dynamic response of the PWM comparator is shown in the
simulated waveform drawing of Figure 17. The error amplifier output
voltage is depicted as sloping positive (increasing) with time as
referenced to the sawtooth waveform. This causes the duty cycle to
increase with time. This is an indication of an increasing load on the
power supply as output voltage is decreasing. The Pin 5 (δMAX)
control voltage is also superimposed midway on the sawtooth,
indicating the limits of duty cycle increase as the output waveform
no longer increases in duty cycle after the δMAX threshold is
crossed. A hypothetical overcurrent pulse (Pin 14) is shown to
illustrate cycle termination immediately at the output (Pin 19).
10
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
+VZ
35µA
35µA
35µA
VH
SAWTOOTH
+
SAWTOOTH
UPPER
THRESHOLD
9k
4
10
(–)
(–)
(–)
ERROR
AMP
OUT
MODULATOR
IN
5
(–)
DELTA
MAX
CONTROL
PWM SIGNAL
TO OUTPUT
NOR GATE
2.5k
100µA
SL00402
Figure 15. PWM Comparator
DELAYED CLOCK
VREF
+3.80V
S
+
+
–
8
PWM
NOR
R OUTPUT
LATCH
δ
TO OUTPUT
STAGE
–
–
10
5
DUTY
CYCLE
CONTROL
SL00403
Figure 16. The Duty Cycle Control Circuit, Pulse Width Modulator, and Error Amplifier, Reference, and Output Latch
1994 Aug 31
11
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
SAWTOOTH
WAVEFORM
PIN 5
δ MAX LEVEL
PWM COMPARATOR
(INTERNAL)
FLYBACK PULSE
(INTERNAL)
+0.528V
PIN 14
CURRENT
SENSE INPUT
(OUTPUT)
PIN 19
SL00404
Figure 17. Duty Cycle vs Feedback Error and Overcurrent Sense
95%. The amplifier can sink 10mA and source 5mA. The nominal
DC output for 50% duty cycle is 3.55V. Feedback control resistor
value may range from 1kΩ to 240kΩ without overload or instability.
However, low closed-loop gains must be compensated by lag lead
network techniques for optimum stability. Loop compensation
networks may intersect the open-loop gain curve with a slope 2
closure and must then be compensated to maintain overall phase
and gain margin (Figure 18).
The error amplifier’s non-inverting input is tied to a bandgap
reference of 3.80V, accurate to ±2% at 25°C. The temperature
stability of the voltage reference is 30ppm/°C.
The error amplifier is designed for an open-loop gain of 86dB having
a small-signal unity gain bandwidth of 3MHz. Closed-loop gain is
stable to 10dB, as shown in Figure 19. The DC output excursion of
the amplifier is capable of controlling the full PWM range of 0 to
+VZ (7.50V)
VZ
6k
2.5k
VZ
ERROR AMP
OUT
10
3.80
VREF
30
N BIAS
7pF
FEEDBACK
SENSE
8
6k
6k
SL00405
Figure 18. Error Amplifier
1994 Aug 31
12
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
EST. –3dB
FREQUENCY
PHASE DELAY
160° 143°
130°
98°
+VREF 3.75V
80
(dB)
70
A
OL
60
50
OFFSET
ADJUST
40
5k
(8)
30
A
CL ≈
NE5562
ERROR AMPLIFIER
PHASE/AMPLITUDE
RESPONSE
95°
+
360
20
–
10M
(10)
92°
SLOPE
= (–)1
10
50
0
NE/SE5562
SLOPE
= (–)2
fP1
1
10
100
83°
80°
70°
32°
1000
10000
100000
fP2
1000000
FREQUENCY (Hz)
SL00406
Figure 19. Error Amp Response
(7.50V) increases the charge rate on CT, causing the duty cycle to
be terminated earlier for each cycle that input voltage is increased.
The threshold voltages at the sawtooth limit comparator reference
inputs are changed with Pin 1 also in order to offset any change in
oscillator frequency.
FEED-FORWARD COMPENSATION (PIN 1)
To provide a means of automatically improving line-to-load voltage
regulation, a technique called feed-forward regulation is made a part
of the NE/SE5562 active mechanism. Referring back to the diagram
for the sawtooth oscillator, note that Pin 1 is capable of changing the
internal supply voltage to the charging circuit for the timing capacitor,
Ct.
With a nominal duty cycle of 30%, for instance, increasing Pin 1
voltage by 1V from 10.3 to 11.3 will reduce the output duty cycle by
approximately 5%. Thus, a primary voltage change has caused a
decrease in volt-seconds (duty cycle X primary volts) of 5/30 or 16%
(Figure 6). The result is a small over-compensation in the output
energy, but an overall safe margin in transformer flux.
The secondary benefit of using feed-forward is the attenuation of
any low-frequency AC riding on the DC supply before it reaches the
regulated output.
Note that a start delay circuit is added to the Pin 1 divider in order to
prevent internal race conditions during initial power-up. Once the
turn-on transient has decayed, normal operation of the feed-forward
circuit is assured. Figure 21 shows an RC delay placed in a base
clamping circuit to provide reliable starting.
The mechanism which produces inverse duty cycle modulation is
shown in Figure 20. Increasing Pin 1 voltage beyond the value of Vz
LINE VOLTAGE SENSE
2VZ
VZ
+
PWM
COMPARATOR
VTH
VTH
T
δ
δ
SL00407
Figure 20. Feed-Forward
1994 Aug 31
–
T
13
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
SYNCHRONIZATION
The synchronization of the sawtooth oscillator to an external pulse
of negative-going polarity is shown in Figure 22. When the sync
input pulse crosses the 1.5V threshold, negative, the sawtooth
oscillator is prevented from discharging the timing capacitor, causing
the charge voltage on the capacitor to remain high (5.25V) until the
sync pulse again goes above 1.5V, allowing reset. This action
stretches the period of the oscillator and results in a lower frequency
under-synchronization control than the free-running frequency.
VFFWD
2N3906
0.2µF
220k
1
The following relationship holds—
f free*run u f sync
NE/SE5562
f sync +
t0 )
1
A typical recommended starting point in calculating frequency for
synchronous operation is to set the free-run frequency
approximately 10% higher than the sync frequency. Then set the
pulse width, τ, to 10% of t0, the free-run period, with the desired new
frequency determined by the sum as above.
SL00408
Figure 21. Feed-forward Turn-On Delay Circuit
+VCC
T
19
+
NE/SE5562
1.5V
SYNC
11
2
d
T
SL00409
Figure 22. Synchronization Signals
PIN 11
SYNC
SIGNAL
+1.5V
τ
SAWTOOTH
WAVEFORM
TO
SL00410
Figure 23. Sync Signal Relationship to Controlled Sawtooth Waveform
priority level sensing circuit. The lowest level on Pin 4, 5, or 10 gains
control of the duty cycle limit. During normal operation, the δMAX
circuit sends a continuous threshold signal to the PWM comparator,
setting a fixed limit on how much the error amplifier is allowed to
increase the duty cycle in response to load demand. Figure 24
shows the circuit within the NE/SE5562 which actually controls duty
cycle as listed below:
1. Duty cycle ramp-up (slow-start) during power-up. Time constant
controlled by external R, C ramp voltage at Pin 5.
DUTY CYCLE LIMIT (PIN 5)
The forward or buck converter, and even the flyback converters,
may require an automatic duty cycle limit to prevent transformer
saturation or unstable behavior. A special input provides access to
the PWM comparator for this purpose. As discussed previously in
regard to the error amplifier, increasing load demand may drive the
system current beyond safe limits. A simple solution is the
placement of a duty cycle limit within the system dynamic response
before this can occur. Figure 15 shows the PWM comparator with its
multiple input ports. All are inverting in polarity and provide a lowest
1994 Aug 31
14
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
2. Slow-start if remote ON/OFF is actuated, if OC2 threshold trips,
demagnetization/overvoltage is sensed, or low supply voltage to
the internal regulator is sensed (VS≤8.45V).
R2 = 10kΩ, find R1
R2
+ 0.48
R1 ) R2
3. Note that Pin 8 is monitored by the loop fault comparator. When
the regulated supply feedback drops below this threshold level
(0.955V), the duty cycle is clamped by two diodes in series with
a 2kΩ load across Pin 5 to ground. This implies a minimum duty
cycle condition as long as the low output level remains.
∴ R2 = 0.48 (R1 + R2)
0.48R1 = R2 – 0.48R2
N R1 +
Referring to the graph in Figure 25, the designer may choose a
divider ratio which, when referenced to VZ, 7.5V, provides an easy
duty cycle limit control. For example, a 50% limit results in a ratio of
0.48. Setting R2 at a nominal value between 10 and 20kΩ and
solving for R1, the proper limit is obtained.
+
R 2(1 * 0.48)
0.48
10k
(0.52)
0.48
= 10.8kΩ
Example:
A duty cycle limit of 50% is required for a forward converter.
DELTA
MAX TO
PWM COMP
SLOW
START
CAP
R1
R2
CSS
VZ
5
0.9V
VZ
ERROR
AMP IN
36µA
8
N BIAS
1.5V
0.9V
9k
0.955V
SLOW
START
COMP
50
LOOP
FAULT
COMP
SLOW
START
COMP
OUT
2k
‘A’
FROM
START/STOP
LATCH
+
STOP
SL00411
Figure 24. Duty Cycle Limit Control
1994 Aug 31
15
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
90
MAXIMUM DUTY CYCLE %
80
70
60
V Z + 7.50V
50
DUTY
CYCLE
CONTROL
40
30
20
R2
R1 )
10
R2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
SL00412
Figure 25. Maximum Duty Cycle
TO
OUTPUT
NOR
DEMAG/OV
SENSE
REMOTE
ON/OFF
TO
OUTPUT
NOR
VZ
OC2
SENSE
LOW SUPPLY
SENSE
R73
10k
Q262
R79
10k
Q264
R74
10k
R75
18k
R76
15k
R77
10k
Q276
Q277
Q269
Q261
Q282
Q284
Q279
Q283
Q266
Q260
OC ACCUM
1.5V
R78
10k
Q265
Q270 Q271 Q272 Q273 Q274
Q278
Q275
Q267
Q263
Q280
Q281
Q268
Q283B
SHUTDOWN LATCH
CSS
DISCHARGE
SLOW-START
COMPARATOR
+ RESET
Q283A
START STOP LATCH
BULK
SENSE
SIGNAL
GND
+
RESET 0V
20
SL00413
Figure 26. Start-Stop/Shutdown Latches
1994 Aug 31
16
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
duty cycle. The equivalent circuit at this instant in the start-up cycle
which exists at Pin 5 is shown in Figure 28.
THE START-STOP CONTROL SEQUENCE
The start-up circuit involves a sequential set of conditions which
progresses as follows: power-up after OFF condition or remote ON
after OFF. Initially, 0V exist on the supply output, causing zero
feedback volts on Pin 8. The slow-start capacitor is discharged,
forcing Pin 5 to 0V, having been clamped by the internal discharge
transistor. Internal supply regulator input exceeds 8.45V, releasing
low voltage shutdown condition with Pin 5 below 0.955V. The
slow-start comparator output goes high, resetting the start/stop
latch, sending a low output signal to the output stage power NOR
gate. The PWM signal is then enabled to feed the output drive
circuits, starting energy flow through the magnetics. However,
instantaneously the power supply output is still below 0.955V and
the loop fault comparator forces the PWM to remain at a minimum
The actual minimum duty cycle is determined by the parallel source
resistance of R1 and R2 combined with the shunt loading internal to
Pin 5. High values of divider resistance, 20-30kΩ, will supply less
shunt current to Pin 5 and create a lower modulator duty cycle, while
lower values of R1 and R2 (5-10kΩ) will generate a higher modulator
voltage and a greater resultant minimum duty cycle.
As the power conversion circuits become active and Pin 8 feedback
voltage increases above 0.955V, the duty cycle network is
unclamped; duty cycle increases, controlled by the RC time constant
R1||R2.CSS, and as output voltage brings the feedback voltage up to
equal the reference voltage, 3.80V, the error amplifier takes control
and the supply is in regulation.
+7.50V
DEMAG
0V
DISCHARGE
OC2
R1
5
S
CSS
R2
START/
STOP Q
LATCH
–
R
0.955V +
SLOW-START
COMPARATOR
SL00414
Figure 27. Slow-Start Comparator
7.50V
+
– PWM
– COMP
R1
VMOD
5
CSS
R2
MINIMUM
DUTY CYCLE
–
ON
0.2V
5
FEEDBACK
VOLTAGE
SENSE
LOOP FAULT
COMPARATOR
1.4V
2k
SL00415
Figure 28. Loop Fault Comparator and Minimum Duty Cycle Clamp
c. Remote ON/OFF voltage at Pin 6 greater than 2V.
The stop or shutdown sequence is initiated by any of the following
conditions:
d. Sustained OC2 causing CDLY to charge above 3.80V (current
sense on Pin 14 continuously above 0.645V peak).
a. Supply voltage (bulk) sense below 3.80V at Pin 12.
b. Pin 17 below 8.45V or Pin 7 current below level (less than
9mA).
1994 Aug 31
17
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
If the overcurrent sense feature is not used, it is recommended that
Pin 14 be tied to ground.
DUAL-LEVEL OVERCURRENT COMPARATORS
The overcurrent sensing circuit (Figure 29) consists of a single PNP
input buffer with emitter-follower tied to VZ, 7.50V, feeding into the
base of an NPN split-emitter transistor. This forms the input node to
a set of dual-level voltage comparators with references of 0.528 and
0.645V, respectively. Current sources for the comparator are fixed
biased NPNs.
When used for sensing current-derived voltage impulses from the
primary driver, a high-speed, low-impedance transient filter network
is advised. An example is shown in Figure 30. Keep CF close to the
NE/SE5562.
The typical transition time delay for an overcurrent fault is 300ns.
Bias current at the input averages 500nA.
VZ = 7.50V
135µA
135µA
1.5V
135µA
3k
OC2
CURRENT
14 SENSE
INPUT
REFERENCE
0.645V
100µA
135µA
1.5V
3k
OC1
0.528V
0.645V
REFERENCE
0.528V
100µA
SL00416
Figure 29. NE/SE5562 Overcurrent Comparator
THEORY—OC1 AND OC2
Overcurrent Logic and Delay Capacitor Operations
The circuit takes a voltage input from Pin 14 and compares the level
to a dual reference comparator with trips at 0.53 and 0.65V. The
lower trip point actuates cycle-by-cycle shutdown of the output stage
with an intrinsic delay of 400ns. The second level actuates the
slow-start function. In addition, there exists a separate
housekeeping circuit whose function is to terminate operation of the
output stage if its threshold is exceeded. This involves a time delay
circuit based on two separate switchable current sources, OC1 and
OC2. The time delay capacitor allows the user to program shutdown
of the system after a predetermined number of overcurrent cycles
have occurred within the period set by the ramp-up of the delay
capacitor. Once shutdown has occurred in this manner, external
reset is required to restart the system. Referring to the logic block
Figure 31, which controls the gating of the two charge pumps into
the delay capacitor at Pin 16, the complete signal flow may be
traced. Logic signals from the overcurrent 1 and 2 comparators are
gated by the clock and delayed clock signals generated by the
+VCC
NE/SE5562
500-1000Ω
10% CARBON
CF
IMAG
RSH
SL00417
Figure 30. Transient Suppression
1994 Aug 31
18
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
frame. Consecutive overcurrent pulses of either OC1 or OC2
magnitude will activate the selected charge pump for the total
duration that such overcurrent occurs. The charging cycle will
continue until the delay capacitor reaches the 3.86V trip level.
sawtooth oscillator. The complete sequence for an overcurrent fault
may be understood by referring to Figure 32 for OC2. Here it is
shown that an OC2 signal exists indicating that the 0.65V threshold
has been exceeded by a signal at Pin 14.
Note that an overcurrent pulse within a particular clock frame turns
on the respective OC2 charge ramp during the entire next clock
C
Q
A
C
A
C
A
C
A
B
OC2
LATCH
OC2 DELAYED
OC2
A
C
B
A
B
C
A
C
Q
B
B
C
B
CLOCK
A
A
C
C
C
A
C
A
C
A
Q
A
C
A
A
C
A
C
B
B
C A
A
B
OC1
LATCH
A
C
Q
C
B
DELAYED
CLOCK
OUT
A
OC1 DLEAYED
OC1
OC2 IN
B
B
A
B
C
A
B
OC1 IN
SL00418
Figure 31. Overcurrent Logic
SAWTOOTH
CLOCK
CLOCK
DELAY
CLOCK
LET OC2 GO UP AT ANY TIME BETWEEN DELAY CLOCK RISES AND CLOCK RISES
OC2
QA
QB
R
S
QPUMP
SL00419
Figure 32. Fault Cycle
1994 Aug 31
19
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
3.86V
0.1µF
0.5µF
1µF
CDELAY
0.00V
100
200
300
OC1 DELAY TIME (MILLISECONDS)
3.66V
SL00421
1µF
Figure 34. OC1 Ramp and Shutdown Delay
5µF
mode), on the first such pulse. OC2 delays are based on an
interrupted charging cycle with total cycle time determined by the
external slow-start delay capacitor duty cycle maximum
divider—time constant.
10µF
CDELAY
For a continuous OC1 overcurrent:
0.00V
10
20
30
40
50
60 70
OC2 DELAY TIME (MILLISECONDS)
(neglecting recycle dfelay)
C DLY +
80
SL00420
(13X10 *6)(Delay time * sec)
(1)
3.86V
For a continuous OC2 overcurrent:
Figure 33. Overcurrent Shutdown Function
C DLY +
(550X10 *6)(Delay cycles x 1ń f SW)
3.86V
(2)
Some downward adjustment of the OC2 capacitor value may be
necessary to compensate for the 1-2µA of discharge current at Pin
16 during the delay cycles.
CALCULATING THE DELAY CAPACITOR
Actual delay time for a given capacitor value at Pin 16 may be
estimated using the graphs in Figure 33 for OC1 and OC2. By first
determining the allowable overcurrent time product for a particular
power converter, a capacitor delay value may be calculated.
Example: A maximum of 100 OC2 current fault cycles is allowed.
fSW =400kHz, find CDLY
(550X10 *6)(100 x 1ń 4 x 105)
C DLY +
3.86V
Note that the OC1 charge pump is typically 13µA while OC2 pumps
550µA into the capacitor. If the exact value is to be calculated for a
particular delay requirement, use the following procedure:
=0.036µF
1. Determine the level of overcurrent—OC1 or OC2.
Example: OC2/CDLY
2. Find the maximum delay time which the supply may safely sustain for this continuous overcurrent condition. Note that OC1 may
be activated on every cycle if OC2 is not reached, causing continuous charging of C-Delay. However, OC2 overcurrent detection causes the supply to go into slow-start shutdown (hiccup
1994 Aug 31
Find number of OC1 cycles before shutdown with 0.036µF CDLY.
20
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
Delay Time (3.6 X 10 8)(3.86V)
13 x 10 6A
NE/SE5562
adjusted near midway, the line voltage will have to exceed VNOMINAL
before the supply will restart. The hysteresis control may then be
calibrated for the desired over-excursion before restart. This
prevents unstable circuit chatter.
=10.7ms
10.7 X 10 3
2.5 x 10 6
=4280
The reset switch provides a means for resetting the shutdown latch
after overcurrent faults have charged CDLY to its trip threshold. This
also provides a discharge path for the delay capacitor. Figure 36
shows internal circuit.
Total cycles shutdown Figure 35 shows an actual OC1 charging cycle for continuous fault
current sensed at Pin 14 and a DLY = 1µF.
VBULK
+VS
BULK-SENSE AUXILIARY COMPARATOR WITH
SHUTDOWN
R1
This circuit is intended to act as an automatic low-line detection
mechanism. As shown in Figure 35, a voltage divider is connected
from the main unregulated DC supply to Pin 12. The lower divider
resistor may be a potentiometer of 5-10kΩ resistance with
center-tap connected to Pin 13. The comparator which senses Pin
12 voltage is referenced to 3.80V and Pin 12 divider voltage must be
greater than this voltage by a sufficient margin to operate within the
prescribed low-line limits. For instance, if a line voltage drop of 25%
is considered the shutdown threshold, then V12 should be calculated
for a nominal operating voltage as shown in Figure 35.
NE/SE5562
12
13
R2 HYSTERESIS
ADJUST
SL00422
Figure 35. Bulk-Sense Comparator Divider
When the line voltage drops more than 25%, the output stage is
disabled. With the hysteresis connected as shown and the pot
1.5V
++
VBULK
18k
BULK
SENSE OUT
RA
VZ
16
RESET
CDELAY
25k
12
3.80V
BULK
SENSE IN
36µA
N BIAS
26k
BULK
SENSE
COMP
BULK
13 SENSE
HYSTERESIS
RB
POTENTIOMETER
26k
SL00423
Figure 36. Bulk-Sense Comparator
power MOS FET gate. This feature protects the output stage from
inadvertent catastrophic overload.
THE OUTPUT DRIVE STAGE
The output stage contains the power NOR inhibit gate, invert logic
function, and source-sink drivers. The driver stage is capable of
sourcing and sinking 100mA at frequencies up to 600kHz. The
output transistors are Schottky clamped to prevent saturation and
the resultant switching delay due to stored charge. A 2.5Ω current
sense resistor in the emitter of Q419 serves to drive active clamp
Q427 when the output sources more than 200mA. This places a limit
on the peak current available during instantaneous charging of a
1994 Aug 31
When sinking current, the output is clamped to a maximum of 1.4V.
Output swing for positive output is typically VS-1.9V at 100mA
sourcing. Rise time for a 2000pF load at Pin 19 is typically 160ns
with a fall time of 80ns.
The power NOR gate provides a fast response inhibit function to
shutdown the output in the event of a number of different fault
21
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
means of designing with P-channel power MOS FETs without adding
external inverters. The invert logic is controlled by a simple logic
signal at Pin 15. Grounding will cause the output to be a normal
positive output and a high level gives inverted output.
conditions. All inputs are internal to the device and do not appear
directly on the external pins as is shown on Figure 37.
The additional flexibility of an invert control allows the polarity at the
output during duty cycle to be reversed. This provides a simple
17
R31
10k
Q126
R32
3k
Q125
R34
R30
R37
5k
15
10k
Q128 R35
Q131
Q129
3k
R33
5k
+V5
R38
1k
Q127
Q132
Q155
Q130
Q156
Q133
PWM
DEMAG
0.V
SHUT
DOWN
LATCH
Q154
Q158
OUTPUT
LATCH
START/STOP
LATCH
Q157
R39
300
3.80V
R40
2.5
1.5V
19
OUTPUT
R28
5k
R29
5k
R30
1.25k
Q159
Q144
Q142
Q134
Q135
Q136
VZ
Q160
Q143
Q141
Q137
Q161
Q151
R43
4k Q162
Q145 Q146 Q147
Q138 1.5V
Q153
Q148
Q139
Q165
R41
5k
PBIAS
Q140
Q152
Q149
Q163
Q164
Q165
R42
1k
Q150
INVERT
15
OUTPUT NCR
NORM
SL00424
Figure 37. Output Driver Schematic
THE INTERNAL VOLTAGE REGULATOR
20-Pin glass/ceramic—NE5562F/ SE5562F: θJA 90°C/W
The internal regulator is configured to provide for external supply to
the NE/SE5562 from either a voltage feed or a current feed.1
20-Pin SO: -55 to +85°C/W (board-dependent)
NOTE:
For the current-fed mode, a series-dropping resistor may be used to
power the device from voltages greater than 18V with current supply
of 15 to 25mA. Note that supply current stated in the data sheet is
for the device only without load on the output or VZ. Drive currents
also are pulse-related and thus reflect frequency components onto
the current-feed circuit. These must be filtered out at Pin 7 with
adequately large capacitors in order to prevent motor-boating (see
Figure 38 and Figure 39).
1. See Figures 7 and 8 for internal Regulator Response Curves.
Design Example—An NE5562N is operated at 40°C ambient in the
voltage-fed mode with VS=15V; assume IS=22mA average:
++V
47-100µF
35V
+
Input current to Pin 7 flows through Zeners Z1 and Z2, and shunt
regulator transmitter QR. A differential amplifier with 3.80V reference
provides feedback to regulate VS to 15V.
7
In the voltage-fed mode using Pin 17, the Zeners prevent current
flow through QR for input voltages less than 19V.
Power dissipation of the device must stay within the allowable
package limits. These limits are derived from the thermal
characteristics of the particular package chosen. The NE5562N
plastic package is capable of operating within the temperature range
19
NE/SE5562
(ambient) of 0 to +70°C. This rating applies to the surface-mount
product NE5562D also. Obviously, the power dissipation of the “D”
package is lower than the standard DIP. Thermal resistance for the
various packages are:
20
SL00425
20-Pin plastic—NE5562N/SE5562N: θJA 61°C/W
1994 Aug 31
Figure 38. Current-Feed
22
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
VOLTAGE
SOURCE
VS
17
VI
7
NE/SE5562
VS
CURRENT
SOURCE
790
FROM BIASING
NETWORK
30k
10k
QR
20k
REGULATOR
3.80V
SL00426
Figure 39. Internal Voltage Regulator
∴ PD = (22×10-3) (15)
=330mW
Junction temperatures will be 20.1°C above average ambient
temperatures which is 40°C
TJ=40°C 20.1°C 60.1°C
Solving for the temperature rise from ambient to the IC functions:
Temperature rise = 61°C/W×0.33W
The allowable maximum junction temperature is 150°C 125°C is
more conservative. The conditions of this example are safe.
= 20.1°C
+25V
+12–15V
LO
10k
12
VZ
17
CO
10k
(0.472) VZ
CL
15
4
19
5
IRF530
NE5562
3
2
1µF
1k
14
VREF
100pF
8
ERROR
AMP
RSH
6
20
10k
‘A’
10
VARIABLE
SUPPLY
0-5V
10k
NOTES:
1. Supply will become active as point ‘A’ reaches the level of VREF, 3.80V.
2. Monitor Pin 19 and Pin 2 on dual-trace scope with voltmeter connected to supply output.
Figure 40. Open-Loop Test Setup
1994 Aug 31
23
SL00427
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
D3
LO
+
+
P1
P2
CP
n
S1
D2
CO
VO
n
–
VIN
Q1
–
NOTE:
The P1 clamp winding prevents collector voltage from exceeding 2X VIN during off time.
SL00428
Figure 41. Forward Converter
+
Flyback Converter Design
Flyback Converter
n
Advantages:
1
–
• Simple circuit. Only one inductive component even with line isolation.
m
• Economic. Low component count, low cost.
• Work over large input voltage variations.
• Can accommodate multiple outputs.
To Prevent Core Saturation Due to
Flux Staircasing
Disadvantages:
m
1 * m ) nif m = n δmax < .5
max t
• Large output ripple current due to discontinuous energy transfer.
• Large output capacitor; has to supply part of the load current.
• Low leakage inductance required to prevent high voltage spikes at
Demagnetization of Core
the switching transistors.
V CEmax + V imax
m ) n
X
m
• Relatively large core volume for the output power. Core driven in
(V)
one direction only.
Design Parameters for Flyback Inductor
Maximum Voltage Across Transistor
SL00429
Input
• Minimum input voltage
• Maximum input voltage
Figure 42. Forward Converter Design Formulas
D1
Output
+
+
• Output voltage or voltages
• Output current or currents
• Output load
CP
CO
VO
VI
–
Q1
–
SL00430
Figure 43. Isolated Secondary
1994 Aug 31
24
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
Frequency of Operation
Estimate of Overall Efficiency. (η)
+16V
AUXILIARY
BOOTSTRAP
SUPPLY
(SEE FIGURE 43)
+V=48V
0.47µF
F. FWD
SENSE
+VS = 12V
3.9
10
0.01µF
2N3906
40k
220k
BYV19-35
BYV26C
10k
C3
0.01µF
0.22µF
1
13k
570
pF
4
3.26V
5
13
D
R
I
V
E
R
L
A
T
C
H
PWM
10k
CSS
L0
+5V
3.9
D3
n
LOW
SUPPLY
DETECTOR
CLOCK
DELAY
2
5.1k
D2
n T1
0.01µF
COM.
1
3
(PIN 9)
VZ
7.50V
RESET
[O.C.]
12
17
+VOUT
D1
HYSTERESIS
ADJUST
4.7nF
BUZ41A
19
4.7
BYV26C
18
Q1
6
10
START/
STOP
15
INVERT
LA645V
OFF
0V
ON
REMOTE
SHUT DOWN
1.3k
+5
VOUT
SENSE
ICC
3.80V
+5V
SHUT
DOWN
PGM
+
8
CL
1
IN914
T2
14
100pF
ERROR
AMP
–
13µA
550µA
C@ T
100:1
CL
2
OC1
OC2
Q1
10
20
16
PIN
14
0.00µF
CDELAY
1k
1.6k
PIN
14
ALTERNATE
CIRCUIT
I MAX +
RSH
0.24
0.53
R
SH
SL00431
Figure 44. Forward Converter, 100W – 5V
1994 Aug 31
25
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
+48V
+17V
100
15V
P3
n
D40K2
+VO
+5V
P2
33k
n
n/2
7
1
P1
NE/SE5562
n
+3.80V
220k
19
6.8k
+
0.22µF
–
8
RF
10
20
SL00432
Figure 45. Shunt-Regulated Output With Bootstrap Supply
1994 Aug 31
26
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
+
S
CURRENT PATH
WITH SWITCH
CLOSED
VI
NE/SE5562
–
CURRENT PATH
WITH SWITCH
OPEN
VO
–
+
+
S
CURRENT PATH
WITH SWITCH
CLOSED
VI
CURRENT PATH
WITH SWITCH
OPEN
–
+
+
+
VI
–
VO
Negative Output
VO
Positive Output
–
Development of Practical Flyback Converter Circuit
ID1
T1
IC
VI
TR1 ON OFF
IO
D1
L1
a iL
iL
IL
+
CO
VO
N1
nVO
VI
nVO
VI
IL
VCE
TR1
VCE
c iL
O δ T
Flyback Converter and Current and Voltage Waveforms
Figure 46.
1994 Aug 31
VCE
iL VCE
b iL
NOTES:
a. Unlimited choke current
b. Interrupted choke current
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉ
27
T
O δ T
VI
T
SL00433
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
48V +VS
+5V
T
COM
33k
+12V
2N3906
0.22µF
V0’ SENSE
+5V
6.8k
RT
5.1k
20
2
19
3
4
18
17
16
6
7
8
9
10
3.8V
3.5V
1
5
R1
R2
COM
0.1µF
CERAMIC
NE5562
570pF
CT
+12
FEEDFORWARD
220k
RF
–12
BUZ41A
4.7
CDELAY
1k
15
O.C.
14
13
HYST.
12
11
RSH
100pF
CSS
LOW
SUPPLY
SENSE
EXT
SYNC
+5
+VS
RESET
0V–
NOTE:
400kHz operation with feed-forward line regulation and cycle-by-cycle current timing.
SL00434
Figure 47. NE5562 Flyback Converter
++V
(17)
–VOUT
(10)
(19)
RF
+
(8)
–
VZ (9)
+7.50V
ERROR
AMP
(20)
100
100
2N3906
RS
+3.80V
IS’
RI
IS
SL00435
Figure 48. Negative Output Regulator Using Current Mirror
1994 Aug 31
28
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
+48V
(+)
+15V
SLAVED
OUTPUTS
17
+15V
(–)
NE/SE5562
–15V
+
+
4
NE5018
D/A
1–5V
PWM
–
+5V
–12V
NE5034
A/D
15
5k
+
PROGRAMMED
SUPPLY
VOLTAGE
µP
SL00436
Figure 49. Microprocessor Controlled SMPS
3. H. Dean Venable, Stability Analysis Made Simple, Venable
Industries, Inc., 1981.
REFERENCES
1. R.D. Middlebrook and Slobadan Cuk, Advances in Switched
Mode Power Conversion, Volumes I and II, TESLA Co., Pasadena, CA, 1983.
4. J. Jongsma and L.P.M. Bracke, High Frequency Ferrite Power
Transformer and Choke Design, N. V. Philips ELCOMA Publications, Eindhoven, the Netherlands, September 1982.
2. Rudolf P. Stevens and Gordon E. Bloom, Modern DC to DC
Switchmode Power Convertor Circuits, Van Nostrand Reinhold/
Computer Science and Engineering Series, 1985.
1994 Aug 31
5. Edwin S. Oxner, Power FETs and Their Applications, PrenticeHall, 1982.
29