SST SST29EE512-90-4C-EH

512 Kbit (64K x8) Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
SST29EE512 / SST29LE512 / SST29VE512512Kb Page-Mode flash memories
Data Sheet
FEATURES:
• Single Voltage Read and Write Operations
– 5.0V-only for SST29EE512
– 3.0-3.6V for SST29LE512
– 2.7-3.6V for SST29VE512
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and 10 mA
(typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
• Fast Page-Write Operation
– 128 Bytes per Page, 512 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 2.5 sec (typical)
– Effective Byte-Write Cycle Time: 39 µs (typical)
• Fast Read Access Time
– 5.0V-only operation: 70 and 90 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
• Latched Address and Data
• Automatic Write Timing
– Internal VPP Generation
• End of Write Detection
– Toggle Bit
– Data# Polling
• Hardware and Software Data Protection
• Product Identification can be accessed via
Software Operation
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm, 8mm x 20mm)
– 32-pin PDIP
PRODUCT DESCRIPTION
The SST29EE/LE/VE512 are 64K x8 CMOS, Page-Write
EEPROMs manufactured with SST’s proprietary, high
performance CMOS SuperFlash technology. The splitgate cell design and thick oxide tunneling injector attain
better reliability and manufacturability compared with
alternate approaches. The SST29EE/LE/VE512 write
with a single power supply. Internal Erase/Program is
transparent to the user. The SST29EE/LE/VE512 conform to JEDEC standard pinouts for byte-wide memories.
Featuring high performance Page-Write, the SST29EE/
LE/VE512 provide a typical Byte-Write time of 39 µsec.
The entire memory, i.e., 64 KBytes, can be written pageby-page in as little as 2.5 seconds, when using interface
features such as Toggle Bit or Data# Polling to indicate
the completion of a Write cycle. To protect against inadvertent write, the SST29EE/LE/VE512 have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum
of applications, the SST29EE/LE/VE512 are offered with
a guaranteed Page-Write endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
©2001 Silicon Storage Technology, Inc.
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1
The SST29EE/LE/VE512 are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications, the SST29EE/LE/VE512 significantly improve performance and reliability, while lowering power
consumption. The SST29EE/LE/VE512 improve flexibility while lowering the cost for program, data, and configuration storage applications.
To meet high density, surface mount requirements, the
SST29EE/LE/VE512 are offered in 32-lead PLCC and 32lead TSOP packages. A 600-mil, 32-pin PDIP package is
also available. See Figures 1, 2, and 3 for pinouts.
Device Operation
The SST Page-Mode EEPROM offers in-circuit electrical
write capability. The SST29EE/LE/VE512 do not require
separate Erase and Program operations. The internally
timed Write cycle executes both erase and program transparently to the user. The SST29EE/LE/VE512 have industry standard optional Software Data Protection, which SST
recommends always to be enabled. The SST29EE/LE/
VE512 are compatible with industry standard EEPROM
pinouts and functionality.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
SSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Read
consists of a specific three byte-load sequence that allows
writing to the selected page and will leave the SST29EE/
LE/VE512 protected at the end of the Page-Write. The
page load cycle consists of loading 1 to 128 Bytes of data
into the page buffer. The internal Write cycle consists of the
TBLCO time-out and the write timer operation. During the
Write operation, the only valid reads are Data# Polling and
Toggle Bit.
The Read operations of the SST29EE/LE/VE512 are controlled by CE# and OE#, both have to be low for the system
to obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either CE# or OE# is high.
Refer to the read cycle timing diagram for further details
(Figure 4).
The Page-Write operation allows the loading of up to 128
Bytes of data into the page buffer of the SST29EE/LE/
VE512 before the initiation of the internal Write cycle. During the internal Write cycle, all the data in the page buffer is
written simultaneously into the memory array. Hence, the
Page-Write feature of SST29EE/LE/VE512 allows the
entire memory to be written in as little as 2.5 seconds. During the internal Write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in
the system to set up the write to the next page. In each
Page-Write operation, all the bytes that are loaded into the
page buffer must have the same page address, i.e. A7
through A16. Any byte not loaded with user data will be written to FFH.
Write
The Page-Write to the SST29EE/LE/VE512 should always
use the JEDEC Standard Software Data Protection (SDP)
three-byte command sequence. The SST29EE/LE/VE512
contain the optional JEDEC approved Software Data Protection scheme. SST recommends that SDP always be
enabled, thus, the description of the Write operations will
be given using the SDP enabled format. The three-byte
SDP Enable and SDP Write commands are identical;
therefore, any time a SDP Write command is issued,
Software Data Protection is automatically assured. The
first time the three-byte SDP command is given, the device
becomes SDP enabled. Subsequent issuance of the same
command bypasses the data protection for the page being
written. At the end of the desired Page-Write, the entire
device remains protected. For additional descriptions,
please see the application notes The Proper Use of
JEDEC Standard Software Data Protection and Protecting
Against Unintentional Writes When Using Single Power
Supply Flash Memories.
See Figures 5 and 6 for the Page-Write cycle timing diagrams. If after the completion of the three-byte SDP load
sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byte-load cycle time
(TBLC) of 100 µs, the SST29EE/LE/VE512 will stay in the
page load cycle. Additional bytes are then loaded consecutively. The page load cycle will be terminated if no additional byte is loaded into the page buffer within 200 µs
(TBLCO) from the last byte-load cycle, i.e., no subsequent
WE# or CE# high-to-low transition after the last rising edge
of WE# or CE#. Data in the page buffer can be changed by
a subsequent byte-load cycle. The page load period can
continue indefinitely, as long as the host continues to load
the device within the byte-load cycle time of 100 µs. The
page to be loaded is determined by the page address of
the last byte loaded.
The Write operation consists of three steps. Step 1 is the
three-byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
SST29EE/LE/VE512. Steps 1 and 2 use the same timing
for both operations. Step 3 is an internally controlled write
cycle for writing the data loaded in the page buffer into the
memory array for nonvolatile storage. During both the SDP
three-byte load sequence and the byte-load cycle, the
addresses are latched by the falling edge of either CE# or
WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. The
internal write cycle is initiated by the TBLCO timer after the
rising edge of WE# or CE#, whichever occurs first. The
Write cycle, once initiated, will continue to completion, typically within 5 ms. See Figures 5 and 6 for WE# and CE#
controlled Page-Write cycle timing diagrams and Figures
15 and 17 for flowcharts.
Software Chip-Erase
The SST29EE/LE/VE512 provide a Chip-Erase operation,
which allows the user to simultaneously clear the entire
memory array to the “1” state. This is useful when the entire
device must be quickly erased.
The Software Chip-Erase operation is initiated by using a
specific six-byte load sequence. After the load sequence,
the device enters into an internally timed cycle similar to the
Write cycle. During the Erase operation, the only valid read
is Toggle Bit. See Table 4 for the load sequence, Figure 10
for timing diagram, and Figure 19 for the flowchart.
The Write operation has three functional cycles: the Software Data Protection load sequence, the page load cycle,
and the internal Write cycle. The Software Data Protection
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
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512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Write Operation Status Detection
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
The SST29EE/LE/VE512 provide two software means to
detect the completion of a Write cycle, in order to optimize
the system write cycle time. The software detection
includes two status bits: Data# Polling (DQ7) and Toggle Bit
(DQ6). The end of write detection mode is enabled after the
rising WE# or CE# whichever occurs first, which initiates
the internal Write cycle.
Software Data Protection (SDP)
The SST29EE/LE/VE512 provide the JEDEC approved
optional Software Data Protection scheme for all data alteration operations, i.e., Write and Chip-Erase. With this
scheme, any Write operation requires the inclusion of a
series of three byte-load operations to precede the data
loading operation. The three byte-load sequence is used to
initiate the Write cycle, providing optimal protection from
inadvertent write operations, e.g., during the system powerup or power-down. The SST29EE/LE/VE512 are shipped
with the Software Data Protection disabled.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejection is valid.
The software protection scheme can be enabled by applying a three-byte sequence to the device, during a pageload cycle (Figures 5 and 6). The device will then be automatically set into the data protect mode. Any subsequent
write operation will require the preceding three-byte
sequence. See Table 4 for the specific software command
codes and Figures 5 and 6 for the timing diagrams. To set
the device into the unprotected mode, a six-byte sequence
is required. See Table 4 for the specific codes and Figure 9
for the timing diagram. If a write is attempted while SDP is
enabled the device will be in a non-accessible state for ~
300 µs. SST recommends Software Data Protection
always be enabled. See Figure 17 for flowcharts.
Data# Polling (DQ7)
When the SST29EE/LE/VE512 are in the internal Write
cycle, any attempt to read DQ7 of the last byte loaded during the byte-load cycle will receive the complement of the
true data. Once the Write cycle is completed, DQ7 will
show true data. The device is then ready for the next operation. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart.
The SST29EE/LE/VE512 Software Data Protection is a
global command, protecting (or unprotecting) all pages in
the entire memory array once enabled (or disabled). Therefore using SDP for a single Page-Write will enable SDP for
the entire array. Single pages by themselves cannot be
SDP enabled or disabled, although the page addressed
during the SDP write will be written.
Toggle Bit (DQ6)
During the internal Write cycle, any consecutive attempts to
read DQ6 will produce alternating 0s and 1s, i.e., toggling
between 0 and 1. When the Write cycle is completed, the
toggling will stop. The device is then ready for the next
operation. See Figure 8 for Toggle Bit timing diagram and
Figure 16 for a flowchart. The initial read of the Toggle Bit
will typically be a “1”.
Single power supply reprogrammable nonvolatile memories may be unintentionally altered. SST strongly recommends that Software Data Protection (SDP) always be
enabled. The SST29EE/LE/VE512 should be programmed
using the SDP command sequence. SST recommends the
SDP Disable Command Sequence not be issued to the
device prior to writing.
Data Protection
The SST29EE/LE/VE512 provide both hardware and software features to protect nonvolatile data from inadvertent
writes.
Please refer to the following Application Notes for more
information on using SDP:
Hardware Data Protection
•
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
•
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 2.5V.
©2001 Silicon Storage Technology, Inc.
Protecting Against Unintentional Writes When
Using Single Power Supply Flash Memories
The Proper Use of JEDEC Standard Software
Data Protection
S71060-06-000 6/01
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301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Product Identification
Product Identification Mode Exit
The product identification mode identifies the device as the
SST29EE/LE/VE512 and manufacturer as SST. This mode
is accessed via software. For details, see Table 4, Figure
11 for the software ID entry, and read timing diagram and
Figure 18 for the ID entry command sequence flowchart.
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Software ID Exit (reset) operation, which returns the device to the Read operation. The
Reset operation may also be used to reset the device to the
Read mode after an inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. See Table 4 for software command
codes, Figure 12 for timing waveform, and Figure 18 for a
flowchart.
TABLE 1: PRODUCT IDENTIFICATION
Address
Data
0000H
BFH
SST29EE512
0001H
5DH
SST29LE512
0001H
3DH
SST29VE512
0001H
3DH
Manufacturer’s ID
Device ID
T1.2 301
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X-Decoder
A15 - A0
Address Buffer & Latches
Y-Decoder and Page Latches
CE#
OE#
WE#
Control Logic
I/O Buffers and Data Latches
DQ7 - DQ0
NC
VDD
4
3
2
1
32 31 30
29
NC
NC
A6
A15
5
A12
A7
WE#
301 ILL B1.1
28
A13
A5
7
27
A8
A4
8
26
A9
A3
9
25
A11
A2
10
24
OE#
A1
11
23
A10
A0
12
22
CE#
DQ0
13
21
14 15 16 17 18 19 20
DQ7
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
32-lead PLCC
Top View
DQ6
A14
6
301 ILL F19.1
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
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512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Standard Pinout
Top View
Die Up
301 ILL F01.2
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
32-pin
6
PDIP
7
8 Top View
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
301 ILL F02.2
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
A15-A7
Row Address Inputs
To provide memory addresses. Row addresses define a page for a Write cycle.
A6-A0
Column Address Inputs
Column Addresses are toggled to load page data
DQ7-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD
Power Supply
To provide:
VSS
Ground
NC
No Connection
5.0V supply (±10%) for SST29EE512
3.0V supply (3.0-3.6V) for SST29LE512
2.7V supply (2.7-3.6V) for SST29VE512
Unconnected pins.
T2.1 301
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
5
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
TABLE 3: OPERATION MODES SELECTION
Mode
CE#
OE#
WE#
DQ
Address
Read
VIL
VIL
VIH
DOUT
AIN
Page-Write
VIL
VIH
VIL
DIN
AIN
Standby
VIH
X1
X
High Z
X
X
VIL
X
High Z/ DOUT
X
X
X
VIH
High Z/ DOUT
X
VIL
VIH
VIL
DIN
AIN, See Table 4
Software Mode
VIL
VIH
VIL
Manufacturer’s ID (BFH)
Device ID2
See Table 4
SDP Enable Mode
VIL
VIH
VIL
See Table 4
SDP Disable Mode
VIL
VIH
VIL
See Table 4
Write Inhibit
Software Chip-Erase
Product Identification
T3.4 301
1. X can be VIL or VIH, but no other value.
2. Device ID = 5DH for SST29EE512 and 3DH for SST29LE/VE512
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
Addr1
Data
2nd Bus
Write Cycle
Addr1
Data
3rd Bus
Write Cycle
Addr1
4th Bus
Write Cycle
Data
Addr1
Data
Data
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
Data
Addr1
Data
Software
Data Protect Enable
& Page-Write
5555H
AAH
2AAAH
55H
5555H
A0H
Addr2
Software
Data Protect Disable
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
20H
Software Chip-Erase3 5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
5555H
AAH
2AAAH
55H
5555H
60H
Software ID
Entry4,5
5555H
AAH
2AAAH
55H
5555H
90H
Software ID Exit
5555H
AAH
2AAAH
55H
5555H
F0H
Alternate
Software ID Entry6
5555H
AAH
2AAAH
55H
5555H
80H
T4.2 301
1. Address format A14-A0 (Hex), Address A15 can be VIL or VIH, but no other value.”
2. Page-Write consists of loading up to 128 Bytes (A6-A0)
3. The software Chip-Erase function is not supported by the industrial temperature part.
Please contact SST if you require this function for an industrial temperature part.
4. The device does not remain in Software Product ID Mode if powered down.
5. With A14-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0,
SST29EE512 Device ID = 5DH, is read with A0 = 1
SST29LE/VE512 Device ID = 3DH, is read with A0 = 1
6. Alternate six-byte Software Product ID Command Code
Note: This product supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code
sequence. For new designs, SST recommends that the three-byte command code sequence be used.
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
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301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
FOR
Range
Ambient Temp
Commercial
Industrial
OPERATING RANGE
Commercial
Industrial
OPERATING RANGE
Commercial
Industrial
OF
0°C to +70°C
5.0V±10%
5.0V±10%
SST29LE512
Ambient Temp
VDD
0°C to +70°C
3.0-3.6V
-40°C to +85°C
3.0-3.6V
FOR
Range
VDD
-40°C to +85°C
FOR
Range
AC CONDITIONS
SST29EE512
SST29VE512
Ambient Temp
VDD
0°C to +70°C
2.7-3.6V
-40°C to +85°C
2.7-3.6V
TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns
Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF
See Figures 13 and 14
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
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301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
TABLE 5: DC OPERATING CHARACTERISTICS VDD = 5.0V±10% FOR SST29EE512
Limits
Symbol
Parameter
IDD
Power Supply Current
Min
Max
Units
Test Conditions
Address input=VIL/VIH, at f=1/TRC Min,
VDD=VDD Max
Read
30
mA
CE#=OE#=VIL, WE#=VIH, all I/Os open
Write
50
mA
CE#=WE#=VIL, OE#=VIH, VDD=VDD Max
ISB1
Standby VDD Current
(TTL input)
3
mA
CE#=OE#=WE#=VIH, VDD=VDD Max
ISB2
Standby VDD Current
(CMOS input)
50
µA
CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
10
µA
VOUT=GND to VDD, VDD=VDD Max
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
0.8
2.0
0.4
2.4
V
VDD=VDD Min
V
VDD=VDD Max
V
IOL=2.1 mA, VDD=VDD Min
V
IOH=-400 µA, VDD=VDD Min
T5.1 301
TABLE 6: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST29LE512 AND 2.7-3.0V FOR SST29VE512
Limits
Symbol
Parameter
IDD
Power Supply Current
Min
Max
Units
Test Conditions
Address input=VIL/VIH, at f=1/TRC Min,
VDD=VDD Max
Read
12
mA
CE#=OE#=VIL, WE#=VIH, all I/Os open
Write
15
mA
CE#=WE#=VIL, OE#=VIH, VDD=VDD Max
ISB1
Standby VDD Current
(TTL input)
1
mA
CE#=OE#=WE#=VIH, VDD=VDD Max
ISB2
Standby VDD Current
(CMOS input)
15
µA
CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
10
µA
VOUT=GND to VDD, VDD=VDD Max
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
0.8
2.0
0.4
2.4
V
VDD=VDD Min
V
VDD=VDD Max
V
IOL=100 µA, VDD=VDD Min
V
IOH=-100 µA, VDD=VDD Min
T6.2 301
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
8
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
µs
Power-up to Write Operation
5
ms
TPU-WRITE
1
T7.0 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: CAPACITANCE
(Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
CI/O1
I/O Pin Capacitance
VI/O = 0V
12 pF
Input Capacitance
VIN = 0V
6 pF
CIN
1
T8.0 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: RELIABILITY CHARACTERISTICS
Symbol
1
Parameter
Minimum Specification
Test Method
10,000
Cycles
JEDEC Standard A117
TDR1
Data Retention
100
Years
JEDEC Standard A103
ILTH1
Latch Up
100
mA
NEND
Endurance
Units
JEDEC Standard 78
T9.5 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
9
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
AC CHARACTERISTICS
TABLE 10: READ CYCLE TIMING PARAMETERS
FOR
SST29EE512
SST29EE512-70
Min
Max
SST29EE512-90
Symbol
Parameter
TRC
Read Cycle Time
TCE
Chip Enable Access Time
70
90
ns
TAA
Address Access Time
70
90
ns
TOE
Output Enable Access Time
30
40
ns
TCLZ1
TOLZ1
TCHZ1
TOHZ1
TOH1
CE# Low to Active Output
0
0
ns
OE# Low to Active Output
0
0
ns
70
Min
Max
90
Units
ns
CE# High to High-Z Output
20
30
ns
OE# High to High-Z Output
20
30
ns
Output Hold from Address Change
0
0
ns
T10.2 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: READ CYCLE TIMING PARAMETERS
FOR
SST29LE512
SST29LE512-150
Max
SST29LE512-200
Symbol
Parameter
Min
Min
Max
Units
TRC
Read Cycle Time
150
TCE
Chip Enable Access Time
150
200
ns
TAA
Address Access Time
TOE
Output Enable Access Time
150
200
ns
60
100
TCLZ1
TOLZ1
TCHZ1
TOHZ1
TOH1
ns
CE# Low to Active Output
0
0
ns
OE# Low to Active Output
0
0
ns
200
ns
CE# High to High-Z Output
30
50
ns
OE# High to High-Z Output
30
50
ns
Output Hold from Address Change
0
0
ns
T11.1 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: READ CYCLE TIMING PARAMETERS
FOR
SST29VE512
SST29VE512-200
Max
SST29VE512-250
Symbol
Parameter
Min
Min
Max
Units
TRC
Read Cycle Time
200
TCE
Chip Enable Access Time
250
ns
TAA
Address Access Time
TOE
Output Enable Access Time
200
250
ns
100
120
TCLZ1
TOLZ1
TCHZ1
TOHZ1
TOH1
ns
CE# Low to Active Output
0
0
ns
OE# Low to Active Output
0
0
ns
250
200
ns
CE# High to High-Z Output
50
50
ns
OE# High to High-Z Output
50
50
ns
Output Hold from Address Change
0
0
ns
T12.1 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
10
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS
SST29EE512
Symbol
Parameter
TWC
Write Cycle (Erase and Program)
TAS
Address Setup Time
0
0
ns
TAH
Address Hold Time
50
70
ns
TCS
WE# and CE# Setup Time
0
0
ns
TCH
WE# and CE# Hold Time
0
0
ns
TOES
OE# High Setup Time
0
0
ns
TOEH
OE# High Hold Time
0
0
ns
TCP
CE# Pulse Width
70
120
ns
TWP
WE# Pulse Width
70
120
ns
TDS
Data Setup Time
35
50
ns
Data Hold Time
0
0
ns
TDH
1
Min
Max
SST29LE/VE512
Min
10
Max
Units
10
ms
TBLC1
Byte Load Cycle Time
0.05
TBLCO1
Byte Load Cycle Time
200
TIDA1
Software ID Access and Exit Time
10
10
µs
TSCE
Software Chip-Erase
20
20
ms
100
0.05
100
200
µs
µs
T13.6 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
11
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
TRC
TAA
ADDRESS A15-0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
HIGH-Z
TCHZ
TOH
TCLZ
DATA VALID
DQ 7-0
DATA VALID
301 ILL F03.0
FIGURE 4: READ CYCLE TIMING DIAGRAM
Three-Byte Sequence for
Enabling SDP
ADDRESS A15-0
5555
2AAA
TAH
TAS
5555
TCS
TCH
CE#
TOES
TOEH
OE#
TWP
TBLCO
TBLC
WE#
TDH
DQ 7-0
AA
55
SW0
SW1
A0
DATA VALID
TWC
TDS
SW2
BYTE 0
BYTE 1
BYTE 127
301 ILL F04.1
FIGURE 5: WE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
12
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Three-Byte Sequence for
Enabling SDP
ADDRESS A15-0
5555
2AAA
TAH
TAS
5555
TCP
TBLCO
TBLC
CE#
TOES
TOEH
OE#
TCS
TCH
WE#
TDH
DQ 7-0
AA
55
SW0
SW1
A0
DATA VALID
TWC
TDS
SW2
BYTE 0
BYTE 1
BYTE 127
301 ILL F05.1
FIGURE 6: CE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
ADDRESS A15-0
TCE
CE#
TOES
TOEH
OE#
TOE
WE#
DQ 7
D
D#
D#
D
TWC + TBLCO
301 ILL F06.0
FIGURE 7: DATA# POLLING TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
13
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
ADDRESS A15-0
TCE
CE#
TOEH
TOES
TOE
OE#
WE#
DQ6
TWC + TBLCO
TWO READ CYCLES
WITH SAME OUTPUTS
301 ILL F07.0
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
Six-Byte Sequence for Disabling
Software Data Protection
ADDRESS A14-0
DQ 7-0
5555
AA
2AAA
5555
55
5555
80
2AAA
AA
TWC
5555
55
20
CE#
OE#
TBLCO
TWP
WE#
TBLC
SW0
SW1
SW2
SW3
SW4
SW5
301 ILL F08.1
FIGURE 9: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
14
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Six-Byte Code for Software Chip-Erase
ADDRESS A14-0
5555
DQ 7-0
2AAA
AA
5555
55
5555
80
2AAA
AA
TSCE
5555
55
10
CE#
OE#
TBLCO
TWP
WE#
TBLC
SW0
SW1
SW2
SW3
SW4
SW5
301 ILL F09.2
FIGURE 10: SOFTWARE CHIP-ERASE TIMING DIAGRAM
Three-Byte Sequence
for Software ID Entry
ADDRESS A14-0
5555
5555
2AAA
0000
0001
TAA
DQ 7-0
AA
55
BF
90
DEVICE ID
TIDA
CE#
OE#
TWP
WE#
TBLC
SW0
SW1
DEVICE ID = 5DH for SST29EE512
= 3DH for SST29LE512/29VE512
SW2
301 ILL F10.2
FIGURE 11: SOFTWARE ID ENTRY
AND
READ
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
15
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Three-Byte Sequence
for Software ID Exit and Reset
ADDRESS A14-0
DQ 7-0
5555
AA
2AAA
5555
55
F0
TIDA
CE#
OE#
TWP
WE#
TBLC
SW0
SW1
SW2
301 ILL F11.0
FIGURE 12: SOFTWARE ID EXIT AND RESET
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
16
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
VIHT
VHT
INPUT
VHT
REFERENCE POINTS
OUTPUT
VLT
VLT
VILT
301 ILL F12.1
AC test inputs are driven at VIHT (2.4V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for
inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE
VDD
TO TESTER
RL HIGH
TO DUT
CL
RL LOW
301 ILL F13.1
FIGURE 14: A TEST LOAD EXAMPLE
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
17
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Start
Software Data
Protect Write
Command
See Figure 17
Set Page
Address
Set Byte
Address = 0
Load Byte
Data
Increment
Byte Address
By 1
No
Byte
Address =
128?
Yes
Wait TBLCO
Wait for end of
Write (TWC,
Data# Polling bit
or Toggle bit
operation)
Write
Completed
301 ILL F14.1
FIGURE 15: WRITE ALGORITHM
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
18
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Page-Write
Initiated
Page-Write
Initiated
Page-Write
Initiated
Wait TWC
Read a byte
from page
Read DQ7
(Data for last
byte loaded)
Write
Completed
Read same
byte
No
Is DQ7 =
true data?
Yes
No
Does DQ6
match?
Write
Completed
Yes
Write
Completed
301 ILL F15.1
FIGURE 16: WAIT OPTIONS
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
19
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Software Data Protect Enable
Command Sequence
Software Data Protect
Disable Command Sequence
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: A0H
Address: 5555H
Write data: 80H
Address: 5555H
Load 0 to
128 Bytes of
page data
Optional Page Load
Operation
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Wait TBLCO
Write data: 20H
Address: 5555H
Wait TWC
Wait TBLCO
SDP Enabled
Wait TWC
SDP Disabled
301 ILL F16.1
FIGURE 17: SOFTWARE DATA PROTECTION FLOWCHARTS
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
20
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: 90H
Address: 5555H
Write data: F0H
Address: 5555H
Pause 10 µs
Pause 10 µs
Read Software ID
Return to normal
operation
301 ILL F17.1
FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
21
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Software Chip-Erase
Command Sequence
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 80H
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 10H
Address: 5555H
Wait TSCE
Chip-Erase
to FFH
301 ILL F18.2
FIGURE 19: SOFTWARE CHIP-ERASE COMMAND CODES
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
22
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
PRODUCT ORDERING INFORMATION
Device
SST29xE512
Speed
- XXX
Suffix1
-
XX
Suffix2
-
XX
Package Modifier
H = 32 leads
Numeric = Die modifier
Package Type
N = PLCC
W = TSOP (die up) (8mm x 14mm)
E = TSOP (die up) (8mm x 20mm)
P = PDIP
U = Unencapsulated die
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
250 = 250 ns
200 = 200 ns
150 = 150 ns
90 = 90 ns
70 = 70 ns
Voltage
E = 5.0V-only
L = 3.0-3.6V
V = 2.7-3.6V
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
23
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Valid combinations for SST29EE512
SST29EE512-70-4C-NH
SST29EE512-70-4I-NH
SST29EE512-70-4C-WH
SST29EE512-70-4I-WH
SST29EE512-70-4C-EH
SST29EE512-70-4I-EH
SST29EE512-70-4C-PH
SST29EE512-90-4C-U2
Valid combinations for SST29LE512
SST29LE512-150-4C-NH
SST29LE512-150-4I-NH
SST29LE512-150-4C-WH
SST29LE512-150-4I-WH
SST29LE512-150-4C-EH
SST29LE512-150-4I-EH
SST29LE512-200-4C-U2
Valid combinations for SST29VE512
SST29VE512-200-4C-NH
SST29VE512-200-4I-NH
SST29VE512-200-4C-WH
SST29VE512-200-4I-WH
SST29VE512-200-4C-EH
SST29VE512-200-4I-EH
SST29VE512-250-4C-U2
Note:
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
Note:
The software Chip-Erase function is not supported by the industrial temperature part.
Please contact SST, if you require this function for an industrial temperature part.
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
24
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
Optional
Pin #1 Identifier
SIDE VIEW
.485
.495
.447
.453
.042
.048
2
1
.106
.112
32
.020 R.
MAX.
.023
x 30˚
.029
.030
R.
.040
.042
.048
.585
.595
BOTTOM VIEW
.547
.553
.013
.021
.400
BSC
.026
.032
.490
.530
.050
BSC.
.015 Min.
.075
.095
.050
BSC.
.026
.032
.125
.140
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
32.PLCC.NH-ILL.2
4. Coplanarity: 4 mils.
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
1.05
0.95
Pin # 1 Identifier
.50
BSC
.270
.170
8.10
7.90
0.15
0.05
12.50
12.30
0.70
0.50
14.20
13.80
32.TSOP-WH-ILL.4
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM
SST PACKAGE CODE: WH
X
©2001 Silicon Storage Technology, Inc.
14MM
S71060-06-000 6/01
25
301
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
1.05
0.95
Pin # 1 Identifier
.50
BSC
.27
.17
8.10
7.90
0.15
0.05
18.50
18.30
0.70
0.50
Note:
20.20
19.80
1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM
SST PACKAGE CODE: EH
X
32.TSOP-EH-ILL.4
20MM
32
CL
.600
.625
Pin #1 Identifier
1
.530
.550
1.645
1.655
.065
.075
7˚
4 PLCS.
.170
.200
Base Plane
Seating Plane
.015
.050
.070
.080
Note:
.045
.065
.016
.022
.100 BSC
.120
.150
0˚
15˚
.008
.012
1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
.600 BSC
32.pdipPH-ILL.2
32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP)
SST PACKAGE CODE: PH
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
©2001 Silicon Storage Technology, Inc.
S71060-06-000 6/01
26
301