TI TAS5616PHD

TAS5616
www.ti.com
SLAS596B – JUNE 2009 – REVISED JANUARY 2010
160-W STEREO / 300-W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE
Check for Samples: TAS5616
FEATURES
APPLICATIONS
•
•
•
•
•
1
23
•
•
•
•
•
•
PurePath™ HD Enabled Integrated Feedback
Provides:
– Signal Bandwidth up to 80 kHz for
High-Frequency Content From HD Sources
– Ultralow 0.03% THD at 1 W into 8 Ω
– Flat THD at All Frequencies for Natural
Sound
– 80-dB PSRR (BTL, No Input Signal)
– >100-dB (A-weighted) SNR
– Click- and Pop-Free Startup
– Minimal External Components Compared to
Discrete Solutions
Multiple Configurations Possible on the Same
PCB With Stuffing Options:
– Mono Parallel Bridge-Tied Load (PBTL)
– Stereo Bridge-Tied Load (BTL)
– 2.1 Single-Ended Stereo Pair and
Bridge-Tied Load Subwoofer
– Quad Single-Ended Outputs
Total Output Power at 10% THD+N
– 330 W in Mono PBTL Configuration
– 160 W per Channel in Stereo BTL
Configuration
– 80 W per Channel in Quad Single-Ended
Configuration
High-Efficiency Power Stage (>90%) With
120-mΩ Output MOSFETs
Two Thermally Enhanced Package Options:
– PHD (64-Pin QFP)
– DKD (44-Pin PSOP3)
Self-Protection Design (Including
Undervoltage, Overtemperature, Clipping, and
Short-Circuit Protection) With Error Reporting
EMI Compliant When Used With
Recommended System Design
Mini Combo System
AV Receivers
DVD Receivers
Active Speakers
DESCRIPTION
The TAS5616 is a high-performance PWM-input
class-D amplifier with integrated closed-loop
feedback technology (known as PurePath™ HD
technology). It has the ability to drive up to 160-W
(1)
stereo into 8-Ω speakers from a single 50-V
supply.
PurePath™ HD technology enables traditional
AB-amplifier performance (<0.03% THD) levels while
providing the power efficiency of traditional class-D
amplifiers.
Ultralow 0.03% THD+N is flat across all frequencies,
ensuring that the amplifier does not add uneven
distortion characteristics, and helps maintain a natural
sound.
The efficiency of this class-D amplifier is greater than
90%. Undervoltage protection, overtemperature,
clipping, short-circuit and overcurrent protection are
all integrated, safeguarding the device and speakers
against fault conditions that could damage the
system. PurePath HD™
♫♪
ANALOG
AUDIO
INPUT
DIGITAL
AUDIO
INPUT
TAS3308
Digital Audio
Processor
With Analog Interface
TM
PurePath HD
TAS5616
TAS5630
(2.1 Configuration)
♫♪
♫♪
25 V–50 V
12 V
TM
+3.3V
REG.
PurePath HD
Power Supply
Ref. Design
110 VAC®240 VAC
(1)
Achievable output power levels are dependent on the thermal
configuration of the target application. A high performance
thermal interface material between the package exposed
thermal pad and the heat sink should be used to achieve high
output power levels.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath HD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
TAS5616
SLAS596B – JUNE 2009 – REVISED JANUARY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Terminal Assignment
The TAS5616 is available in two thermally enhanced packages:
• 44-Pin PSOP3 package (DKD)
• 64-Pin QFP (PHD) Power Package
Both package types contain a heat slug that is located on the top side of the device for convenient thermal
coupling to the heat sink.
DKD PACKAGE
(TOP VIEW)
64-pins QFP package
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
OTW2
CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PSU_REF
VDD
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
SD
OTW
READY
M1
M2
M3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 pins PACKAGE
(TOP VIEW)
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
SD
OTW1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
PHD PACKAGE
(TOP VIEW)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GVDD_AB
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD_CD
PIN ONE LOCATION PHD PACKAGE
Electrical Pin 1
Pin 1 Marker
White Dot
2
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
MODE SELECTION PINS
MODE PINS
M3
M2
M1
ANALOG
INPUT (1)
OUTPUT
CONFIGURATION
0
0
0
2N
2 × BTL
AD mode
0
0
1
—
—
Reserved
0
1
0
2N
2 × BTL
BD mode
0
1
1
1N
1 × BTL +2 × SE
AD mode
1
0
0
1N
4 × SE
AD mode
(1)
(2)
1
0
1
1
1
0
1
1
1
2N
1 × PBTL
DESCRIPTION
INPUT_C (2)
INPUT_D (2)
0
0
AD mode
1
0
BD mode
Reserved
The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=AGND)..
PACKAGE HEAT DISSIPATION RATINGS (1)
PARAMETER
TAS5616PHD
TAS5616DKD
RqJC (°C/W) – 2 BTL or 4 SE channels
3.63
2.52
RqJC (°C/W) – 1 BTL or 2 SE channel(s)
5.95
3.22
RqJC (°C/W) – 1 SE channel
Pad Area
(1)
(2)
(2)
9.9
6.9
49 mm2
80 mm2
JC is junction-to-case, CH is case-to-heat sink
RqCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heat sink and
both channels active. The RqCH with this condition is 1.22°C/W for the PHD package and 1.02°C/W for the DKD package
Table 1. ORDERING INFORMATION (1)
(1)
TA
PACKAGE
DESCRIPTION
0°C–70°C
TAS5616PHD
64 pin HTQFP
0°C–70°C
TAS5616DKD
44 pin PSOP3
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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TAS5616
SLAS596B – JUNE 2009 – REVISED JANUARY 2010
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5616
UNIT
VDD to AGND
–0.3 to 13.2
V
GVDD to AGND
–0.3 to 13.2
V
PVDD_X to GND_X (2)
–0.3 to 69.0
V
(2)
–0.3 to 69.0
V
BST_X to GND_X (2)
–0.3 to 82.2
V
BST_X to GVDD_X (2)
–0.3 to 69.0
V
VREG to AGND
–0.3 to 4.2
V
GND_X to GND
–0.3 to 0.3
V
GND_X to AGND
–0.3 to 0.3
V
GND to AGND
–0.3 to 0.3
V
OC_ADJ, M1, M2, M3, VI_CM, C_STARTUP, PSU_REF to AGND
–0.3 to 4.2
V
INPUT_X
–0.3 to 5.0
V
RESET, SD, OTW1, OTW2, CLIP, READY to AGND
–0.3 to 7.0
V
OUT_X to GND_X
Maximum continuous sink current (SD, OTW1, OTW2, CLIP, READY)
Maximum operating junction temperature range, TJ
Storage temperature, Tstg
Electrostatic discharge
(1)
(2)
(3)
Human-Body Model
(3)
Charged-Device Model
9
mA
0 to 150
°C
–40 to 150
°C
±2
kV
±500
V
(all pins)
(3)
(all pins)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
Failure to follow good anti-static ESD handling during manufacture and rework will contribute to device malfunction. Please ensure
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
PVDD_x
Half-bridge supply
DC supply voltage
Half-bridge supply, BTL 4Ω load
MAX
25
50
52.5
25
38
40
UNIT
V
GVDD_x
Supply for logic regulators and gate-drive
circuitry
DC supply voltage
10.8
12
13.2
V
VDD
Digital regulator supply voltage
DC supply voltage
10.8
12
13.2
V
7
8
3.5
4
RL(BTL)
RL(SE)
Load impedance
RL(PBTL)
Output filter according to
schematics in the application
information section.
LOUTPUT(BTL)
LOUTPUT(SE)
Output filter inductance
Minimum output inductance under
short-circuit condition
LOUTPUT(PBTL)
FPWM
PWM frame rate
TJ
Junction temperature
4
3.5
4
14
15
14
15
14
15
352
384
0
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Ω
mH
500
kHz
150
°C
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TAS5616
TAS5616
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
TERMINAL FUNCTIONS
TERMINAL
PHD
NO.
DKD
NO.
FUNCTION (1)
AGND
8
10
P
Analog ground
BST_A
54
43
P
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_A required.
BST_B
41
34
P
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_B required.
BST_C
40
33
P
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_C required.
BST_D
27
24
P
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_D required.
C_STARTUP
3
5
O
Startup ramp requires a charging capacitor of 4.7 nF to AGND
CLIP
18
—
O
Clipping warning; open drain; active low
GND
7, 23,
24, 57,
58
9
P
Ground
GND_A
48, 49
38
P
Power ground for half-bridge A
GND_B
46, 47
37
P
Power ground for half-bridge B
GND_C
34, 35
30
P
Power ground for half-bridge C
GND_D
32, 33
29
P
Power ground for half-bridge D
GVDD_A
55
—
P
Gate drive voltage supply requires 0.1 mF capacitor to AGND
GVDD_AB
—
44
P
Gate drive voltage supply requires 0.22 mF capacitor to AGND
GVDD_B
56
—
P
Gate drive voltage supply requires 0.1 mF capacitor to AGND
GVDD_C
25
—
P
Gate drive voltage supply requires 0.1 mF capacitor to AGND
GVDD_CD
—
23
P
Gate drive voltage supply requires 0.22 mF capacitor to AGND
GVDD_D
26
—
P
Gate drive voltage supply requires 0.1 mF capacitor to AGND
INPUT_A
4
6
I
Input signal for half bridge A
INPUT_B
5
7
I
Input signal for half bridge B
INPUT_C
10
12
I
Input signal for half bridge C
INPUT_D
11
13
I
Input signal for half bridge D
M1
20
20
I
Mode selection
M2
21
21
I
Mode selection
M3
22
22
I
Mode selection
NC
59-62
—
—
No connect, pins may be grounded.
NC
13
15
—
No connect, pins may be grounded.
NC
14
16
—
No connect, pins may be grounded.
OC_ADJ
1
3
O
Analog over current programming pin requires resistor to ground.
64 pin QFP package (PHD) = 22 kΩ
44 pin PSOP3 Package (DKD) = 24 kΩ
OTW
—
18
O
Overtemperature warning signal, open drain, active low.
OTW1
16
—
O
Overtemperature warning signal, open drain, active low.
OTW2
17
—
O
Overtemperature warning signal, open drain, active low.
OUT_A
52, 53
39, 40
O
Output, half bridge A
OUT_B
44, 45
36
O
Output, half bridge B
OUT_C
36, 37
31
O
Output, half bridge C
OUT_D
28, 29
27, 28
O
Output, half bridge D
63
1
P
PSU Reference requires close decoupling of 4.7 mF to AGND
PVDD_A
50, 51
41, 42
P
Power supply input for half bridges A requires close decoupling of 2.2-mF capacitor to GND_A
PVDD_B
42, 43
35
P
Power supply input for half bridges B requires close decoupling of 2.2-mF capacitor to GND_B
PVDD_C
38, 39
32
P
Power supply input for half bridges C requires close decoupling of 2.2-mF capacitor to GND_C
PVDD_D
30, 31
25, 26
P
Power supply input for half bridges D requires close decoupling of 2.2-mF capacitor to GND_D
READY
19
19
O
Normal operation; open drain; active high
RESET
2
4
I
Device reset Input; active low
SD
15
17
O
Shutdown signal, open drain, active low
TEST
12
14
I
Connect to VREG node
NAME
PSU_REF
(1)
DESCRIPTION
I = Input, O = Output, P = Power
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TERMINAL FUNCTIONS (continued)
TERMINAL
PHD
NO.
DKD
NO.
FUNCTION (1)
VDD
64
2
P
Power supply for digital voltage regulator requires a 10-mF capacitor in parallel with a 0.1-mF
capacitor to GND for decoupling.
VI_CM
6
8
O
Analog comparator reference input requires close decoupling of 4.7 mF to AGND
VREG
9
11
P
Digital regulator supply filter pin requires 0.1-mF capacitor to AGND
NAME
DESCRIPTION
TYPICAL SYSTEM BLOCK DIAGRAM
Caps for
External
Filtering
&
Startup/Stop
System
microcontroller
/AMP RESET
(2)
LeftChannel
Output
PWM_A
INPUT_A
PWM_B
INPUT_B
C_STARTUP
VI_CM
PSU_REF
/RESET
VALID
/CLIP
*NOTE1
READY
/SD
TAS5518/
TAS5508/
TAS5086
/OTW1, /OTW2, /OTW
I2C
BST_A
BST_B
OUT_A
Input
H-Bridge 1
Output
H-Bridge 1
2
OUT_B
2
Bootstrap
Caps
2nd Order
L-C Output
Filter for
each
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
PWM_C
INPUT_C
PWM_D
INPUT_D
OUT_C
Output
H-Bridge 2
Input
H-Bridge 2
2
OUT_D
8
50V
PVDD
12V
PVDD
Power Supply
Decoupling
SYSTEM
Power
Supplies
GND
8
OC_ADJ
TEST
AGND
VDD
M3
2nd Order
L-C Output
Filter for
each
H-Bridge
BST_C
VREG
M2
GND
M1
GND_A, B, C, D
Hardwire
Mode
Control
GVDD_A, B, C, D
2
PVDD_A, B, C, D
RightChannel
Output
BST_D
Bootstrap
Caps
4
GVDD, VDD,
& VREG
Power Supply
Decoupling
Hardwire
OverCurrent
Limit
GND
GVDD (12V)/VDD (12V)
VAC
*NOTE1: Logic AND in or outside microcontroller
6
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
FUNCTIONAL BLOCK DIAGRAM
/CLIP
READY
/OTW1
/OTW2
/SD
PROTECTION & I/O LOGIC
M1
M2
M3
/RESET
STARTUP
CONTROL
C_STARTUP
VDD
POWER-UP
RESET
UVP
VREG
VREG
AGND
TEMP
SENSE
GVDD_A
GVDD_C
GVDD_B
OVER-LOAD
PROTECTION
PPSC
CURRENT
SENSE
CB3C
4
4
4
GND
GVDD_D
OC_ADJ
PVDD_X
OUT_X
GND_X
GVDD_A
PWM
ACTIVITY
DETECTOR
BST_A
PVDD_A
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_A
GND_A
PSU_REF
GVDD_B
VI_CM
INPUT_D
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
-
+
ANALOG COMPARATOR MUX
PVDD_X
GND
PVDD_B
PWM
RECEIVER
+
ANALOG INPUT MUX
4
AGC
BST_B
+
ANALOG
LOOP FILTER
INPUT_B
INPUT_C
-
ANALOG
LOOP FILTER
INPUT_A
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_B
GND_B
GVDD_C
BST_C
PVDD_C
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
+
OUT_C
GND_C
-
GVDD_D
BST_D
PVDD_D
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_D
GND_D
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AUDIO CHARACTERISTICS (BTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM Processor (modulation index limited to 97.7%)
and a TAS5616 power stage. PCB and system configuration are in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM =
15 mH, CDEM = 680 nF, MODE = 000, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
RL = 8 Ω, 10% THD+N
160
RL = 8 Ω, 1% THD+N
125
MAX
UNIT
PO
Power output per channel
THD+N
Total harmonic distortion +
noise
1W
Vn
Output integrated noise
A-weighted, TAS5518 Modulator
|VOS|
Output offset supply
No signal
SNR
Signal to noise ratio (1)
A-weighted, TAS5518 Modulator
103
dB
DNR
Dynamic range
A-weighted, input level –60 dBFS using TAS5518 modulator
103
dB
Pidle
Power dissipation due to idle
losses (IPVDD_X)
PO = 0, 4 channels switching (2)
1.8
W
(1)
(2)
W
0.03%
185
mV
40
150
mV
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses also are affected by core losses of output inductors.
AUDIO SPECIFICATION (Single-Ended Output)
Audio performance is recorded as a chipset consisting of a TAS5086 PWM Processor (modulation index limited to 97.7%)
and a TAS5616 power stage. PCB and system configuration are in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4Ω, fS = 384 kHz, ROC_PHD = 22 kΩ, or ROC_DLD = 24 kΩ, TC =
75°C, Output Filter: LDEM = 15 mH, CDEM = 330 nF, MODE = 100, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
RL = 4 Ω, 10%, THD+N
75
RL = 4 Ω, 0 dBFS
60
UNIT
PO
Power output per channel
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, TAS5086 modulator
170
mV
A-weighted, TAS5086 modulator
98
dB
98
dB
2
W
SNR
Signal to noise ratio
(1)
0.05%
DNR
Dynamic range
A-weighted, input level –60 dBFS using TAS5086
modulator
Pidle
Power dissipation due to idle losses
(IPVDD_X)
PO = 0, 4 channels switching (2)
(1)
(2)
W
SNR is calculated relative to 1% THD+N output level
Actual system idle losses are affected by core losses of output inductors.
AUDIO SPECIFICATION (PBTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM Processor (modulation index limited to 97.7%)
and a TAS5616 power stage. PCB and system configuration are in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4Ω, fS = 384 kHz, ROC_PHD = 22 kΩ, ROC_DKD = 24 kΩ, TC = 75°C,
Output Filter: LDEM = 15 mH, CDEM = 680 nF, MODE = 101-00, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
RL = 4 Ω, 10%, THD+N
300
RL = 4 Ω, 1%, THD+N
210
UNIT
PO
Power output per channel
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, TAS5518 modulator
180
mV
SNR
Signal to noise ratio (1)
A-weighted, TAS5518 modulator
103
dB
DNR
Dynamic range
A-weighted, input level –60 dBFS using
TAS5518 modulator
103
dB
Pidle
Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching (2)
1.8
W
(1)
(2)
8
W
0.03%
SNR is calculated relative to 1% THD+N output level
Actual system idle losses are affected by core losses of output inductors.
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as reference
node
VI_CM
Analog comparator reference node
IVDD
VDD supply current
IGVDD_x
Gate-supply current per half-bridge
IPVDD_x
Half-bridge idle current
VDD = 12 V
3
3.3
3.6
V
1.5
1.75
1.9
V
Operating, 50% duty cycle
22.5
Idle, reset mode
22.5
50% duty cycle
mA
8
Reset mode
mA
1.5
50% duty cycle without output filter or
load
9
mA
Reset mode, No switching
610
mA
TJ = 25°C, exclude metallization
resistance, GVDD = 12 V
120
200
mΩ
120
200
mΩ
OUTPUT-STAGE MOSFETs
RDS(on),LS
Drain-to-source resistance, (LS)
RDS(on),HS
Drain-to-source resistance, (HS)
I/O PROTECTION
Vuvp,G
Vuvp,hyst
Undervoltage protection limit, GVDD_x
9.5
(1)
V
0.6
V
OTW1 (1)
Overtemperature warning 1
95
100
105
°C
OTW2 (1)
Overtemperature warning 2
115
125
135
°C
OTWHYST
Temperature drop needed below OTW
temperature for OTW to be inactive after
OTW event.
(1)
OTE (1)
Overtemperature error
OTEOTWdifferential
OTEHYST
25
(1)
OLPC
IOC
(1)
145
155
°C
165
°C
OTE-OTW differential
30
°C
A reset needs to occur for SD to be released
following an OTE event
25
°C
fPWM = 384 kHz
2.6
ms
Resistor – programmable, nominal peak
current in 1Ω load, 64 pin QFP package
(PHD)
ROCP = 22 kΩ
10
A
Resistor – programmable, nominal peak
current in 1Ω load, 44 pin PSOP3
package (DKD)
ROCP = 24 kΩ
10
A
10
A
Overload protection counter
Overcurrent limit protection
IOC_LATCHED
Overcurrent limit protection
Resistor – programmable, nominal peak
current in 1Ω load,
ROCP = 47 kΩ
IOCT
Overcurrent response time
Time from application of short condition to
Hi-Z of affected half bridge
150
ns
IPD
Output pulldown current of each half bridge
Connected when RESET is active to
provide bootstrap charge. Not used in SE
mode.
3
mA
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
VIL
Low level input voltage
Leakage
Input leakage current
(1)
INPUT_X, M1, M2, M3, RESET
2
V
0.8
V
100
mA
Specified by design.
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
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ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
OTW/SHUTDOWN (SD)
RINT_PU
Internal pull-up resistance, OTW1 to VREG,
OTW2 to VREG, SD to VREG
VOH
High level output voltage
VOL
Low level output voltage
IO = 4 mA
FANOUT
Device fanout OTW1, OTW2, SD, CLIP,
READY
No external pull-up
10
Internal pull-up resistor
External pull-up of 4.7 kΩ to 5 V
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20
26
32
3
3.3
3.6
4.5
5
200
30
500
kΩ
V
mV
devices
Copyright © 2009–2010, Texas Instruments Incorporated
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TAS5616
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC+NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
TC = 75°C
5
2
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
10
1
0.5
0.2
0.1
0.05
8W
0.02
0.01
0.005
20m
100m 200m
1 2
10 20
PO - Output Power - W
100 200
Figure 1.
Figure 2.
UNCLIPPED OUTPUT POWER
vs
SUPPLY VOLTAGE
SYSTEM EFFICIENCY
vs
OUTPUT POWER
100
150
140
TC = 75°C
THD+N at 1%
130
90
70
100
Efficiency - %
PO - Output Power - W
110
90
8W
70
60
50
60
50
40
30
40
30
TC = 25°C
THD+N at 10%
20
20
10
10
0
8W
80
120
80
180
170 TC = 75°C
160 THD+N at 10%
150
140
130
120
110
8W
100
90
80
70
60
50
40
30
20
10
0
25 27 29 31 33 35 37 39 41 43 45 47 49
VCC - Supply Voltage - Vrms
25 27 29 31 33 35 37 39 41 43 45 47 49
VCC - Supply Voltage - Vrms
0
0
40
Figure 3.
80 120 160 200 240 280 320 360
2 Channel Output Power - W
Figure 4.
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEM POWER LOSS
vs
OUTPUT POWER
OUTPUT POWER
vs
CASE TEMPERATURE
40
200
TC = 25°C
THD+N at 10%
36
180
160
PO - Output Power - W
Power Loss - W
32
28
24
20
16
8W
12
8W
140
120
100
80
60
40
8
THD+N at 10%
20
4
0
10 20
0
0
40
80
120 160 200 240 280
2 Channel Output Power - W
320 360
30
Figure 5.
40 50 60 70 80 90 100 110 120
TC - Case Temperature - C
Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY - VREF = 32.7 V
0
-20
Noise Amplitude - dB
-40
TC = 75°C
VREF = 32.69V
Sample Rate = 48 kHz
FFT Size = 16384
-60
-80
-100
-120
8W
-140
-160
0
12
2
4
6
8 10 12 14 16
f - Frequency - kHz
Figure 7.
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20 22
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
TYPICAL CHARACTERISTICS, SE CONFIGURATION
TOTAL HARMONIC DISTORTION
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
10
4W
2
70
6W
1
0.5
8W
0.2
0.1
0.05
60
4W
50
6W
40
30
8W
20
0.02
10
0.01
0.005
20m
TC = 75°C
THD+N at 10%
80
PO - Output Power - W
THD - Total Harmonic Distortion - %
5
90
TC = 75°C
100m 200m
1
2
10 20
PO - Output Power - W
0
100
25 27 29 31 33 35 37 39 41 43 45 47 49
VCC - Supply Voltage - Vrms
Figure 8.
Figure 9.
OUTPUT POWER
vs
CASE TEMPERATURE
90
80
4W
PO - Output Power - W
70
60
6W
50
40
8W
30
20
THD+N at 10%
10
0
10
20
30
40 50 60 70 80 90 100 110 120
TC - Case Temperature - °C
Figure 10.
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC DISTORTION
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
10
TC = 75°C
2
1
PO - Output Power - W
THD - Total Harmonic Distortion - %
4W
6W
0.2
8W
0.1
0.02
0.01
0.005
20m 100m 200m 1 2
10 20
100 200 500
PO - Output Power - W
340
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
25
TC = 75°C
THD+N at 10%
4W
6W
8W
27 29 31 33 35 37 39 41 43 45 47 49
VCC - Supply Voltage - Vrms
Figure 11.
Figure 12.
PO - Output Power - W
OUTPUT POWER
vs
CASE TEMPERATURE
360
340
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
10
4W
6W
8W
THD+N at 10%
20
30
40
50
60
70
80
90 100 110 120
TC - Case Temperature - °C
Figure 13.
14
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
APPLICATION INFORMATION
PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. (70 mm) is recommended for use with the TAS5616. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
PVDD Capacitor Recommendation
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000mF, 63V will support more
applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with
high-speed switching.
Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 0.1mF that is placed on the power supply to each half-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 63V is required for use with a 50V power
supply.
System Design Recommendations
The following schematics and PCB layouts illustrate best practices in the use of the TAS5616.
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15
R_RIGHT_N
IN_RIGHT_P
IN_LEFT_N
IN_LEFT_P
100R
R13
100R
R12
100R
R11
100R
R10
100R
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READY
/CLIP
/OTW2
/OTW1
/SD
C18
100pF
GND
GND
GND
GND
GND
100nF
C22
VREG
GND
VREG
4.7uF
C21
4.7nF
22.0k
C20
R20
4.7uF
/OTW1
/SD
NC
NC
TEST
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
/RESET
OC_ADJ
GND
NC
READY
VREG
NC
M1
VDD
/OTW2
GND
NC
M2
C23
PSU_REF
/CLIP
/RESET
R19
47k
GND
U10
TAS5616PHD
GND
GND
C33
100nF
GND
GND
GND
GND
GND
NC
M3
C31
100nF
C32
100nF
GND GND
C40
33nF
3.3R
3.3R
R33
R32
C43
33nF
BST_A
BST_D
C30
100nF
OUT_A
OUT_D
3.3R
GVDD_B
GVDD_C
C26
100nF
GVDD_A
GVDD_D
R18
VREG
C25
10uF
OUT_A
OUT_D
R31
C60
2.2uF
C63
2.2uF
PVDD_A
PVDD_D
3.3R
GND_A
PVDD_A
PVDD_D
16
GND_D
R30
GND_D
GND_C
GND_C
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND_B
GND_B
GND_A
GND
GND
C62
2.2uF
C61
2.2uF
GND
L13
15uH
15uH
L12
C42
33nF
C41
33nF
L11
15uH
L10
15uH
1000uF
C65
C53
680nF
C52
680nF
GND
C51
680nF
C50
680nF
C72
1nF
GND
C73
1nF
GND
1000uF
C66
C71
1nF
GND
C70
1nF
R73
3.3R
C77
10nF
C76
10nF
R72
3.3R
GND
GND
C68
47uF
63V
R71
3.3R
C75
10nF
C74
10nF
R70
3.3R
GND
GND
C67
1000uF
GND
C69
2.2uF
GND
C64
1000uF
OUT_RIGHT_R
-
+
GND
OUT_RIGHT_P
C78
10nF
R74
3.3R
GND
PVDD
GVDD/VDD (+12V)
PVDD
GND
OUT_LEFT_M
-
+
OUT_LEFT_P
PVDD
GVDD/VDD (+12V)
TAS5616
SLAS596B – JUNE 2009 – REVISED JANUARY 2010
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Figure 14. Typical Differential (2N) BTL Application With BD Filters
Copyright © 2009–2010, Texas Instruments Incorporated
READY
/CLIP
/OTW2
/OTW1
/SD
IN_N
IN_P
/RESET
100R
100R
100R
GND
100pF
GND
VREG
47k
GND
GND
GND
GND
100nF
4.7uF
4.7nF
22.0k
VREG
VREG
GND
GND
1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
/OTW1
/SD
NC
NC
TEST
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
/RESET
OC_ADJ
4.7uF
GND GND
100nF
64
VDD
VREG
10uF
63
18
/OTW2
17
PSU_REF
/CLIP
100nF
GND
GND
GND GND
58
100nF
100nF
GND
GND GND
100nF
TAS5616PHD
VREG
33nF
3.3R
3.3R
3.3R
3.3R
33nF
GND
24
62
NC
READY
19
57
GND
GVDD_C
25
54
GVDD_D
26
61
NC
M1
20
56
GVDD_B
BST_A
BST_D
27
53
OUT_A
OUT_D
28
60
NC
M2
55
GVDD_A
29
52
OUT_A
OUT_D
51
PVDD_A
PVDD_D
30
50
PVDD_A
PVDD_D
31
59
NC
M3
22
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23
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21
GND
GND
49
GND_A
GND_D
32
VDD (+12V)
2.2uF
GND_D
GND_C
GND_C
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND_B
GND_B
GND_A
GND
2.2uF
48
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
GND
2.2uF
2.2uF
GND
33nF
33nF
15uH
15uH
15uH
15uH
1000uF
1000uF
680nF
GND
680nF
1000uF
1000uF
GND
GND
1nF
1nF
GND
GND
47uF
GND
3.3R
10nF
10nF
3.3R
GND
GVDD (+12V)
PVDD
OUT_LEFT_M
-
+
OUT_LEFT_P
10nF
3.3R
GND
GND
2.2uF
PVDD
GVDD (+12V)
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
TAS5616
Figure 15. Typical (2N) PBTL Application With AD Modulation Filters
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17
READY
/CLIP
/OTW2
/OTW1
/SD
IN_D
IN_C
IN_B
IN_A
/RESET
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130 kOhm
147 kOhm
165 kOhm
182 kOhm
191 kOhm
50 V
49 V
48 V
47 V
<47 V
R_COMP
GND
PVDD
100R
100R
100R
100R
100R
100pF
PVDD
PVDD
C
A
47k
10k
470uF
R_COMP
10k
10k
10k
GND
GND
R_COMP
100nF
4.7uF
10nF
470uF
470uF
470uF
GND
GND
GND
GND
22.0k
VREG
10k
10k
VREG
GND
GND
1
2
16
15
14
13
12
11
10
9
8
7
6
5
4
3
330nF
330nF
/OTW1
/SD
NC
NC
TEST
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
/RESET
OC_ADJ
4.7uF
100nF
100nF
100nF
100nF
62
NC
100nF
61
GND
GND
60
10nF
10nF
3.3R
3.3R
10nF
10nF
3.3R
3.3R
GND
GND
GND GND
58
GND GND
100nF
100nF
57
54
59
TAS5616PHD
GND
GND
OUT_C_M
-
+
OUT_C_P
GND
GND
OUT_A_M
-
+
OUT_A_P
GND
GND
100nF
VREG
PVDD
PVDD
D
B
GND GND
100nF
33nF
52
3.3R
3.3R
53
470uF
470uF
470uF
470uF
3.3R
3.3R
33nF
50
PVDD_A
VREG
10uF
64
VDD
/OTW2
17
63
PSU_REF
/CLIP
18
READY
19
NC
M1
20
NC
M3
22
NC
21
GND
GND
23
GND
24
M2
56
GVDD_B
GVDD_C
25
51
GND
GND
49
GND_A
R_COMP
R_COMP
10k
10k
10k
10k
GND_D
55
GVDD_A
GVDD_D
26
BST_A
BST_D
27
OUT_A
OUT_D
28
OUT_A
OUT_D
29
PVDD_A
PVDD_D
30
PVDD_D
31
18
32
VDD (+12V)
2.2uF
GND_D
GND_C
GND_C
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND_B
GND_B
GND_A
GND
2.2uF
10k
10k
48
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
330nF
330nF
GND
100nF
100nF
100nF
100nF
GND
2.2uF
2.2uF
33nF
33nF
GND
GND
10nF
47uF
10nF
3.3R
3.3R
10nF
10nF
3.3R
3.3R
15uH
15uH
15uH
15uH
GND
GND
OUT_D_M
-
+
OUT_D_P
GND
GND
OUT_B_M
-
+
OUT_B_P
GND
GND
2.2uF
GND
10nF
3.3R
GVDD (+12V)
D
PVDD
C
PVDD
B
PVDD
A
GVDD (+12V)
TAS5616
SLAS596B – JUNE 2009 – REVISED JANUARY 2010
www.ti.com
Figure 16. Typical SE Application
Copyright © 2009–2010, Texas Instruments Incorporated
READY
/CLIP
/OTW2
/OTW1
/SD
IN_RIGHT
IN_LEFT
IN_CENTER
/RESET
VDD (+12V)
100R
100R
100R
100R
GND
100pF
47k
VREG
GND
GND
GND
GND
100nF
4.7uF
10nF
22.0k
VREG
GND
VREG
VREG
GND
182 kOhm
191 kOhm
47 V
<47 V
165 kOhm
147 kOhm
49 V
48 V
R_COMP
130 kOhm
PVDD
/OTW1
/SD
NC
NC
TEST
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
/RESET
OC_ADJ
4.7uF
GND GND
100nF
63
50 V
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
10uF
64
VDD
/OTW2
17
PSU_REF
/CLIP
18
100nF
60
61
62
NC
19
READY
VREG
20
NC
M1
GND
GND GND
59
100nF
GND
100nF
GND
3.3R
3.3R
33nF
GND GND
100nF
TAS5616PHD
NC
M3
22
NC
58
GND
GND
23
M2
54
3.3R
3.3R
33nF
GVDD_D
26
53
BST_A
BST_D
27
57
GND
GND
24
Product Folder Link(s) :TAS5616
25
Copyright © 2009–2010, Texas Instruments Incorporated
21
55
GVDD_A
OUT_A
OUT_D
28
52
OUT_A
OUT_D
29
51
PVDD_A
PVDD_D
30
50
PVDD_A
PVDD_D
31
56
GVDD_B
GVDD_C
49
GND_A
GND_D
32
2.2uF
GND_D
GND_C
GND_C
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND_B
GND_B
GND_A
GND
2.2uF
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
GND
2.2uF
2.2uF
GND
15uH
PVDD
15uH
PVDD
33nF
33nF
470uF
470uF
470uF
470uF
1000uF
10k
GND
10k
10k
R_COMP
GND
GND
10k
R_COMP
GND
47uF
GND
10k
10k
10nF
3.3R
GND
2.2uF
15uH
680nF
GND
680nF
15uH
GND
330nF
GND
GND
330nF
GND
1nF
1nF
10nF
100nF
100nF
10nF
10nF
100nF
100nF
10nF
1000uF
3.3R
GND
3.3R
3.3R
GND
3.3R
3.3R
10nF
10nF
3.3R
GND
+
-
GVDD (+12V)
PVDD
OUT_RIGHT_M
-
+
OUT_RIGHT_P
OUT_LEFT_M
-
+
OUT_LEFT_P
PVDD
OUT_CENTER_M
GND
OUT_CENTER_P
PVDD
GVDD (+12V)
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
TAS5616
Figure 17. Typical 2.1 System (2N) Input BTL and (1N) Input SE Application
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20
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READY
/OTW
/SD
IN_RIGHT_N
IN_RIGHT_P
IN_LEFT_N
IN_LEFT_P
/RESET
VDD (+12V)
100R
100R
100R
100R
100R
GND
100pF
VREG
47k
GND
GND
GND
GND
GND
100nF
4.7uF
4.7nF
24k
4.7uF
VREG
10uF
GND
GND
GND
VREG
VREG
GND
100nF
1
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
M3
M2
M1
READY
/OTW
/SD
NC
NC
TEST
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
/RESET
OC_ADJ
VDD
PSU_REF
TAS5616DKD
GVDD_CD
BST_D
PVDD_D
PVDD_D
OUT_D
OUT_D
GND_D
GND_C
OUT_C
PVDD_C
BST_C
BST_B
PVDD_B
OUT_B
GND_B
GND_A
OUT_A
OUT_A
PVDD_A
PVDD_A
BST_A
GVDD_AB
100nF
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
GND
100nF
33nF
1.5R
33nF
GND
100nF
GND
33nF
GND
33nF
100nF
1.5R
2.2uF
2.2uF
2.2uF
2.2uF
GND
15uH
680nF
GND
GND
1000uF
680nF
15uH
GND
1000uF
15uH
680nF
GND
680nF
15uH
1nF
1nF
GND
1000uF
47uF
1nF
1nF
1000uF
GND
3.3R
10nF
10nF
3.3R
GND
2.2uF
3.3R
10nF
10nF
3.3R
GND
+
-
GND
+
-
OUT_RIGHT_M
GND
OUT_RIGHT_P
10nF
3.3R
OUT_LEFT_M
GND
OUT_LEFT_P
GVDD (+12V)
PVDD
PVDD
PVDD
GVDD (+12V)
TAS5616
SLAS596B – JUNE 2009 – REVISED JANUARY 2010
www.ti.com
Figure 18. Typical Input BTL Application and BD Modulation Filters DKD Package
Copyright © 2009–2010, Texas Instruments Incorporated
TAS5616
www.ti.com
SLAS596B – JUNE 2009 – REVISED JANUARY 2010
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5616 needs only a 12V supply in addition to the (typical) 50V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive
and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has
separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the
same 12V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300kHz to 400kHz, it is recommended to use 33nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient energy storage, even during
minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining
part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2mF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5616 reference design. For additional information on recommended power
supply and required components, see the application diagrams given previously in this data sheet.
The 12V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50V
power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not
critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5616 is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5616 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedance
state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically
required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal
circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
Powering Down
The TAS5616 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
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TAS5616
SLAS596B – JUNE 2009 – REVISED JANUARY 2010
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ERROR REPORTING
The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 goes low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see the following table).
SD
OTW1
OTW2,
OTW
DESCRIPTION
0
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
0
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature
higher than 100°C (overtemperature warning)
0
1
1
Overload (OLP) or undervoltage (UVP)
1
0
0
Junction temperature higher than 125°C (overtemperature warning)
1
0
1
Junction temperature higher than 100°C (overtemperature warning)
1
1
1
Junction temperature lower than 100°C and no OLP or UVP faults
(normal operation)
Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature
warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device
shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW
outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics table of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5616 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5616 responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and over-temperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device will function on errors, as shown in the following table.
BTL MODE
LOCAL ERROR IN
A
B
C
D
PBTL MODE
TURNS OFF
A+B
B+D
LOCAL ERROR IN
SE MODE
TURNS OFF
A
B
C
LOCAL ERROR IN
A
A+B+B+D
D
B
C
D
TURNS OFF
A+B
B+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge.
PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage in the case that a power output pin
(OUT_X) is shorted to GND_X or PVDD_X. For comparison the OC protection system detects an over current
after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system
startup will not activate the PPSC detection system. When PPSC detection is activated by a short on the output,
all half bridges are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence
and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that
there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to
PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The
22
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TAS5616
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
typical duration is < 15 ms/mF. While the PPSC detection is in progress, SD is kept low, and the device will not
react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is
released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output
configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system it
is recommended not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options have individual over-temperature protection schemes.
PHD Package
The TAS5616 PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package
The TAS5616 DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5616 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics Table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when
asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD
output, i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after
an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the
falling edge of SD.
SYSTEM DESIGN CONSIDERATION
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
Apply only audio when the state of READY is high that will start and stop the amplifier without having audible
artifacts that is heard in the output transducers. If an overcurrent protection event is introduced the READY signal
goes low hence filtering is needed if the signal is intended for audio muting.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply controlling a low and a high rail.
The VREG pin is not recommended to be used as a voltage source for external circuitry.
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TAS5616
SLAS596B – JUNE 2009 – REVISED JANUARY 2010
www.ti.com
PRINTED CIRCUIT BOARD RECOMMENDATION
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply for
power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high fast switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
the audio input should be kept short and together with the accompanied audio source ground. A local ground
area underneath the device is important to keep solid to minimize ground bounce.
Netlist for this printed circuit board is generated from the schematic in Figure 14.
Note T1: PVDD decoupling bulk capacitors C60-C64 should be as close as possible to the PVDD and GND_X pins,
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
Note T3: Heat sink needs to have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range preferable metal film types.
Figure 19. Printed Circuit Board - Top Layer
24
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TAS5616
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SLAS596B – JUNE 2009 – REVISED JANUARY 2010
Note B1: It is important to have a direct low impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low impedance X7R ceramic capacitors placed on bottom side providing a short low inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors.
Figure 20. Printed Circuit Board - Bottom Layer
REVISION HISTORY
Changes from Original (June 2009) to Revision A
•
Page
Deleted Product Preview from the PHD package ................................................................................................................. 3
Changes from Revision A (September 2009) to Revision B
Page
•
NC pin function changed from "I/O" to "—" .......................................................................................................................... 5
•
OLPC typical value changed from 1.3 ms to 2.6 ms ............................................................................................................ 9
•
Changed error-reporting bits from 010 to 011 .................................................................................................................... 22
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25
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jan-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TAS5616DKD
ACTIVE
HSSOP
DKD
44
29
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
TAS5616DKDR
ACTIVE
HSSOP
DKD
44
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
TAS5616PHD
ACTIVE
HTQFP
PHD
64
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-5A-260C-24 HR
TAS5616PHDR
ACTIVE
HTQFP
PHD
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-5A-260C-24 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TAS5616DKDR
HSSOP
DKD
44
500
330.0
24.4
TAS5616PHDR
HTQFP
PHD
64
1000
330.0
24.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
14.7
16.4
4.0
20.0
24.0
Q1
17.0
17.0
1.5
20.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5616DKDR
HSSOP
DKD
TAS5616PHDR
HTQFP
PHD
44
500
346.0
346.0
41.0
64
1000
346.0
346.0
41.0
Pack Materials-Page 2
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products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DLP® Products
www.dlp.com
Communications and
Telecom
www.ti.com/communications
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
www.ti.com/clocks
Consumer Electronics
www.ti.com/consumer-apps
Interface
interface.ti.com
Energy
www.ti.com/energy
Logic
logic.ti.com
Industrial
www.ti.com/industrial
Power Mgmt
power.ti.com
Medical
www.ti.com/medical
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
www.ti.com/video
Wireless
www.ti.com/wireless-apps
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