L9777 Low power voltage regulator Features ■ Operating DC supply voltage range 5.6 V to 31 V ■ Low current consumption (110 µA typ @ Iout = 0) ■ High precision output voltage (2 %) ■ Low dropout voltage ■ VDD tracking regulator switchable on/off by VDD_EN pin ■ Reset circuit sensing the output voltage down to 1 V. ■ Double reset function ■ Adjustable reset threshold ■ External capacitor to set NMI/ reset power up delay and watchdog frequency ■ Over temperature protection ■ Wide temperature range (TJ = -40 °C to 150 °C) ■ Short circuit proof ■ Suitable for use in automotive electronics Table 1. PowerSSO-12 (exposed DIE Pad) Description The L9777 is a monolithic integrated low drop regulator which can supply up to 200 mA, available in the PowerSSO-12 package. It is designed to supply microprocessor systems under severe conditions of automotive applications and therefore equipped with additional protection functions against over load, short circuit and over temperature. Of course the L9777 can also be used in other applications where a regulated voltage is required. Device summary Order code Package Packing L9777A PowerSSO-12 Tray L9777B PowerSSO-12 Tray L9777B13TR PowerSSO-12 Tape and reel L9777C PowerSSO-12 Tray December 2010 Doc ID 13496 Rev 2 1/25 www.st.com 1 Contents L9777 Contents 1 Block diagrams and pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Block diagram (option A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Option B features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Option C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 NMI and RESET driver delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 RESET adjustable threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 VDD regulated voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 VDD_LOW (option C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Option A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Option B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Option C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Electrical and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 Doc ID 13496 Rev 2 L9777 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Doc ID 13496 Rev 2 3/25 List of figures L9777 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. 4/25 Block diagram (option A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package pin configuration (options A and B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block diagram (option B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram (option C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package pin configuration (option C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCC versus output current IVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Filter time between VCC and NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset time diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Filter time between NMI and RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 RESET and NMI drivers fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Resistor divider to adjust the under voltage threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Watchdog timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VDD_LOW filter tim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PowerSSO-12 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 23 Doc ID 13496 Rev 2 L9777 Block diagrams and pins configuration 1 Block diagrams and pins configuration 1.1 Block diagram (option A) Figure 1. Block diagram (option A) VDD_EN VDD IVDD=100mA C VDD IVDD_EN VI Vbatt VCC IVCC=200mA 3R C VCC Start up VMUXTH R GND VCC 1.26V Voltage Reference VOFF RADJ + _ 1 IWD_EN WD_EN TIMING 0 RRESET RNMI C TIMING RESET Delay watchdog WD NMI RWD Low Voltage Reset D VD CD 1.2 Option B features ● VDD can sustain short to 40 V regardless of VI battery voltage ● Current capability of VDD scaled down to 50 mA with dropout of 1.5 V (Max.) ● In default condition, VDD and WD functions are disabled using 2 pull down current on VDD_EN and WD_EN pin ● Standby current consumption reduced to 100 µA (Typ.) Figure 2. Package pin configuration (options A and B) RESET 1 12 RADJ NMI 2 11 GND D 3 10 VDD VDD_EN 4 9 VCC WD 5 8 TIMING WD_EN 6 7 VI PinConfA_B Doc ID 13496 Rev 2 5/25 Block diagrams and pins configuration Figure 3. L9777 Block diagram (option B) VDD_EN IVDD_EN VDD IVDD= 50 mA VCC VI Vbatt C VDD IVCC=200mA 3R C VCC Start up VMUXTH R GND Voltage Reference 1.26V VOFF RADJ + _ 1 WD_EN TIMING 0 RRESET RNMI C TIMING RESET IWD_EN Delay watchdog WD NMI RWD Low Voltage Reset D VD CD Figure 4. Block diagram (option C) VDD_EN IVDD = 50mA IVDD_EN VDD C VDD 300mV VI Vbatt VCC IVCC=200mA 3R C VCC Start up VMUXTH R GND Voltage Reference 1.26V VOFF RADJ + _ 1 WD_EN 0 RVDD_LOW RNMI IWD_EN Low Voltage Reset watchdog WD RWD D VD VDD_LOW NMI Low Voltage Reset CD 1.3 6/25 Option C features ● VDD can sustain short to 40 V regardless of VI battery voltage ● Current capability of VDD scaled down to 50 mA with dropout of 1.5V (Max.) ● In default condition, VDD and WD functions are disabled using 2 pull down current on VDD_EN and WD_EN pin ● Double reset function removed and pin RESET used to detect undervoltage condition on VDD regulated voltage (VDD_LOW pin) Doc ID 13496 Rev 2 L9777 Block diagrams and pins configuration Figure 5. Package pin configuration (option C) VDD_LOW 1 12 RADJ NMI 2 11 GND D 3 10 VDD VDD_EN 4 9 VCC WD 5 8 N.C. WD_EN 6 7 VI PinConfC Table 2. Pin# Pin description I/O Name Function OPTION A & B: RESET output. This pin is set low if NMI output goes low for adjustable filter time RESET/VDD_LOW OPTION C: VDD_LOW output This pin is set low when undervoltage on VDD is detected 1 O 2 O NMI 3 I D NMI/RESET power up delay. External cap on this pin sets the time response of the VCC low voltage detector and the time response of the watchdog monitor. VDD control. OPTION A: If this pin is low VDD output voltage is not available (connect this pin to VCC or left floating to switch on VDD output voltage) OPTION B & C: If this pin is low or left floating VDD output voltage is not available (connect this pin to VCC to switch on VDD regulator) 4 I VDD_EN 5 I WD 6 I WD_EN 7 I VI Non maskable Interrupt Output This pin is set low when low voltage on VCC is detected or frequency of WD signal is too low. Watchdog input. If the frequency at this input pin is too low, the NMI output is activated low Watchdog function enable/disable OPTION A: If this pin is low the watchdog function is disabled, if connected to VCC or left floating the watchdog function is enabled. OPTION B & C: If this pin is low or floating, the watchdog function is disabled, if connected to VCC the watchdog function is enabled. Input voltage Block to GND with a capacitor of value at least 100 nF Doc ID 13496 Rev 2 7/25 Block diagrams and pins configuration Table 2. Pin# Pin description (continued) I/O Name Function OPTION A & B: RESET filter time External cap on this pin sets the delay time between NMI and RESET output OPTION C: not used and should be left floating or shorted to ground. 8 I TIMING 9 O VCC Voltage regulator output External cap CVCC ≥ 220 nF is needed to stabilize the regulator 10 O VDD VDD Output regulated voltage switched on/off by VDD_EN pin. External cap CVDD=100 nF is needed to stabilize the regulator GND Ground RADJ VCC under voltage Threshold Adjustment By connecting this pin to an external resistor divider vs. VCC, is possible to set the VCC under voltage threshold. If this pin is connected to GND the under voltage threshold is set by internal circuit. 11 12 8/25 L9777 I Doc ID 13496 Rev 2 L9777 2 Absolute maximum ratings Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Min. Max. Unit -0.3 40 V Input voltage VI VVI Voltage IVI Current Internal limited VCC VVCC Voltage IVCC Current -0.3 5.5 V Internal limited NMI VNMI Voltage INMI Current VD Voltage -0.3 VCC+0.3 V Internal limited D -0.3 Current VCC+0.3 V Internal limited RADJ VRADJ Voltage IRADJ Current -0.3 VCC+0.3 V Internal limited WD VWD Voltage IWD Current -0.3 VCC+0.3 V Internal limited WD_EN VWD_EN Voltage IWD_EN Current -0.3 VCC+0.3 V Internal limited VDD_EN VVDD_EN Voltage IVDD_EN Current -0.3 VCC+0.3 V Internal limited RESET VRESET Voltage IRESET Current -0.3 VCC+0.3 V Internal limited Doc ID 13496 Rev 2 9/25 Absolute maximum ratings Table 3. L9777 Absolute maximum ratings (continued) Symbol Parameter Min. Max. Unit -0.3 - V Timing VI + 0.3 (Opt. A) 40V (Opt. B) Not connected (Opt. C) VTIMING Voltage ITIMING Current Internal limited VDD VVDD Voltage IVDD Current -0.3 VI + 0.3 40V 40V (Opt. A) (Opt. B) (Opt. C) V Internal limited Temperature TJ Junction temperature -40 150 °C -1.5 1.5 kV ESD voltage level VESD 10/25 HBM-MIL STD 883C Doc ID 13496 Rev 2 L9777 Functional description 3 Functional description 3.1 Voltage regulator This device supply an always active 5 V regulated voltage on pin VCC with a current capability up to 200 mA. VCC voltage has an accuracy of 2% over a wide supply voltage (VI = 5.6 V to 31 V) and temperature range (TJ = -40 °C to 150 °C). A short circuit protection to GND is provided (see Figure 6). By means of tracking regulator, it is available a second output regulated voltage on pin VDD with a current capability up to 50mA. This regulated output is switchable on/off by external pin VDD_EN. Figure 6. VCC versus output current IVCC VCC VCCREF ISHORT 3.2 ILIM IVCC Reset The reset circuit monitors the output voltage VCC. In case of internal reset threshold, if the output voltage stays lower than VCCUN for a filter time TRR, then NMI goes low. This filter time depends on the distance between the VCC output and the under voltage reset threshold (VCCUN): this solution increases the noise immunity of the voltage regulator be-cause the filter time between the reset event and the falling of NMI output changes according to the depth of spike on output voltage (see following picture). A minimum filter time of 1 µs (TRR1) is guaranteed if VCC goes down to 2.5 V and VS > 5.6 V. Figure 7. Filter time between VCC and NMI VCC VCC VCCUN V1 2.5V NMI NMI TRR1 TRR2 Otherwise, in case of external reset threshold fixed by means of external resistor divider on pin RADJ, there is only a constant filter time (TRRADJ) of 1 µs min value. Doc ID 13496 Rev 2 11/25 Functional description L9777 In both cases, if the output voltage VCC becomes lower than 2.0V (typ) than NMI may go immediately low without any delay. The NMI low signal is guaranteed for an output voltage VCC greater than 1V. When VCC returns over VCCUN threshold NMI goes high with a filter time TRD. This time is obtained by 127 period of an oscillator with an additional initial time. The oscillator period is given by: ( VDU – VDRL ) ⋅ CD ]- + [---------------------------------------------------------( VDU – VDRL ) ⋅ CD ]TOSC = [---------------------------------------------------------IRC IRD where: ICR = 20 µA (typ) is a current internally generated, IDR = 20 µA (typ) is a current internally generated, VDU = 1.24 V and VDRL = 0.62 V are two typical internal thresholds, CD is the external capacitance on pin D. TRD is given by: TRD (s) = T0 + 127 x TOSC = 0.62*10-3 + 7.874* 106 * CD (typ) Where T0 is the initial ramp between 0 V and VDU as in Figure 8. Figure 8. Reset time diagram RRUN VCCUN VCC TOSC < TRR TRR TRR VDU VD VDRL TRD = T0 + 127 TOSC TRD = T0 + 127 TOSC NMI < TRESDF TRESDR RESET TRESDF TRESDF VBGAP VTIMING If NMI output goes to 0 V for filter time TRESDF (which is fixed by external cap on TIMING pin) also the RESET signal goes to 0 V. RESET low signal is guaranteed for VCC > 1 V. Figure 9. Filter time between NMI and RESET < TRESDF NMI RESET 12/25 Doc ID 13496 Rev 2 TRESDF L9777 3.3 Functional description NMI and RESET driver delay NMI and RESET pins are driven by bipolar transistor with a maximum current capability internally limited of value respectively INMIL and IRESL. For this reason, when the drivers are activated, the capacitors present on pin NMI or RESET are discharged with constant current. The waveform on output pin is a voltage ramp with a slope linearly dependent on external capacitance. The fall time needed by drivers to discharge external capacitor can be calculated in first approximation using this expression. ( ΔV ⋅ C ext ) t fall = ---------------------------I lim Where ΔV is the voltage difference between 90% and 10% of total voltage swing of the transition, Cext is the total pin capacitance and Ilim is the current limitation of the driver (IRESL and INMIL). Figure 10. RESET and NMI drivers fall time RESET (V) 5 90% Vsw Vsw 10% Vsw VRESL Tfall Doc ID 13496 Rev 2 TIME (µs) 13/25 Functional description 3.4 L9777 RESET adjustable threshold The under voltage threshold value (VCCUN) can be set between 0.7VCC (typ.) and 0.96VCC (typ) by connecting external resistor divider to RADJ pin (see Figure 11). This feature can be used with microprocessors that guarantee a safe operation with supply voltage lower than internal reset threshold. The calculation of this threshold is given by: VCCUN_ext = VRADJTH (1+R1/R2) (neglecting RADJ input current) where: VRADJTH=1.2V (typ) and VCCUN_ext is the reset threshold. If this features is not needed, RADJ pin has to be connected to GND, in this case the internal under voltage threshold value is 0.94*VCC (typ.). Figure 11. Resistor divider to adjust the under voltage threshold VCC L9777 R1 RADJ R2 3.5 Watchdog The watchdog input WD monitors a connected microcontroller. If pulses are missing, the output NMI is set to low. The minimum WD frequency to avoid reset event can be set with the external capacitor CD. The watchdog circuit charges and discharges the capacitor CD with the constant currents IWC and IWD, counting the number of oscillations as for TRD delay time. If no rising edge is sensed on pin WD between 48 oscillation periods (TWOP TWOL, time A to B in Figure 12), a watchdog reset is generated. To prevent this reset the microcontroller must generate a positive edge during this time window in order to reset the counter. Minimum frequency of microprocessor input signal can be calculated using following equation: TWOP - TWOL = 48 * TOSC = 2.976*106*CD s Every WD positive edge resets the counter and makes a synchronization between internal oscillator and external WD input signal. Synchronization is realized changing the current from charging to discharging if rising edge is detected during rising ramp on CD (time D in Figure 12). Otherwise if rising edge is detected during falling ramp on CD, no current inversion is performed (time E). This operation leads to a maximum error of half oscillation period on TWOP - TWOL time window. When NMI goes low for watchdog reset, the counter will go on for other 16 counts, returning to initial state (time B to C in Figure 12). During this time (TWOL) the NMI remains low and WD edges are masked, so the TWOL reset time is fully guaranteed. The Watchdog operation is not active only if WD_EN input pin is set low. 14/25 Doc ID 13496 Rev 2 L9777 Functional description In this case the capacitor CD, when not used for VCC undervoltage condition, is pulled down to 0V by an active switch. At time F we can see that during TWOL reset time, WD_EN pin is not sensed, so the watchdog function can be disabled only when TWOL is finished. In this way a full reset time is guaranteed even in this condition. Figure 12. Watchdog timing waveforms A B C D E F WD_EN The watchdog disable is sensed only when TWOL is finisched TWOP NMI No current inversion TWOL Counter state is incremented when the high threshold is reached TWOL VDTHH VDTHL CD 48 osc 48 osc 16 osc Current inversion on cap CD WD COUNTER RESET 0 1 2 3 47 63 0 1 2 3 0 1 5 0 1 2 3 47 48 63 0 TRESDF filter time Doc ID 13496 Rev 2 15/25 VDD regulated voltage 4 L9777 VDD regulated voltage L9777 provides a second regulated voltage in tracking with VCC main regulator capable to source load with up to 100 mA output current capability. VDD tracking regulator function is controlled by VDD_EN input pin. If pin is set high VDD voltage becomes available. If pin is set low or left floating regulator is disabled. Note that VDD regulator will be disable also in case of undervoltage condition on VCC main regulator, so at power up regulator will start up only when VCC rises over undervoltage threshold without TRD power up delay time, even if VDD_EN pin is set high. 16/25 Doc ID 13496 Rev 2 L9777 5 VDD_LOW (option C) VDD_LOW (option C) VDD_LOW circuit monitors VDD regulated voltage. When VDD falls below VDDUN for a filter time TFVDD VDD_LOW output voltage is set low. VDDUN is a reference voltage 300 mV (Typ) lower than VCC regulated voltage. Filter time TFVDD is spike dependent as TRR1 for VCC regulator so the same consideration applies also in this case. Figure 13. VDD_LOW filter tim VDD VCC VDDUN VDDUN - 100mV 2.5 V VDD_LOW VDD_LOW TFVDD11 Doc ID 13496 Rev 2 TFVDD2 17/25 Device options 6 Device options 6.1 Option A L9777 This is the standard configuration with VDD output capable to source up to 100 mA to an external load with low dropout (400 mV max.) and double reset function provided (NMI and RESET output). Note that as we can see in absolute section VDD and TIMING pin are capable to sustain only short to VI pin. With this option input digital pins VDD_EN and WD_EN are both pulled up by 5 µA typ current source (minimum quiescent current is 110 µA typ.). 6.2 Option B With this option VDD and TIMING pins are both capable to sustain short to 40V regardless of VI battery voltage. To provide this feature a series diode is introduced between VI pin and VDD power PMOS source. In this configuration current capability on VDD output is scaled down to 50 mA while dropout voltage increases to 1.5V (Max). All other features are unchanged and double reset capability is maintained. In option B VDD_EN and WD_EN are both pulled down with 10 µA typ internal current source so minimum quiescent current is reduced to 100 µA typ. 6.3 Option C Using option C VDD is capable to sustain short to 40 V as in option B. VDD output current is scaled down to 50 mA and dropout increase up to 1.5 V (Max). Double reset feature is removed and RESET pin is used to monitor VDD output voltage (VDD_LOW pin). A spike dependent filter time similar to VCC main regulator is provided and same low voltage reset specifications applies to bipolar output driver (VDD_LOW driver). For this reason TIMING pin is no more used and can be left floating or shorted to ground. Note that NMI output pin behaves normally as in option A and becomes the main reset signal for VCC and watchdog monitor. As in option B VDD_EN and WD_EN are both pulled down with 10 µA typ internal current source so minimum quiescent current is reduced to 100 µA typ. 18/25 Doc ID 13496 Rev 2 L9777 7 Electrical and thermal characteristics Electrical and thermal characteristics VI = 5.6V to 31V, TJ = -40°C to +150°C unless otherwise specified. Table 4. Pin Electrical and thermal characteristics Symbol Parameter Test condition Min. Typ. Max. Unit General VCC VCCREF Output voltage VI = 5.6 to 31 V IVCC = 0 to 200 mA 4.9 5.00 5.1 V VCC ISHORT Short circuit current VCC = 0 V 150 250 500 mA VCC ILIM1 210 300 600 mA Output current limitation Current consumption with watchdog not active IQS0 = IVI-IVCC Option A VI =13.5 V, IVCC = 0 mA, WD_EN = 0 V VDD_EN = 0 V (VDD disabled) - 110 220 μA Option B VI = 13.5 V, IVCC = 0 mA, WD_EN floating or low, VDD_EN floating or low (VDD disabled) - 100 200 μA Option C VI = 13.5 V, IVCC = 0 mA, WD_EN floating or low, VDD_EN floating or low (VDD reset active) - 400 700 µA IQS200 Current consumption IQS200 = IVI-IVCC VI = 13.5 V, IVCC = 200 mA - 2 3 mA VI, VCC VDP1 Dropout voltage IVCC = 200 mA - 200 400 mV VCC VLINE1 Line regulation voltage VI = 5.6 to 31 V IVCC = 0 to 200 mA - - 25 mV VCC VLOAD1 Load regulation voltage IVCC = 0 to 200 mA - - 25 mV VCC SVR Ripple rejection fr = 100 Hz 55 - - dB - TW Thermal protection temperature - 150 - 190 °C - TWH Thermal protection temperature hysteresis - - 10 - °C NMI VNMIL NMI output low voltage Rext = 5 kΩ to VCC, VCC > 1 V - - 0.4 V NMI INMILK NMI output leakage current VNMI = 5 V - - 1 μA NMI RNMI Pull up internal resistance - 12 25 50 kΩ IQS0 VI, VCC NMI Doc ID 13496 Rev 2 19/25 Electrical and thermal characteristics Table 4. L9777 Electrical and thermal characteristics (continued) Pin Symbol NMI VCCUN RADJ VRADJTH RADJ VRJMUXTH D Parameter Test condition Min. Typ. Max. Unit 4.5V 0.94 VCC 0.96 VCC - Threshold for VCC under voltage detection 1.15 1.20 1.25 V Threshold for RADJ multiplexer comparator - 0.52 0.62 0.72 V VDU NMI timing high threshold - 1.14 1.24 1.34 V D VDRL NMI timing low threshold - 0.52 0.62 0.72 V D IRC Charge current VI = 13.5 V VD = 0.1 V 10 20 40 μA D IRD Discharge current VI = 13.5 V VD = 2.5 V 10 20 40 μA NMI TRR1 NMI spike dependent filter time in case of internal reset threshold VCC > 2 V RADJ = 0V 1 - - μs NMI TRRADJ NMI fixed filter time in case of external reset threshold External resistor divider on RADJ (see Figure 11). VCC > 2 V 1 2.5 5 μs NMI TRD NMI power up delay VI =13.5 V, CD=10 nF 45 80 115 ms NMI INMIL NMI limitation current - 5 - 25 mA Reset output low voltage Rext = 5 kΩ to VCC, VCC > 1 V - - 0.4 V RESET output leakage current - - - 1 μA RESET limitation current - 5 25 mA VCC under voltage threshold RADJ = 0 V RESET (option A & B) RESET VRESL RESET IRESETLK RESET IRESL RESET TRESDF RESET delay from NMI falling edge CTIMING = 2.2 nF RESET TRESDR RESET delay from NMI rising edge RESET RRESET Pull up internal resistance 350 550 750 μs - - - 1 μs - 12 25 50 kΩ - - 0.4 V - - - 1 μA VDD_LOW IVDD_LOWL RESET limitation current - 5 - 25 mA 12 25 50 kΩ VDD_LOW (option C) VDD_LOW VVDD_LOWL Reset output low voltage Rext = 5 kΩ to VCC, VCC > 1 V VDD_LOW IVDD_LOWLK VDD_LOW RVDD_LOW 20/25 RESET output leakage current Pull up internal resistance - Doc ID 13496 Rev 2 L9777 Table 4. Pin Electrical and thermal characteristics Electrical and thermal characteristics (continued) Symbol Parameter VDD_EN VVDDTHL VDD_EN input low threshold VDD_EN VVDDTHH VDD_EN Test condition Min. Typ. Max. Unit - - - 0.30 VCC V VDD_EN input high threshold - 0.70 VCC - - V VVDDHY VDD_EN hysteresis - 200 500 800 mV VDD_EN IVDD_EN Pull up current Option A - 2.5 5 10 μA VDD_EN IVDD_EN Pull down current Option B and C - 5 10 20 μA Output voltage difference IVDD=1 to 100 mA between VDD and VCC -25 - 25 mV 110 200 400 mA VDD_EN VDD (option A) VDD,VCC DIFFVR VDD ILIM2 VDD output limitation current - VI,VDD VDP2 Dropout voltage IVDD=100 mA - 200 400 mV VDD VLINE2 VDD Line regulation voltage VI = 5.6 to 31 V IVDD = 1 to 100 mA - - 25 mV VDD VLOAD2 VDD Load regulation voltage IVDD = 1 to 100 mA - - 25 mV Output voltage difference IVDD = 1 to 50mA VI = 6.6 to 31V between VDD and VCC -25 - 25 mV 55 100 240 mA VDD (option B) VDD,VCC DIFFVR VDD ILIM2 VDD output limitation current VI = 6.6 to 31V VI,VDD VDP2 Dropout voltage IVDD = 50mA; VI = 6.6 to 31V - - 1.5 V VDD VLINE2 VDD Line regulation voltage IVDD = 1 to 50mA VI = 6.6 to 31V - - 25 mV VDD VLOAD2 VDD Load regulation voltage IVDD = 1 to 50mA VI = 6.6 to 31V - - 25 mV Doc ID 13496 Rev 2 21/25 Electrical and thermal characteristics Table 4. Pin L9777 Electrical and thermal characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Output voltage difference IVDD = 1 to 50 mA between VDD and VCC VI = 6.6 to 31 V -25 - 25 mV 55 100 240 mA VDD (option C) VDD,VCC DIFFVR VDD ILIM2 VDD output limitation current VI = 6.6 to 31 V VI,VDD VDP2 Dropout voltage IVDD = 50 mA; VI = 6.6 to 31 V - - 1.5 V VDD VLINE2 VDD Line regulation voltage VI = 6.6 to 31 V IVDD = 1 to 50 mA - - 25 mV VDD VLOAD2 VDD Load regulation voltage IVDD = 1 to 50 mA VI = 6.6 to 31 V - - 25 mV VDD VDDUN VDD undervoltage threshold VI = 6.6 to 31 V VCC400 VCC300 VCC200 mV VDD TFVDD VDD spike dependent undervoltage filter time VDD transition from 5 V to 4 V 1 - - µs WD WD VWDTHH Input high voltage - - - 0.3 VCC V WD VWDTHL Input low voltage - 0.7 VCC - - V WD VWDHY WD input hysteresis - 250 500 800 mV WD RWD Pull down resistor - 15 35 80 kΩ D IWDC Charge current VD = 0.1 V; VI = 13.5 V 10 20 40 μA D IWDD Discharge current VD = 2.5 V; VI = 13.5 V 10 20 40 μA D VDTHL Low threshold - 0.52 0.62 0.72 V D VDTHH High threshold - 1.14 1.24 1.34 V D TWOP Watchdog period CD =10 nF 20 40 80 ms D TWOL Watchdog output low time CD =10 nF 5 10 20 ms WD_EN WD_EN VWENTL WD_EN input low voltage - - - 0.30 VCC - WD_EN VWENTH WD_EN input high voltage - 0.70 VCC - - - WD_EN VWENHY WD_EN input hysteresis - 200 500 800 mV WD_EN IWD_EN Pull up current Option A - 2.5 5 10 μA WD_EN IWD_EN Pull down current Option B and C - 5 20 μA 22/25 Doc ID 13496 Rev 2 10 L9777 8 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 14. PowerSSO-12 mechanical data and package dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. A 1.250 1.620 0.049 0.002 A1 0.000 0.100 0.000 0.004 A2 1.100 1.650 0.043 0.065 B 0.230 0.410 0.009 0.016 C 0.190 0.250 0.007 0.010 D (1) 4.800 5.000 0.189 0.197 E 3.800 4.000 0.150 e 0.800 OUTLINE AND MECHANICAL DATA MAX. 0.157 0.031 H 5.800 6.200 0.228 0.244 h 0.250 0.500 0.010 0.020 L 0.400 1.270 0.016 0.050 k 0¡ 8¡ 0¡ 8¡ X 1.900 2.500 0.075 0.098 Y 3.600 4.200 0.142 ddd 0.100 0.165 PowerSSO-12 (Exposed Pad) 0.004 Note: 1. D does not include mold flash or protrusions or gate burrs. Mold flash potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total. D 0.25 mm GAUGE PLANE h x 45˚ C A2 A B ddd 12 SEATING PLANE C A1 C L K 7 X E H Y 1 BOTTOM VIEW 6 e 7392413 A Doc ID 13496 Rev 2 23/25 Revision history 9 L9777 Revision history Table 5. Revision history Date Revision 10-May-2007 1 Initial release. 2 Changed ESD parameter values in Table 3. Modified Section 1.3: Option C features on page 6. Modified Section 6.3: Option C on page 18. Updated Table 4: Electrical and thermal characteristics on page 19. Document status promoted from preliminary data to datasheet. 14-Dec-2010 24/25 Description of changes Doc ID 13496 Rev 2 L9777 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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