TP0604 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / BVDGS RDS(ON) (max) ID(ON) (min) VGS(th) (max) -40V 2.0Ω -2.0A -2.4V Order Number / Package TO-92 SOW-20* TP0604N3 TP0604WG * Same as SO-20 with 300 mil wide body. Features Low Threshold DMOS Technology ❏ Low threshold — -2.4V max. These low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. ❏ High input impedance ❏ Low input capacitance — 95pF typical ❏ Fast switching speeds ❏ Low on resistance ❏ Free from secondary breakdown Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. ❏ Low input and output leakage ❏ Complementary N- and P-channel devices Applications Package Options ❏ Logic level interfaces – ideal for TTL and CMOS ❏ Solid state relays ❏ Battery operated systems ❏ Photo voltaic drives ❏ Analog switches ❏ General purpose line drivers ❏ Telecom switches SGD Absolute Maximum Ratings TO-92 Drain-to-Source Voltage BVDSS Drain-to-Gate Voltage BVDGS Gate-to-Source Voltage ± 20V Operating and Storage Temperature Soldering Temperature* SOW-20 -55°C to +150°C 300°C Note 1: Note 2: * Distance of 1.6 mm from case for 10 seconds. See Package Outline section for dimensions. See Array section for quad pinouts. 11/12/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 TP0604 Thermal Characteristics Package ID (continuous)* TO-92 ID (pulsed) -0.43A SOW-20 Power Dissipation @ TC = 25°C -4.2A θjc θja °C/W °C/W 1W 125 170 IDR* IDRM -0.43A -4.2A Refer to Enhancement Mode MOSFET Arrays Section * ID (continuous) is limited by max rated Tj. Electrical Characteristics (@ 25°C unless otherwise specified) Parameter Min BVDSS Drain-to-Source Breakdown Voltage -40 VGS(th) Gate Threshold Voltage -1.0 ∆V GS(th) Change in VGS(th) with Temperature IGSS Gate Body Leakage IDSS Zero Gate Voltage Drain Current ID(ON) -3.0 ON-State Drain Current RDS(ON) Typ -0.4 -0.6 -2.0 -3.3 Max VGS = 0V, ID = -2.0mA -2.4 V VGS = VDS, ID = -1.0mA -4.5 mV/°C VGS = VDS, ID = -1.0mA -100 nA VGS = ±20V, VDS = 0V -10 µA VGS = 0V, VDS = Max Rating -1.0 mA VGS = 0V, VDS = 0.8 Max Rating TA = 125°C A VGS = -5V, VDS = -20V VGS = -10V, VDS = -20V 3.5 1.5 2.0 0.75 1.2 ∆RDS(ON) Change in RDS(ON) with Temperature GFS Forward Transconductance CISS Input Capacitance 95 150 COSS Common Source Output Capacitance 85 120 CRSS Reverse Transfer Capacitance 35 60 td(ON) Turn-ON Delay Time 5.0 8 tr Rise Time 7.0 18 td(OFF) Turn-OFF Delay Time 10 15 tf Fall Time 6.0 19 VSD Diode Forward Voltage Drop -1.3 -2.0 trr Reverse Recovery Time 300 0.4 Conditions V 2.0 Static Drain-to-Source ON-State Resistance Unit Ω VGS = -5V, ID = -250mA VGS = -10V, ID = -1.0A %/°C VGS = -10V, ID = -1.0A 0.6 Ω Symbol VDS = -20V, ID = -1.0A pF VGS = 0V, VDS = -20V f = 1 MHz ns VDD = -20V ID = -1.0A RGEN = 25Ω V VGS = 0V, ISD = -1.5A ns VGS = 0V, ISD = -1.5A Notes: 1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 0V 10% PULSE GENERATOR INPUT 90% -10V t(ON) td(ON) Rgen t(OFF) td(OFF) tr tF D.U.T. 0V 90% OUTPUT INPUT 90% RL OUTPUT VDD 10% 10% VDD 2 TP0604 Typical Performance Curves -( ') / * ( '+,) & ! +% ( % ( * / * ( '+,) 12 ( +% & % & $ * ° % & $ * ° % 1( '2) -( ') /0 ') & $ * ° % & % % -( ') -( ') ! " # $ % & '() % & * ° % % ( '+,) % &, ',.!) 3 & '°) &, % % % & 1 ( * 3 & * ° % % % % ' !) TP0604 Typical Performance Curves BVDSS Variation with Temperature On-Resistance vs. Drain Current 1.1 7.5 VGS = -5V VGS = -10V RDS(ON) (ohms) BVDSS (normalized) 6.0 1.0 5.0 3.0 1.5 0 0.9 -50 0 50 100 0 150 -1 -2 Tj (°C) -3 -4 -5 ID (amperes) Transfer Characteristics V(th) and RDS Variation with Temperature 2.0 --5 VDS = -25V 1.4 -4 = TA -2 TA = C 0° 15 V(th) @ -1mA 1.2 1.2 RDS(ON) @ -10V, -1.0A 1.0 0.8 0.8 RDS(ON) (normalized) = °C 25 A -3 T ID (amperes) -5 VGS(th) (normalized) 5° C 1.6 0.4 -1 0.6 0 0 0 -2 -4 -6 -8 -10 -50 0 50 VGS (volts) 150 Tj (°C) Capacitance vs. Drain-to-Source Voltage Gate Drive Dynamic Characteristics 200 –10 f = 1MHz –8 VDS = -10V 150 180 pF VGS (volts) C (picofarads) 100 CISS 100 COSS –6 VDS = -40V –4 50 CRSS –2 75 pF 0 0 0 -10 -20 -30 -40 0 VDS (volts) 0.5 1.0 1.5 2.0 2.5 QG (nanocoulombs) 11/12/01 ©2001 Supertex Inc. All rights reserved. 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