TI TPA6204A1

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SLOS429 − MAY 2004
FEATURES
D Designed for Wireless or Cellular Handsets
APPLICATIONS
D Ideal for Wireless Handsets
D PDAs
D Notebook Computers
D
and PDAs
1.7 W Into 8 Ω From a 5-V Supply at
THD = 10% (Typ)
Low Supply Current: 4 mA typ at 5 V
Shutdown Current: 0.01 mA Typ
D
D
D Fast Startup With Minimal Pop
D Only Three External Components
DESCRIPTION
− Improved PSRR (−80 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) for Direct Battery
Operation
− Fully Differential Design Reduces RF
Rectification
− −63 dB CMRR Eliminates Two Input
Coupling Capacitors
D Pin to Pin Compatible With TPA2005D1 and
TPA6211A1 in QFN Package
D Available in 3 mm X 3 mm QFN Package
(DRB)
The TPA6204A1 is a 1.7-W mono fully-differential
amplifier designed to drive a speaker with at least 8-Ω
impedance while consuming only 20 mm2 total
printed-circuit board (PCB) area in most applications. The
device operates from 2.5 V to 5.5 V, drawing only 4 mA of
quiescent supply current. The TPA6204A1 is available in
the space-saving 3 mm x 3 mm QFN (DRB) package.
The TPA6204A1 is ideal for PDA/smart phone
applications due to features such as −80-dB supply
voltage rejection from 20 Hz to 2 kHz, improved RF
rectification immunity, small PCB area, and a fast startup
with minimal pop.
APPLICATION CIRCUIT
8-pin QFN (DRB) PACKAGE
(TOP VIEW)
VDD 6
Cs
40 kΩ
− RI
In From
DAC
+ RI
4
IN−
3
IN+
_
+
40 kΩ
VO+ 5
SHUTDOWN
C(BYPASS)(1)
SHUTDOWN
1
8 V
O−
BYPASS
2
7 GND
IN+
3
6 VDD
IN−
4
5 VO+
VO− 8
DGN Package
(TOP VIEW)
GND 7
2
1
To Battery
Bias
Circuitry
100 kΩ
SHUTDOWN
BYPASS
IN+
IN−
1
8
2
7
3
6
4
5
VO−
GND
VDD
VO+
(1) C(BYPASS) is optional.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
! " #$%! " &$'(#! )!% )$#!"
# ! "&%##!" &% !*% !%" %+" "!$%!" "!)) ,!-
)$#! &#%"". )%" ! %#%""(- #($)% !%"!. (( &%!%"
Copyright  2004, Texas Instruments Incorporated
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SLOS429 − MAY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGED DEVICE
QFN (DRB)
MSOP (DGN)
Device
TPA6204A1DRB
TPA6204A1DGN
Symbolization
AYJ
TBD
(1) The DRB is only available taped and reeled. To order taped and reeled parts, add the suffix R to the part number (TPA6204A1DRBR).
TERMINAL FUNCTIONS
TERMINAL
NAME
DRB
I/O
DESCRIPTION
IN−
4
I
Negative differential input
IN+
3
I
Positive differential input
VDD
VO+
6
I
Power supply
5
O
Positive BTL output
GND
7
I
High-current ground
VO−
SHUTDOWN
8
O
Negative BTL output
1
I
Shutdown terminal (active low logic)
BYPASS
2
Thermal Pad
−
Mid-supply voltage, adding a bypass capacitor improves PSRR
−
Connect to ground. Thermal pad must be soldered down in all applications to properly secure device
on the PCB.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage, VDD
−0.3 V to 6 V
Input voltage, VI
Continuous total power dissipation
−0.3 V to VDD + 0.3 V
See Dissipation Rating Table
Operating free-air temperature, TA
−40°C to 85°C
Junction temperature, TJ
−40°C to 150°C
Storage temperature, Tstg
−65°C to 85°C
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds
DRB
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS
PACKAGE
TA ≤ 25
25°C
C
POWER RATING
DRB
2.7 W
(1))Derating factor based on high-k board layout.
DERATING FACTOR(1)
TA = 70
70°C
C
POWER RATING
TA = 85
85°C
C
POWER RATING
21.8 mW/°C
1.7 W
1.4 W
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VDD
2.5
High-level input voltage, VIH
SHUTDOWN
Low-level input voltage, VIL
SHUTDOWN
Operating free-air temperature, TA
2
TYP
MAX
5.5
1.55
−40
UNIT
V
V
0.5
V
85
°C
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SLOS429 − MAY 2004
ELECTRICAL CHARACTERISTICS, TA = 25°C
PARAMETER
TEST CONDITIONS
VOS
Output offset voltage (measured
differentially)
PSRR
Power supply rejection ratio
VIC
Common mode input range
CMRR
Common mode rejection ratio
VDD = 5.5 V,
VDD = 2.5 V,
VIC = 0.5 V to 4.7 V
VIC = 0.5 V to 1.7 V
Low-output swing
RL = 8 Ω,
VIN+ = VDD,
VIN+ = 0 V,
Gain = 1 V/V,
VIN− = 0 V or
VIN− = VDD
RL = 8 Ω,
VIN+ = VDD,
VIN− = VDD
Gain = 1 V/V,
VIN− = 0 V or
VIN+ = 0 V
High-output swing
VI = 0 V differential, Gain = 1 V/V,
MIN
VDD = 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 2.5 V to 5.5 V
TYP
−9
MAX
0.3
9
mV
−85
−60
dB
V
−63
VDD−0.8
−40
−63
−40
0.5
VDD = 5.5 V
VDD = 3.6 V
0.45
VDD = 2.5 V
VDD = 5.5 V
0.26
VDD = 3.6 V
VDD = 2.5 V
UNIT
0.37
dB
V
0.4
4.95
3.18
2
V
2.13
| IIH |
High-level input current, SHUTDOWN
VDD = 5.5 V,
VI = 5.8 V
58
100
µA
| IIL |
Low-level input current, SHUTDOWN
VDD = 5.5 V,
VI = −0.3 V
3
100
µA
IQ
Quiescent current
4
6
mA
I(SD)
Supply current
VDD = 2.5 V to 5.5 V, no load
V(SHUTDOWN) ≤ 0.5 V, VDD = 2.5 V to 5.5 V,
RL = 8 Ω
0.01
1
µA
38 kΩ
RI
RL = 8 Ω
Gain
Resistance from shutdown to
GND
40 kΩ
RI
42 kΩ
RI
100
V/V
kΩ
OPERATING CHARACTERISTICS, TA = 25°C, Gain = 1 V/V
PARAMETER
TEST CONDITIONS
THD + N= 1%, f = 1 kHz,
RL = 8 Ω
PO
Output power
THD + N= 10%, f = 1 kHz,
RL = 8 Ω
THD+N
kSVR
SNR
Vn
Total harmonic distortion plus noise
Supply ripple rejection ratio
Start-up time from shutdown
0.33
VDD = 3.6 V
VDD = 2.5 V
0.85
VDD = 3.6 V,
Inputs ac-grounded
with Ci = 2 µF,
V(RIPPLE) = 200 mVpp
VDD = 3.6 V
VIC = 1 Vpp
PO = 1 W,
MAX
0.72
UNIT
W
1.7
W
0.4
0.03%
Output voltage noise
Feedback resistance
VDD = 2.5 V
VDD = 5 V
VDD = 2.5 V, PO = 200 mW, RL = 8 Ω, f = 1 kHz
VDD = 3.6 V,
f = 20 Hz to 20 kHz,
Inputs ac-grounded with
Ci = 2 µF
RF
1.36
0.02%
VDD = 5 V,
Common mode rejection ratio
TYP
VDD = 5 V, PO = 1 W, RL = 8 Ω, f = 1 kHz
VDD = 3.6 V, PO = 0.5 W, RL = 8 Ω, f = 1 kHz
Signal-to-noise ratio
CMRR
MIN
VDD = 5 V
VDD = 3.6 V
0.02%
f = 217 Hz
−80
f = 20 Hz to 20 kHz
−70
dB
RL = 8 Ω
105
No weighting
15
A weighting
12
f = 217 Hz
−65
dB
µV
VRMS
38
VDD = 3.6 V, CBYPASS = 0.1 µF
40
27
dB
44
kΩ
ms
3
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SLOS429 − MAY 2004
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
PO
Output power
PD
Power dissipation
vs Supply voltage
1
vs Load resistance
2
vs Output power
3
vs Output power
4
vs Frequency
5
THD+N
Total harmonic distortion + noise
vs Common-mode input voltage
6
KSVR
Supply voltage rejection ratio
vs Frequency
7
GSM Power supply rejection
vs Time
8
GSM Power supply rejection
vs Frequency
9
Closed loop gain/phase
vs Frequency
10
Open loop gain/phase
vs Frequency
11
vs Supply voltage
12
vs Shutdown voltage
13
vs Bypass capacitor
14
IDD
Supply current
Start-up time
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
LOAD RESISTANCE
3.5
2.5
2
1.5
PO = 8 Ω, THD 10%
PO = 8 Ω, THD 1%
1
0.5
0
2.5
2.5
VDD = 5 V, THD 10%
VDD = 5 V, THD 1%
VDD = 3.6 V, THD 10%
2
VDD = 3.6 V, THD 1%
VDD = 2.5 V, THD 10%
1.5
VDD = 2.5 V, THD 1%
1
0.5
0
3
3.5
4
4.5
VDD − Supply Voltage − V
Figure 1
4
f = 1 kHz
Gain = 1 V/V
3
Po − Output Power − W
Po − Output Power − W
3
3.5
f = 1 kHz
Gain = 1 V/V
5
8
13
18
23
RL − Load Resistance − Ω
Figure 2
28
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SLOS429 − MAY 2004
POWER DISSIPATION
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
COMMON MODE INPUT VOLTAGE
THD+N − Total Harmonic Distortion + Noise − %
0.8
PD − Power Dissipation − W
8W
5V
0.6
0.4
3.6 V
0.2
0
0
0.2
0.4
0.6 0.8
1
1.2 1.4
PO − Output Power − W
1.6
0.06
0.056
0.052
VDD = 2.5 V
VDD = 5 V
0.048
VDD = 3.6 V
0.044
0.04
1.8
f = 1 kHz
PO = 200 mW,
RL = 1 kHz
0
1
2
3
4
VIC − Common Mode Input Voltage − V
Figure 3
Figure 4
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
5
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
20
10
RL = 8 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
f = 1kHz
2
1
0.5
2.5 V
0.2
3.6 V
0.1
5V
0.05
0.02
0.01
10m 20m
5
10
VDD = 3.6 V,
RL = 8 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
5
2
1
0.5
0.25 W
0.6 W
0.2
0.1 W
0.1
0.05
0.02
0.01
0.005
0.002
0.001
50m 100m 200m
500m 1
PO − Output Power − W
Figure 5
2
20
50
100 200
500 1k 2k
f − Frequency − Hz
5k
10k 20k
Figure 6
5
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SLOS429 − MAY 2004
0
RL = 8 Ω,
C(BYPASS) = 0.47 µF,
Gain = 1 V/V,
CI = 2 µF,
Inputs ac Grounded
−10
−20
−50
−30
−100
−40
VO − Output Voltage − dBV
k SVR − Supply Voltage Rejection Ratio − dB
+0
−50
−60
VDD = 3.6 V
VDD = 2.5 V
−70
−80
−90
VDD = 5 V
−100
20
50
100 200
500 1k
2k
5k
10k 20k
VDD Shown in Figure 9,
RL = 8 Ω,
CI = 2.2 µF,
Inputs Grounded
−100
−150
VDD − Supply Voltage − dBV
GSM POWER SUPPLY REJECTION
vs
FREQUENCY
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
−120
−140
−160
C(BYPASS) = 0.47 µF
−180
0
400
f − Frequency − Hz
Figure 7
800
1200
f − Frequency − Hz
1600
2000
Figure 8
START-UP TIME
vs
BYPASS CAPACITOR
GSM POWER SUPPLY REJECTION
vs
TIME
300
VDD
250
Start-Up Time − ms
Voltage − V
C1
Frequency
217 Hz
C1 − Duty
20%
C1 Pk−Pk
500 mV
200
150
RL = 8 Ω
100
CI = 2.2 µF
C(BYPASS) = 0.47 µF
VOUT
50
2 ms/div
Ch1 100 mV/div
Ch4 10 mV/div
t − Time − ms
Figure 9
6
0
0
0.2
0.4
0.6
0.8
C(Bypass) − Bypass Capacitor − µF
Figure 10
1
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SLOS429 − MAY 2004
CLOSED LOOP GAIN/PHASE
vs
FREQUENCY
OPEN LOOP GAIN/PHASE
vs
FREQUENCY
Phase
30
20
10
100
150
90
120
80
−10
30
−20
0
−30
−30
−40
−60
VDD = 5 V
RL = 8 Ω
Gain = 1
−70
−80
1
10
100
1 k 10 k 100 k
f − Frequency − Hz
1M
120
90
Gain
50
30
30
0
20
−30
−90
−120
−20
−120
−150
−180
−30
−150
10 M
−90
−40
100
1k
10 k
100 k
f − Frequency − Hz
−180
1M
Figure 12
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SHUTDOWN VOLTAGE
10
VDD = 5 V
TA = 125°C
4.5
VDD = 5 V
1
4
I DD − Supply Current − mA
I DD − Supply Current − mA
−60
Phase
0
−10
Figure 11
5
60
40
10
−60
−50
150
60
Phase − Degrees
Gain − dB
60
Gain
180
VDD = 5 V,
RL = 8 Ω
70
90
0
Gain − dB
180
Phase − Degrees
40
TA = 25°C
3.5
3
TA = −40°C
2.5
2
1.5
1
VDD = 3.6 V
0.1
VDD = 2.5 V
0.01
0.001
0.0001
0.5
0
0
0.5
1
1.5 2 2.5 3 3.5 4
VDD − Supply Voltage − V
Figure 13
4.5
5
5.5
0.00001
0
1
2
3
4
5
Voltage on SHUTDOWN Terminal − V
Figure 14
7
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SLOS429 − MAY 2004
APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER
channels equally and cancels at the differential
output. However, removing the bypass capacitor
slightly worsens power supply rejection ratio (kSVR),
but a slight decrease of kSVR may be acceptable when
an additional component can be eliminated.
The TPA6204A1 is a fully differential amplifier with
differential inputs and outputs. The fully differential
amplifier consists of a differential amplifier and a commonmode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage that is equal to the
differential input times the gain. The common-mode
feedback ensures that the common-mode voltage at the
output is biased around VDD/2 regardless of the commonmode voltage at the input.
D
Advantages of Fully Differential Amplifiers
D
D
Input coupling capacitors not required: A fully
differential amplifier with good CMRR, like the
TPA6204A1, allows the inputs to be biased at voltage
other than mid-supply. For example, if a DAC has
mid-supply lower than the mid-supply of the
TPA6204A1, the common-mode feedback circuit
adjusts for that, and the TPA6204A1 outputs are still
biased at mid-supply of the TPA6204A1. The inputs of
the TPA6204A1 can be biased from 0.5 V to VDD −
0.8 V. If the inputs are biased outside of that range,
input coupling capacitors are required.
Better RF-immunity: GSM handsets save power by
turning on and shutting off the RF transmitter at a rate
of 217 Hz. The transmitted signal is picked-up on input
and output traces. The fully differential amplifier
cancels the signal much better than the typical audio
amplifier.
APPLICATION SCHEMATICS
Figure 15 through Figure 17 show application schematics
for differential and single-ended inputs. Typical values are
shown in Table 1.
Table 1. Typical Component Values
Mid-supply bypass capacitor, C(BYPASS), not
required: The fully differential amplifier does not
require a bypass capacitor. This is because any shift
in the mid- supply affects both positive and negative
COMPONENT
VALUE
RI
C(BYPASS)(1)
CS
0.22 µF
CI
(1) C(BYPASS) is optional
VDD 6
Cs
40 kΩ
In From
DAC
− RI
4
IN−
+ RI
3
IN+
To Battery
_
+
40 kΩ
VO+ 5
VO− 8
GND 7
2
SHUTDOWN
1
C(BYPASS)(1)
Bias
Circuitry
100 kΩ
(1) C(BYPASS) is optional
Figure 15. Typical Differential Input Application Schematic
8
40 kΩ
1 µF
0.22 µF
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SLOS429 − MAY 2004
VDD 6
CI
Cs
40 kΩ
−
RI
4
IN−
+
RI
3
IN+
CI
To Battery
_
+
40 kΩ
VO+ 5
VO− 8
GND 7
2
Bias
Circuitry
1
SHUTDOWN
C(BYPASS)(1)
100 kΩ
(1) C(BYPASS) is optional
Figure 16. Differential Input Application Schematic Optimized With Input Capacitors
VDD 6
CI
IN
Cs
40 kΩ
RI
4
IN−
RI
3
IN+
CI
To Battery
_
+
40 kΩ
VO+ 5
VO− 8
GND 7
2
SHUTDOWN
C(BYPASS)(1)
1
Bias
Circuitry
100 kΩ
(1) C(BYPASS) is optional
(2) Due to the fully differential design of this amplifier, the
performance is severly degraded if you connect the unused
input to BYPASS when using single-ended inputs.
Figure 17. Single-Ended Input Application Schematic
9
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SLOS429 − MAY 2004
SELECTING COMPONENTS
Resistors (RI )
The input resistor (RI) can be selected to set the gain of the
amplifier according to equation 1.
Gain = RF/RI
(1)
The internal feedback resistors (RF) are trimmed to 40 kΩ.
−3 dB
Resistor matching is very important in fully differential
amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors.
CMRR, PSRR, and the cancellation of the second
harmonic distortion diminishes if resistor mismatch
occurs. Therefore, it is recommended to use 1% tolerance
resistors or better to keep the performance optimized.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this
applications section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal
capacitor. The voltage drop across this resistor minimizes
the beneficial effects of the capacitor in the circuit. The
lower the equivalent value of this resistance the more the
real capacitor behaves like an ideal capacitor.
Bypass Capacitor (CBYPASS ) and Start-Up Time
The internal voltage divider at the BYPASS pin of this
device sets a mid-supply voltage for internal references
and sets the output common mode voltage to VDD/2.
Adding a capacitor to this pin filters any noise into this pin
and increases kSVR. C(BYPASS) also determines the rise
time of VO+ and VO− when the device is taken out of
shutdown. The larger the capacitor, the slower the rise
time. NO TAGNO TAGNO TAGNO TAGNO TAG show
the relationship of C(BYPASS) to start-up time.
Input Capacitor (CI )
The TPA6204A1 does not require input coupling
capacitors if using a differential input source that is biased
from 0.5 V to VDD − 0.8 V. Use 1% tolerance or better
gain-setting resistors if not using input coupling capacitors.
In the single-ended input application an input capacitor, CI,
is required to allow the amplifier to bias the input signal to
the proper dc level. In this case, CI and RI form a high-pass
filter with the corner frequency determined in equation 2.
fc +
10
1
2p R C
I I
(2)
fc
The value of CI is important to consider as it directly affects
the bass (low frequency) performance of the circuit.
Consider the example where RI is 10 kΩ and the
specification calls for a flat bass response down to 100 Hz.
Equation 2 is reconfigured as equation 3.
1
C +
I
2p R f c
I
(3)
In this example, CI is 0.16 µF, so one would likely choose
a value in the range of 0.22 µF to 0.47 µF. Ceramic
capacitors should be used when possible, as they are the
best choice in preventing leakage current. When polarized
capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications, as the
dc level there is held at VDD/2, which is likely higher than
the source dc level. It is important to confirm the capacitor
polarity in the application.
Decoupling Capacitor (CS )
The TPA6204A1 is a high-performance CMOS audio
amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as
low as possible. Power supply decoupling also prevents
oscillations for long lead lengths between the amplifier and
the speaker. For higher frequency transients, spikes, or
digital hash on the line, a good low equivalent-seriesresistance (ESR) ceramic capacitor, typically 0.1 µF to
1 µF, placed as close as possible to the device VDD lead
works best. For filtering lower frequency noise signals, a
10-µF or greater capacitor placed near the audio power
amplifier also helps, but is not required in most
applications because of the high PSRR of this device.
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SLOS429 − MAY 2004
VO
FULLY DIFFERENTIAL AMPLIFIER
EFFICIENCY AND THERMAL INFORMATION
Class-AB amplifiers are inefficient. The primary cause of
these inefficiencies is voltage drop across the output stage
transistors. There are two components of the internal
voltage drop. One is the headroom or dc voltage drop that
varies inversely to output power. The second component
is due to the sinewave nature of the output. The total
voltage drop can be calculated by subtracting the RMS
value of the output voltage from VDD. The internal voltage
drop multiplied by the average value of the supply current,
IDD(avg), determines the internal power dissipation of the
amplifier.
An easy-to-use equation to calculate efficiency starts out
as being equal to the ratio of power from the power supply
to the power delivered to the load. To accurately calculate
the RMS and average values of power in the load and in
the amplifier, the current and voltage waveform shapes
must first be understood (see Figure 18).
Efficiency of a BTL amplifier +
P
P
V(LRMS)
IDD
IDD(avg)
Figure 18. Voltage and Current Waveforms for
BTL Amplifiers
Although the voltages and currents for SE and BTL are
sinusoidal in the load, currents from the supply are
different between SE and BTL configurations. In an SE
application the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform.
This means RMS conversion factors are different. Keep in
mind that for most of the waveform both the push and pull
transistors are not on at the same time, which supports the
fact that each amplifier in the BTL device only draws
current from the supply for half the waveform. The
following equations are the basis for calculating amplifier
efficiency.
(4)
L
SUP
Where:
2
V rms 2
V
V
P + L
, and V
+ P , therefore, P + P
L
LRMS
L
Ǹ
R
2R
2
L
L
1
and P SUP + V DD I DDavg and I DDavg + p
ŕ
p V
P sin(t) dt + * 1
p
R
0
L
2V
P
P [cos(t)] p+
0 pR
R
L
L
V
Therefore,
P
SUP
+
2V
V
DD P
pR
L
substituting PL and PSUP into equation 6,
2
Efficiency of a BTL amplifier +
Where:
V
P
+
Ǹ2 PL RL
Therefore,
h BTL +
VP
2 RL
2 V DD V P
p RL
+
p VP
4 VDD
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the
power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
(5)
p
Ǹ2 PL RL
4V
DD
11
www.ti.com
SLOS429 − MAY 2004
Table 2 and Table 3 employ equation (5) to calculate
efficiencies for four different output power levels. Note that
the efficiency of the amplifier is quite low for lower power
levels and rises sharply as power to the load is increased
resulting in a nearly flat internal power dissipation over the
normal operating range. Note that the internal dissipation
at full output power is less than in the half power range.
Calculating the efficiency for a specific system is the key
to proper power supply design. For a 1-W audio system
with 8-Ω loads and a 5-V supply, the maximum draw on the
power supply is almost 1.6 W.
A final point to remember about Class-AB amplifiers is how
to manipulate the terms in the efficiency equation to the
utmost advantage when possible.
A simple formula for calculating the maximum power
dissipated, PDmax, may be used for a differential output
application:
P Dmax +
Θ
JA
+
1
1
+
+ 45.9°CńW
0.0218
Derating Factor
(7)
Given ΘJA, the maximum allowable junction temperature,
and the maximum internal dissipation, the maximum
ambient temperature can be calculated with the following
equation. The maximum recommended junction
temperature for the TPA6204A1 is 150°C.
T A Max + T J Max * ΘJA P Dmax
(8)
+ 150 * 45.9(0.64) + 120.6°C
Equation (8) shows that the maximum ambient
temperature is 120.6°C (package limited to 85°C) at
maximum power dissipation with a 5-V supply.
2V2
DD
p 2R L
(6)
PDmax for a 5-V, 8-Ω system is 0.64 W.
The maximum ambient temperature depends on the heat
sinking ability of the PCB system. The derating factor for
the 3 mm x 3 mm DRB package is shown in the dissipation
rating table. Converting this to ΘJA:
Table 2 shows that for most applications no airflow is
required to keep junction temperatures in the specified
range. The TPA6204A1 is designed with thermal
protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the
IC. In addition, using speakers with an impedance higher
than 8-Ω dramatically increases the thermal performance
by reducing the output current.
Table 2. Efficiency and Maximum Ambient Temperature vs Output Power in 3.6-V 8-Ω BTL Systems
Output Power
(W)
Efficiency
(%)
Internal Dissipation
(W)
Power From Supply
(W)
Max Ambient Temperature (2)
(°C)
0.1
27.6
0.262
0.36
85
0.2
39.0
0.312
0.51
85
0.5
61.7
0.310
0.81
85
0.6
67.6
0.288
0.89
85
(1) DRB package
(2) Package limited to 85°C ambient
Table 3. Efficiency and Maximum Ambient Temperature vs Output Power in 5-V 8-Ω Systems
Output Power
(W)
Efficiency
(%)
Internal Dissipation
(W)
Power From Supply
(W)
Max Ambient Temperature (2)
(°C)
0.5
44.4
0.625
1.13
85
1
62.8
0.592
1.60
85
1.36
73.3
0.496
1.86
85
1.7
81.9
0.375
2.08
85
(1) DRB package
(2) Package limited to 85°C ambient
12
www.ti.com
SLOS429 − MAY 2004
PCB LAYOUT
It is important to keep the TPA6204A1 external components very close to the TPA6204A1 to limit noise pickup.
8-Pin QFN (DRB) Layout
Use the following land pattern for board layout with the 8-pin QFN (DRB) package. Note that the solder paste should use
a hatch pattern to fill solder paste at 50% to ensure that there is not too much solder paste under the package.
0.7 mm
0.33 mm plugged vias (5 places)
1.4 mm
0.38 mm
0.65 mm
1.95 mm
Solder Mask: 1.4 mm x 1.85 mm centered in package
Make solder paste a hatch pattern to fill 50%
3.3 mm
Figure 19. TPA6204A1 8-Pin QFN (DRB) Board Layout (Top View)
13
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