ZQV DRB TPA6205A1 DGN www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER WITH 1.8-V INPUT LOGIC THRESHOLDS FEATURES APPLICATIONS • • • • • • • • • 1.25 W Into 8Ω From a 5-V Supply at THD = 1% (Typical) Shutdown Pin has 1.8V Compatible Thresholds Low Supply Current: 1.7mA Typical Shutdown Current < 10µA Only Five External Components – Improved PSRR (90 dB) and Wide Supply Voltage (2.5V to 5.5V) for Direct Battery Operation – Fully Differential Design Reduces RF Rectification – Improved CMRR Eliminates Two Input Coupling Capacitors – C(BYPASS) Is Optional Due to Fully Differential Design and High PSRR Available in 3 mm x 3 mm QFN Package (DRB) Available in an 8-Pin PowerPAD™ MSOP (DGN) Avaliable in a 2 mm x 2 mm MicroStar Junior™ BGA Package (ZQV) • Designed for Wireless Handsets, PDAs, and other mobile devices Compatible with Low Power (1.8V Logic) I/O Threshold control signals DESCRIPTION The TPA6205A1 is a 1.25-W mono fully differential amplifier designed to drive a speaker with at least 8-Ω impedance while consuming less than 37 mm2 (ZQV package option) total printed-circuit board (PCB) area in most applications. This device operates from 2.5 V to 5.5 V, drawing only 1.7 mA of quiescent supply current. The TPA6205A1 is available in the space-saving 2 mm x 2 mm MicroStar Junior™ BGA package, and the space saving 3 mm x 3 mm QFN (DRB) package. Features like 85-dB PSRR from 90 Hz to 5 kHz, improved RF-rectification immunity, and small PCB area makes the TPA6205A1 ideal for wireless handsets. A fast start-up time of 4 µs with minimal pop makes the TPA6205A1 ideal for PDA applications. APPLICATION CIRCUIT In From DAC RI + RI ININ+ To Battery RF Cs _ VO+ CS (1)C B VO+ RF SHUTDOWN Actual Solution Size VDD RF GND Bias Circuitry C(BYPASS) (Optional) 5,25 mm RI RI RF 6,9 mm Applies to the ZQV Packages Only Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD, MicroStar Junior are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGED DEVICES (1) (2) MicroStar Junior™ (ZQV) QFN (DRB) MSOP (DGN) Device TPA6205A1ZQVR TPA6205A1DRB TPA6205A1DGN Symbolization AANI AAOI AAPI (1) (2) The ZQV packages are only available taped and reeled. The suffix R designates taped and reeled parts. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT VDD Supply voltage VI Input voltage –0.3 V to 6 V INx and SHUTDOWN pins –0.3 V to VDD + 0.3 V Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature –40°C to 85°C TJ Junction temperature –40°C to 125°C Tstg Storage temperature –65°C to 85°C Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds (1) ZQV, DRB, DGN 260°C Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN VDD Supply voltage VIH High-level input voltage SHUTDOWN VIL Low-level input voltage SHUTDOWN VIC Common-mode input voltage VDD = 2.5 V, 5.5 V, CMRR ≤– 60 dB TA ZL TYP 2.5 MAX 5.5 1.15 UNIT V V 0.50 V 0.5 VDD–0.8 V Operating free-air temperature –40 85 °C Load impedance 6.4 Ω 8 DISSIPATION RATINGS 2 PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR TA = 70°C POWER RATING TA = 85°C POWER RATING ZQV 885 mW 8.8 mW/°C 486 mW 354 mW DGN 2.13 W 17.1 mW/°C 1.36 W 1.11 W DRB 2.7 W 21.8 mW/°C 1.7 W 1.4 W Submit Documentation Feedback TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS TA = 25°C, Gain = 1 V/V PARAMETER TEST CONDITIONS MIN |VOO| Output offset voltage (measured differentially) VI = 0 V, VDD = 2.5 V to 5.5 V PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V VDD = 3.6 V to 5.5 V, VIC = 0.5 V to VDD–0.8 VDD = 2.5 V, VIC = 0.5 V to 1.7 V CMRR Common-mode rejection ratio VOL Low-level output voltage VOH High-level output voltage RL = 8 Ω, VIN+ = VDD, VIN– = 0 V or VIN+ = 0 V, VIN– = VDD RL = 8 Ω, VIN+ = VDD, VIN– = 0 V or VIN+ = 0 V, VIN– = VDD TYP MAX UNIT 9 mV –90 –70 dB –70 –65 –62 –55 VDD = 5.5 V 0.30 0.46 VDD = 3.6 V 0.22 VDD = 2.5 V 0.19 VDD = 5.5 V 4.8 VDD = 3.6 V VDD = 2.5 V V 0.26 5.12 3.28 2.1 dB V 2.24 1.2 µA |IIH| High-level input current VDD = 5.5 V, VI = 5.8 V |IIL| Low-level input current VDD = 5.5 V, VI = –0.3 V 1.2 µA IDD Supply current VDD = 2.5 V to 5.5 V, No load, SHUTDOWN = VIH 1.7 2 mA IDD(SD) Supply current in shutdown mode SHUTDOWN = VIL , VDD = 2.5 V to 5.5 V, No load 0.01 0.9 µA OPERATING CHARACTERISTICS TA = 25°C, Gain = 1 V/V, RL = 8 Ω PARAMETER PO THD+N Output power Total harmonic distortion plus noise TEST CONDITIONS THD + N = 1%, f = 1 kHz SNR TYP VDD = 5 V 1.25 VDD = 3.6 V 0.63 VDD = 2.5 V 0.3 VDD = 5 V, PO = 1 W, f = 1 kHz 0.06% VDD = 3.6 V, PO = 0.5 W, f = 1 kHz 0.07% VDD = 2.5 V, PO = 200 mW, f = 1 kHz 0.08% C(BYPASS) = 0.47°F, VDD = 3.6 V to 5.5 V, Inputs ac-grounded with CI = 2 µF kSVR MIN f = 217 Hz to 2 kHz, VRIPPLE = 200 mVPP -87 Supply ripple rejection C(BYPASS) = 0.47 µF, VDD = 2.5 V to 3.6 V, ratio Inputs ac-grounded with CI = 2 µF f = 217 Hz to 2 kHz, VRIPPLE = 200 mVPP -82 C(BYPASS) = 0.47 µF, VDD = 2.5 V to 5.5 V, Inputs ac-grounded with CI = 2 µF f = 40 Hz to 20 kHz, VRIPPLE = 200 mVPP ≤–74 Signal-to-noise ratio VDD = 5 V, PO= 1 W Vn Output voltage noise f = 20 Hz to 20 kHz CMRR Common-mode rejection ratio VDD = 2.5 V to 5.5 V, Resistor tolerance = 0.1%, Gain = 4V/V, VICM = 200 mVPP ZI Input impedance ZO Output impedance Shutdown mode Shutdown attenuation f = 20 Hz to 20 kHz, RF = RI = 20 kΩ 104 No weighting 17 A weighting 13 f = 20 Hz to 1 kHz ≤–85 f = 20 Hz to 20 kHz ≤–74 MAX UNIT W dB dB µVRMS dB 2 MΩ -80 dB >10k Submit Documentation Feedback 3 TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 MicroStar Junior™ (ZQV) PACKAGE (TOP VIEW) GND 1 2 3 A B C VOSHUTDOWN BYPASS VDD VO+ ININ+ (SIDE VIEW) 8-PIN QFN (DRB) PACKAGE (TOP VIEW) SHUTDOWN 1 8 V O- BYPASS 2 7 GND IN+ 3 6 VDD IN- 4 5 VO+ 8-PIN MSOP (DGN) PACKAGE (TOP VIEW) VO- SHUTDOWN 1 8 BYPASS 2 7 GND IN+ 3 6 VDD IN- 4 5 VO+ Terminal Functions TERMINAL ZQV DRB, DGN I/O C1 2 I Mid-supply voltage. Adding a bypass capacitor improves PSRR. GND B2 7 I High-current ground IN- C3 4 I Negative differential input IN+ C2 3 I Positive differential input SHUTDOWN B1 1 I Shutdown terminal (active low logic) VDD A3 6 I Supply voltage terminal VO+ B3 5 O Positive BTL output A1 8 O Negative BTL output NAME BYPASS VOThermal Pad 4 N/A DESCRIPTION Connect to ground. Thermal pad must be soldered down in all applications to properly secure device on the PCB. Submit Documentation Feedback TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Supply voltage 1 vs Load resistance 2, 3 Power dissipation vs Output power 4, 5 Maximum ambient temperature vs Power dissipation PO Output power PD vs Output power Total harmonic distortion + noise vs Frequency vs Common-mode input voltage CMRR IDD 6 7, 8 9, 10, 11, 12 13 Supply voltage rejection ratio vs Frequency Supply voltage rejection ratio vs Common-mode input voltage 18 GSM Power supply rejection vs Time 19 GSM Power supply rejection vs Frequency 20 vs Frequency 21 vs Common-mode input voltage 22 Closed loop gain/phase vs Frequency 23 Open loop gain/phase vs Frequency 24 Supply current vs Supply voltage 25 Start-up time vs Bypass capacitor 26 Common-mode rejection ratio Submit Documentation Feedback 14, 15, 16, 17 5 TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 TYPICAL CHARACTERISTICS OUTPUT POWER vs SUPPLY VOLTAGE OUTPUT POWER vs LOAD RESISTANCE 1.8 THD+N = 10% 1 0.8 0.6 THD+N = 1% 0.4 0.4 0 0 3.5 4 4.5 5 VDD = 2.5 V 0.6 0.2 3 VDD = 3.6 V 0.8 0.2 2.5 0.8 VDD = 2.5 V 0.6 0.4 13 18 23 28 8 32 13 18 23 RL - Load Resistance - Ω RL - Load Resistance - Ω 28 Figure 1. Figure 2. Figure 3. POWER DISSIPATION vs OUTPUT POWER POWER DISSIPATION vs OUTPUT POWER MAXIMUM AMBIENT TEMPERATURE vs POWER DISSIPATION 0.6 PD - Power Dissipation - W 8Ω 0.3 0.25 0.2 0.15 16 Ω 0.1 0.05 Maximum Ambient Temperature - oC VDD = 5 V 0.35 8Ω 0.5 0.4 0.3 16 Ω 0.2 0.1 0 0 0.2 0.4 0.6 0.8 32 90 0.7 VDD = 3.6 V 80 70 60 50 40 30 ZQV Package Only 20 10 0 0 0.2 PO - Output Power - W 0.4 0.6 0.8 1 1.2 0 1.4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 PD - Power Dissipation - W PO - Output Power - W Figure 5. Figure 6. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 5 2.5 V 2 3.6 V 1 0.5 5V 0.2 0.1 0.05 0.02 RL = 8 Ω, f = 1 kHz C(Bypass) = 0 to 1 µF Gain = 1 V/V 0.01 10 m 100 m 1 2 3 THD+N - Total Harmonic Distortion + Noise - % Figure 4. 10 5 2 RL = 16 Ω f = 1 kHz C(Bypass) = 0 to 1 µF Gain = 1 V/V 1 0.5 0.2 2.5 V 5V 3.6 V 0.1 0.05 0.02 0.01 10 m 100 m PO - Output Power - W PO - Output Power - W Figure 7. Figure 8. 1 Submit Documentation Feedback 2 THD+N - Total Harmonic Distortion + Noise - % PD - Power Dissipation - W VDD = 3.6 V 1 0 8 0.4 0 VDD = 5 V 1.2 0.2 VDD - Supply Voltage - V THD+N - Total Harmonic Distortion + Noise - % 1.4 VDD = 5 V 1 f = 1 kHz THD+N = 10% Gain = 1 V/V 1.6 PO - Output Power - W 1.2 f = 1 kHz THD+N = 1% Gain = 1 V/V 1.2 PO - Output Power - W 1.4 PO - Output Power - W 1.8 1.4 RL = 8 Ω f = 1 kHz Gain = 1 V/V 1.6 6 OUTPUT POWER vs LOAD RESISTANCE 10 5 0.5 VDD = 5 V CI = 2 µF RL = 8 Ω C(Bypass) = 0 to 1 µF Gain = 1 V/V 0.2 250 mW 2 1 50 mW 0.1 0.05 0.02 1W 0.01 0.005 0.002 0.001 20 100 200 1k 2k f - Frequency - Hz Figure 9. 10 k 20 k TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 TYPICAL CHARACTERISTICS (continued) 1 0.5 25 mW 0.2 0.1 125 mW 0.05 0.02 500 mW 0.01 0.005 0.002 0.001 20 50 100 200 500 1 k 2 k f - Frequency - Hz 5 k 10 k 20 k 10 5 VDD = 2.5 V CI = 2 µF RL = 8 Ω C(Bypass) = 0 to 1 µF Gain = 1 V/V 2 1 0.5 15 mW 0.2 0.1 75 mW 0.05 0.02 200 mW 0.01 0.005 0.002 0.001 20 50 100 200 500 1 k 2 k f - Frequency - Hz 5 k 10 k 20 k TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % 2 10 5 VDD = 3.6 V CI = 2 µF RL = 16 Ω C(Bypass) = 0 to 1 µF Gain = 1 V/V 2 1 0.5 0.2 25 mW 125 mW 0.1 0.05 0.02 0.01 250 mW 0.005 0.002 0.001 20 50 100 200 500 1 k 2 k f - Frequency - Hz 5 k 10 k 20 k Figure 12. TOTAL HARMONIC DISTORTION + NOISE vs COMMON MODE INPUT VOLTAGE SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY f = 1 kHz PO = 200 mW 1 VDD = 2.5 V 0.10 k VDD = 3.6 V 0.01 0 0 CI = 2 µF RL = 8 Ω C(Bypass) = 0.47 µF Vp-p = 200 mV Inputs ac-Grounded Gain = 1 V/V -10 -20 -30 -40 -50 -60 VDD =2. 5 V -70 VDD = 5 V -80 -90 VDD = 3.6 V -100 20 0.5 1 1.5 2 2.5 3 3.5 VIC - Common Mode Input Voltage - V k 10 - Supply Voltage Rejection Ratio - dB SVR Figure 11. - Supply Voltage Rejection Ratio - dB SVR Figure 10. 50 100 200 500 1 k 2 k 0 Gain = 5 V/V CI = 2 µF RL = 8 Ω C(Bypass) = 0.47 µF Vp-p = 200 mV Inputs ac-Grounded -10 -20 -30 -40 -50 VDD =2. 5 V -60 VDD = 5 V -70 -80 VDD = 3.6 V -90 -100 5 k 10 k 20 k 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k f - Frequency - Hz Figure 13. Figure 14. Figure 15. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY SUPPLY VOLTAGE REJECTION RATIO vs COMMON MODE INPUT VOLTAGE -20 -30 -40 -50 VDD =2. 5 V -60 VDD = 5 V -70 VDD = 3.6 V -80 -90 -100 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k 0 VDD = 3.6 V CI = 2 µF RL = 8 Ω Inputs ac-Grounded Gain = 1 V/V -10 -20 -30 -40 C(Bypass) = 0.47 µF -50 -60 C(Bypass) = 0 C(Bypass) = 1 µF -70 C(Bypass) = 0.1 µF -80 SVR CI = 2 µF RL = 8 Ω Inputs Floating Gain = 1 V/V -90 -100 k - Supply Voltage Rejection Ratio - dB SVR 0 -10 - Supply Voltage Rejection Ratio - dB f - Frequency - Hz k - Supply Voltage Rejection Ratio - dB SVR k VDD = 3.6 V CI = 2 µF RL = 8 Ω C(Bypass) = 0 to 1 µF Gain = 1 V/V TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % 10 5 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 20 50 100 200 500 1 k 2 k f - Frequency - Hz f - Frequency - Hz Figure 16. Figure 17. 5 k 10 k 20 k Submit Documentation Feedback -10 f = 217 Hz C(Bypass) = 0.47 µF RL = 8 Ω Gain = 1 V/V -20 -30 VDD = 2.5 V -40 VDD = 3.6 V -50 -60 -70 -80 VDD = 5 V -90 0 1 2 3 4 VIC - Common Mode Input Voltage - V 5 Figure 18. 7 TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 TYPICAL CHARACTERISTICS (continued) GSM POWER SUPPLY REJECTION vs FREQUENCY 0 C1 Frequency 217.41 Hz -50 C1 - Duty 20 % -100 VO - Output Voltage - dBV Voltage - V VDD C1 High 3.598 V C1 Pk-Pk 504 mV VO Ch1 100 mV/div Ch4 10 mV/div t - Time - ms 2 ms/div 0 -150 VDD Shown in Figure 19 CI = 2 µF, C(Bypass) = 0.47 µF, Inputs ac-Grounded Gain = 1V/V -50 -100 -150 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k CMRR - Common Mode Rejection Ratio - dB COMMON MODE REJECTION RATIO vs FREQUENCY V DD - Supply Voltage - dBV GSM POWER SUPPLY REJECTION vs TIME 0 VDD = 2.5 V to 5 V VIC = 200 mVp-p RL = 8 Ω Gain = 1 V/V -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 f - Frequency - Hz 50 100 200 500 1 k 2 k 5 k 10 k 20 k Figure 19. Figure 20. Figure 21. COMMON MODE REJECTION RATIO vs COMMON MODE INPUT VOLTAGE CLOSED LOOP GAIN/PHASE vs FREQUENCY OPEN LOOP GAIN/PHASE vs FREQUENCY 180 20 10 -30 VDD = 2.5 V -50 60 20 -10 -20 -20 -30 -60 -70 -40 -100 -80 -50 VDD = 5 V -60 VDD = 3.6 V -100 0 0.5 1 1.5 2 2.5 3 3.5 4 100 4.5 5 100 Gain 50 50 0 0 -50 -50 Phase -100 -180 -150 -150 -220 10 M -200 -140 -70 10 10 k 1k 100 k 1 M 100 1k f - Frequency - Hz Figure 22. Figure 23. START-UP TIME(1) vs BYPASS CAPACITOR 6 1.8 1.6 5 Start-Up Time - ms 1.4 1.2 1 0.8 4 3 2 0.6 1 0.4 0 0.2 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VDD - Supply Voltage - V 0.5 1 1.5 C(Bypass) - Bypass Capacitor - µF 2 5.5 (1) 100 k Figure 24. SUPPLY CURRENT vs SUPPLY VOLTAGE I DD - Supply Current - mA 10 k f - Frequency - Hz VIC - Common Mode Input Voltage - V Start-Up time is the time it takes (from a low-to-high transition on SHUTDOWN) for the gain of the amplifier to reach -3 dB of the final gain. Figure 25. 8 150 100 -100 VDD = 3.6 V RL = 8 Ω Gain = 1 V/V -60 -90 150 100 Gain 0 -40 200 VDD = 3.6 V RL = 8 Ω 140 Gain - dB -20 200 220 Phase 30 Phase - Degrees RL = 8 Ω Gain = 1 V/V Submit Documentation Feedback Figure 26. 1M -200 10 M Phase - Degrees 40 0 -10 Gain - dB CMRR - Common Mode Rejection Ratio - dB f - Frequency - Hz TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 APPLICATION INFORMATION • Mid-supply bypass capacitor, C(BYPASS), not required: The fully differential amplifier does not require a bypass capacitor. This is because any shift in the mid-supply affects both positive and negative channels equally and cancels at the differential output. However, removing the bypass capacitor slightly worsens power supply rejection ratio (kSVR), but a slight decrease of kSVR may be acceptable when an additional component can be eliminated (see Figure 17). Better RF-immunity: GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal much better than the typical audio amplifier. FULLY DIFFERENTIAL AMPLIFIER The TPA6205A1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier consists of a differential amplifier and a common- mode amplifier. The differential amplifier ensures that the amplifier outputs a differential voltage that is equal to the differential input times the gain. The common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the common- mode voltage at the input. • Advantages of Fully Differential Amplifiers • Input coupling capacitors not required: A fully differential amplifier with good CMRR, like the TPA6205A1, allows the inputs to be biased at voltage other than mid-supply. For example, if a DAC has mid-supply lower than the mid-supply of the TPA6205A1, the common-mode feedback circuit adjusts for that, and the TPA6205A1 outputs are still biased at mid-supply of the TPA6205A1. The inputs of the TPA6205A1 can be biased from 0.5 V to VDD - 0.8 V. If the inputs are biased outside of that range, input coupling capacitors are required. APPLICATION SCHEMATICS Figure 27 through Figure 31 show application schematics for differential and single-ended inputs. Typical values are shown in Table 1. Table 1. Typical Component Values COMPONENT VALUE RI 10 kΩ RF 10 kΩ C(BYPASS)(1) 0.22 µF CS 1 µF CI 0.22 µF (1) C(BYPASS) is optional VDD RF In From DAC - RI IN- + RI IN+ Cs _ VO+ VO- + RF SHUTDOWN To Battery GND Bias Circuitry C(BYPASS) (Optional) Figure 27. Typical Differential Input Application Schematic Submit Documentation Feedback 9 TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 VDD RF CI IN + RI IN- RI IN+ CI To Battery Cs _ VO+ VO- + RF GND SHUTDOWN Bias Circuitry C(BYPASS) (Optional) Figure 28. Differential Input Application Schematic Optimized With Input Capacitors VDD RF CI RI IN- IN RI CI IN+ To Battery Cs _ VO+ VO- + RF GND SHUTDOWN Bias Circuitry C(BYPASS) (Optional) Figure 29. Single-Ended Input Application Schematic Differential Input 2 Differential Input 1 - CI2 RI2 + CI2 RI2 VDD RF - CI1 RI1 IN- + CI1 RI1 IN+ _ VO+ VO- + RF SHUTDOWN To Battery CS GND Bias Circuitry C(BYPASS) (Optional) Figure 30. Application Schematic With TPA6205A1 Summing Two Differetial Inputs 10 Submit Documentation Feedback TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 CI2 Single Ended Input 2 CI1 Single Ended Input 1 RI2 RI1 IN- RP CP VDD RF IN+ To Battery Cs _ VO+ VO- + RF GND SHUTDOWN Bias Circuitry C(BYPASS) (Optional) Figure 31. Application Schematic With TPA6205A1 Summing Two Single-Ended Inputs Input Capacitor (CI) SELECTING COMPONENTS Resistors (RF and RI) The input (RI) and feedback resistors (RF) set the gain of the amplifier according to Equation 1. Gain − RF/RI (1) RF and RI should range from 1 kΩ to 100 kΩ. Most graphs were taken with RF = RI = 20 kΩ. Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and the cancellation of the second harmonic distortion diminishes if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. The TPA6205A1 does not require input coupling capacitors if using a differential input source that is biased from 0.5 V to VDD - 0.8 V. Use 1% tolerance or better gain-setting resistors if not using input coupling capacitors. In the single-ended input application an input capacitor, CI, is required to allow the amplifier to bias the input signal to the proper dc level. In this case, CI and RI form a high-pass filter with the corner frequency determined in Equation 2. 1 fc + 2pR C I I (2) –3 dB Bypass Capacitor (CBYPASS) and Start-Up Time The internal voltage divider at the BYPASS pin of this device sets a mid-supply voltage for internal references and sets the output common mode voltage to VDD/2. Adding a capacitor to this pin filters any noise into this pin and increases the kSVR. C(BYPASS)also determines the rise time of VO+ and VOwhen the device is taken out of shutdown. The larger the capacitor, the slower the rise time. Although the output rise time depends on the bypass capacitor value, the device passes audio 4 µs after taken out of shutdown and the gain is slowly ramped up based on C(BYPASS). To minimize pops and clicks, design the circuit so the impedance (resistance and capacitance) detected by both inputs, IN+ and IN-, is equal. fc The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit. Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to 100 Hz. Equation 2 is reconfigured as Equation 3. 1 C + I 2pR f c I (3) In this example, CI is 0.16 µF, so one would likely choose a value in the range of 0.22 µF to 0.47 µF. A further consideration for this capacitor is the leakage path from the input source through the input network (RI, CI) and the feedback resistor (RF) to the load. Submit Documentation Feedback 11 TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications, as the dc level there is held at VDD/2, which is likely higher than the source dc level. It is important to confirm the capacitor polarity in the application. Decoupling Capacitor (CS) The TPA6205A1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series- resistance (ESR) ceramic capacitor, typically 0.1 µF to 1 µF, placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a 10-µF or greater capacitor placed near the audio power amplifier also helps, but is not required in most applications because of the high PSRR of this device. SUMMING INPUT SIGNALS WITH THE TPA6205A1 Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources that need separate gain. The TPA6205A1 makes it easy to sum signals or use separate signal sources with different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo headphones require summing of the right and left channels to output the stereo signal to the mono speaker. Summing Two Differential Input Signals Two extra resistors are needed for summing differential signals (a total of 10 components). The gain for each input source can be set independently (see Equation 4 and Equation 5, and Figure 30). V R Gain 1 + O + * F V V I1 R I1 V (4) ǒǓ Gain 2 + 12 VO V I2 +* RF V R I2 V ǒǓ Summing a Differential Input Signal and a Single-Ended Input Signal Figure 31 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple in through IN+ with this method. It is better to use differential inputs. To assure that each input is balanced, the single-ended input must be driven by a low-impedance source even if the input is not in use. Both input nodes must see the same impedance for optimum performance, thus the use of RP and CP. V R Gain 1 + O + * F V V I1 R I1 V (6) ǒǓ Gain 2 + VO V I2 +* RF ǒǓ V R I2 V (7) Where CP = CI1 // CI2 RP = RI1 // RI2 USING LOW-ESR CAPACITORS Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor. DIFFERENTIAL OUTPUT VERSUS SINGLE-ENDED OUTPUT Figure 32 shows a Class-AB audio power amplifier (APA) in a fully differential configuration. The TPA6205A1 amplifier has differential outputs driving both ends of the load. There are several potential benefits to this differential drive configuration, but initially consider power to the load. The differential drive to the speaker means that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the voltage swing on the load as compared to a ground referenced load. Plugging 2 × VO(PP) into the power equation, where voltage is squared, yields 4× the output power from the same supply rail and load impedance (see Equation 8). (5) Submit Documentation Feedback TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 V V (rms) + V Power + fc + O(PP) 2 Ǹ2 2 (rms) R L (8) VDD 1 2pR C L C (9) For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency performance is then limited only by the input network and speaker response. Cost and PCB space are also minimized by eliminating the bulky coupling capacitor. VDD VO(PP) VO(PP) RL CC 2x VO(PP) RL VDD –VO(PP) VO(PP) –3 dB Figure 32. Differential Output Configuration In a typical wireless handset operating at 3.6 V, bridging raises the power into an 8-Ω speaker from a singled-ended (SE, ground reference) limit of 200 mW to 800 mW. In sound power that is a 6-dB improvement—which is loudness that can be heard. In addition to increased power there are frequency response concerns. Consider the single-supply SE configuration shown in Figure 33. A coupling capacitor is required to block the dc offset voltage from reaching the load. This capacitor can be quite large (approximately 33 µF to 1000 µF) so it tends to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system. This frequency-limiting effect is due to the high pass filter network created with the speaker impedance and the coupling capacitance and is calculated with Equation 9. fc Figure 33. Single-Ended Output and Frequency Response Increasing power to the load does carry a penalty of increased internal power dissipation. The increased dissipation is understandable considering that the BTL configuration produces 4× the output power of the SE configuration. FULLY DIFFERENTIAL AMPLIFIER EFFICIENCY AND THERMAL INFORMATION Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output stage transistors. There are two components of the internal voltage drop. One is the headroom or dc voltage drop that varies inversely to output power. The second component is due to the sinewave nature of the output. The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The internal voltage drop multiplied by the average value of the supply current, IDD(avg), determines the internal power dissipation of the amplifier. Submit Documentation Feedback 13 TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 34). VO V(LRMS) Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different. Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform. The following equations are the basis for calculating amplifier efficiency. IDD IDD(avg) Figure 34. Voltage and Current Waveforms for BTL Amplifiers P L Efficiency of a BTL amplifier + P SUP where: 2 V rms 2 V V L P P P + , and V + , therefore, P + L LRMS L Ǹ2 R 2R L L 1 and P SUP + VDD I DDavg and I DDavg + p ŕ p V P sin(t) dt + * 1 p R 0 L 2V P P [cos(t)] p + 0 pR R L L V Therefore, 2V V DD P pR L substituting PL and PSUP into equation 6, P SUP + 2 Efficiency of a BTL amplifier + where: V 14 P + Ǹ2 PL RL VP 2 RL 2 V DD V P p RL + p VP 4 VDD PL = Power delivered to load PSUP = Power drawn from power supply VLRMS = RMS voltage on BTL load RL = Load resistance VP = Peak voltage on BTL load IDDavg = Average current drawn from the power supply VDD = Power supply voltage ηBTL = Efficiency of a BTL amplifier (10) Submit Documentation Feedback TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 Therefore, Θ p h BTL + Ǹ2 PL RL 4V DD (11) Table 2. Efficiency and Maximum Ambient Temperature vs Output Power in 5-V 8-Ω BTL Systems Output Power (W) Efficiency (%) Internal Dissipation (W) Power From Supply (W) Max Ambient Temperature (°C) 0.25 31.4 0.55 0.75 62 0.50 44.4 0.62 1.12 54 1.00 62.8 0.59 1.59 58 1.25 70.2 0.53 1.78 65 JA + 1 1 + + 113°CńW 0.0088 Derating Factor (13) Given θJA, the maximum allowable junction temperature, and the maximum internal dissipation, the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the TPA6205A1 is 125°C. T A Max + T J Max * ΘJA P Dmax + 125 * 113(0.634) + 53.3°C (14) Equation 14 shows that the maximum ambient temperature is 53.3°C at maximum power dissipation with a 5-V supply. Table 2 employs Equation 11 to calculate efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a 1.25-W audio system with 8-Ω loads and a 5-V supply, the maximum draw on the power supply is almost 1.8 W. A final point to remember about Class-AB amplifiers is how to manipulate the terms in the efficiency equation to the utmost advantage when possible. Note that in Equation 11, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. A simple formula for calculating the maximum power dissipated, PDmax, may be used for a differential output application: 2 V2 DD P D max + 2 p RL (12) PDmax for a 5-V, 8-Ω system is 634 mW. The maximum ambient temperature depends on the heat sinking ability of the PCB system. The derating factor for the 2 mm x 2 mm Microstar Junior™ package is shown in the dissipation rating table. Converting this to θJA: Table 2 shows that for most applications no airflow is required to keep junction temperatures in the specified range. The TPA6205A1 is designed with thermal protection that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using more resistive than 8-Ω speakers dramatically increases the thermal performance by reducing the output current. PCB LAYOUT For the DRB (QFN/SON) and DGN (MSOP) packages, it is good practice to minimize the presence of voids within the exposed thermal pad interconnection. Total elimination is difficult, but the design of the exposed pad stencil is key. The stencil design proposed in the Texas Instruments application note "QFN/SON PCB Attachment" (SLUA271) enables out-gassing of the solder paste during reflow as well as regulating the finished solder thickness. Typically the solder paste coverage is approximately 50% of the pad area. In making the pad size for the BGA balls, it is recommended that the layout use soldermask-defined (SMD) land. With this method, the copper pad is made larger than the desired land area, and the opening size is defined by the opening in the solder mask material. The advantages normally associated with this technique include more closely controlled size and better copper adhesion to the laminate. Increased copper also increases the thermal performance of the IC. Better size control is the result of photo imaging the stencils for masks. Small plated vias should be placed near the center ball connecting ball B2 to the ground plane. Added plated vias and ground plane act as a heatsink and increase the thermal performance of the device. Figure 35 shows the appropriate diameters for a 2 mm × 2 mm MicroStar Junior™ BGA layout. Submit Documentation Feedback 15 TPA6205A1 www.ti.com SLOS490A – JULY 2006 – REVISED AUGUST 2006 It is very important to keep the TPA6205A1 external components very close to the TPA6205A1 to limit noise pickup. The TPA6205A1 evaluation module (EVM) layout is shown in the next section as a layout example. 0.38 mm 0.25 mm 0.28 mm C1 B1 C2 B2 C3 B3 A1 VIAS to Ground Plane A3 Solder Mask Paste Mask (Stencil) Copper Trace Figure 35. MicroStar Junior™ BGA Recommended Layout 16 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPA6205A1DGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPA6205A1DGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPA6205A1DGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPA6205A1DGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPA6205A1DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA6205A1DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA6205A1DRBT PREVIEW SON DRB 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Mailing Address: Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated