W83301R Winbond ACPI-STR Controller W83301R Data Sheet Revision History Pages Dates Version Version on Web Main Contents 1 N.A. 01/Feb. 0.5 N.A. All of the versions before 0.50 are for internal use. 2 4,5 01/MAY 0.6 N.A. Application circuit Update Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83301R Preliminary 1. General Description The W83301R is an ACPI-compliant controller for microprocessor and other computer applications. In substance, the part can mainly operate in alternative configurations mode A and B – mode A provides a switch controller to generate a 5VDL voltage from ATX power supply, a linear controller – STR1 (2.5VDUAL), and a bus termination controller – 1.25 VDUAL for high speed bus such as RDRAM/DDRAM current sinking and sourcing; and mode B provides a switch controller to generate a 5VDL voltage from ATX power supply and three linear controllers for specific voltage regulations – that is STR1 (2.5VDUAL), STR2 (3.3VDUAL) and STR3 (1.8 VDUAL), all of the outputs can simply configured by VSET0, VSET1. Besides, the W83301R also can provide extra voltage up to 0.2V in each regulator output for more performance. In order to reduce the customer’s cost, and simplify the circuit design, the W83301R integrates a charge-pump engine into the chip to provide higher driving voltage for single N-channel MOSFETs, that is the W83301R, can drive only N-channel MOSFETs for all applications. In the other hand, the W83301R also offer PWOK and over current detection to protect each output and soft-start protects all linear controllers from rush current attack. The W83301R is available in a 20-pin SOP package. 2.Features Provides alternative configurations for flexible applications Mode A Provide a switch controller to generate 5VDUAL Linear controller STR1–2.5VDUAL (RDRAM/DDRAM application) Bus termination controller –1.25VDUAL for high speed bus termination application to sinking and sourcing redundant current Mode B Provide a switch controller to generate 5VDUAL Linear controller STR1 – 2.5VDUAL (Clock Gen. Application) Linear controller STR2 – 3.3 VDUAL (SDRAM Application) Linear controller STR3 – 1.8VDUAL (Chipset Application) Provide a switch to enable/disable 5VDL output in S5 state via 5VDLEN pin for USB application Supports SDRAM/RDRAM/DDRAM ACPI-STR Functions Drives all N-Channel MOSFETs Power-Up Softstart for all controllers Up to 0.2V incremental voltage on STR1/STR2 for over-clock application. Under-Voltage Fault Monitor Soft-Start function 20-Pin SOP Package Confidential 1 Revision 0.6 W83301R Preliminary 3.Pin Configuration Figure 1. W83301R Pin Configuration STRDRV2/BTDRV 1 20 STRDRV1 STRSEN2/BTSEN 2 19 STRSEN1 STRDRV3/BTSINK 3 18 SS STRSEN3 4 17 PWOK Vss 5 Vcc 6 C1 7 14 VSET0 C2 8 13 VSET1 ChrPmp 9 12 S3# 5VDLEN# 10 11 S5# Confidential inbond W83301R 2 Revision 0.6 16 5VDRV 15 5VDLSB W83301R Preliminary 4.Pin Description SYMBOL PIN STRDRV2/BTDRV 1 STRSEN2/BTSEN 2 STRDRV3/BTSINK 3 STRSEN3 4 GND Vcc 5 6 C1 7 C2 8 ChrPmp 9 5VDLEN# S5# S3# 10 11 12 VSET1 13 VSET0 14 5VDLSB 15 5VDRV 16 PWOK 17 SS 18 STRSEN1 19 STRDRV1 20 FUNCTION Mode A: BT Current Source. Connect this pin to the gate of a suitable N-channel MOSFET for driving bus termination regulator output. Mode B: STR2 Driver. Connect this pin to the gate of a suitable N-channel MOSFET for driving STR2 output. Mode A: BT Sense. Connect this pin to the bus termination regulator output. Mode B: STR2 Sense. Connect this pin to the STR2 output. Mode A: BT Current Sink. This pin is used to drive a N-channel MOSFET to sink the redundant current in the high-speed bus. Mode B: STR3 Driver. Connect this pin to the gate of a suitable N-channel MOSFET for driving STR3 output. Mode A: Function Reserved. Pull up this pin to +5VSB through a 1.5 Kohm resistor. Mode B: STR3 Sense. Connect this pin to the STR3 output. Power Ground. Connect this pin to ground. Power Vcc. Input 5VSB supply. Charge Pump Cap. Attach flying capacitor between this pin and C2 to generate internally used high voltage from 5V power supply. Charge Pump Cap. Attach flying capacitor between this pin and C1 to generate internally used high voltage from 5V power supply. Charge Pump output. This pin produces voltage doubled 5V supply by chargepumping. Bypass with a 0.1uF capacitor. 5VDL Enable. Control 5VDL voltage output. Pull-up internally. S5 Status. Control signal governing the soft off state S5. Pull-up internally. S3 Status. Control signal governing the soft off state S3. Pull-up internally. Voltage Selection 1. Combine with VSET2 to select operation mode and output voltages of STR regulators. Voltage Selection 0. Combine with VSET1 to select operation mode and output voltages of STR regulators. 5VSB Output Control. Connect this pin to the gate of a N-MOSFET to output 5VSB power to 5VDL. 5V Output Control. Connect this pin to the gate of a N-MOSFET to output 5V power to 5VDL. Power OK. Open collector input/output. Used to indicate the ready of 5Vin supply. If any STR supply (only STR1 in mode A) occurs over current and induce undervoltage, PWOK will be pull down. Soft-Start. Attach a capacitor (0.033u) to this pin to determine the softstart rate. A ramp generated by charging this capacitor with internal soft-start current (18uA) is used to clamp the voltage rising slew rate of STR regulators and 5VDL. Soft starting avoids too much rush current during voltage setup. STR1 Sense. Connect this pin to the STR1 output. STR1 Driver. Connect this pin to the gate of a suitable N-channel MOSFET for driving STR1 output. Confidential 3 Revision 0.6 W83301R Preliminary 5. Application Circuit 5VSB C1 0.1u 3.3Vdual 5V C2 0.1u 5VSB 6 U1 Q2 MOSFET N 16 STRdrv1 15 STRsen2 10 12 PWOK 11 Q4 MOSFET N 1 1.25V C6 1000u 5VDLEN S3 STRdrv3 S5 Connect VSET0 and VSET1 as following table to set operation mode and output voltage Q5 MOSFET N 3 C8 0.1u ChrPmp 4 R1 5VSB 1.5k 9 8 C1 C7 0.1u C2 STRsen3 7 VSET1 5 VSET1 VSET0 SS 13 18 14 GND S3 C9 0.1u Figure 2. Mode A (DDR Mode) Application Circuit Mode DDR VSET0 VSET1 STR1 Bus Termination Controller 0V 0V 2.5VDUAL 1.25VDUAL 0V NC 2.6VDUAL 1.30VDUAL 0V 5V 2.7VDUAL 1.35VDUAL Confidential 4 Revision 0.6 C4 0.1u 2 PWOK 5VDLEN (chipset)SLP_S5# 2.5V 3.3Vdual 5VDLSB 5VDUAL C5 1000u 19 C3 1000u STRdrv2 17 20 5VDRV STRsen1 Q3 MOSFET N Q1 MOSFET N W83301R Preliminary 5. Application Circuit Figure 3. Mode B (SDRAM Mode) Application Circuit 5VSB C1 0.1u 3.3Vdual 5V C2 0.1u 6 U1 5VS B STRdrv1 16 Q2 MOSFET N 15 STRsen2 10 12 PWOK 11 2.5V 5VDUAL 5VDLSB 5VDUAL C5 1000u 19 C3 1000u STRdrv2 17 20 5VDRV STRsen1 Q3 MOSFET N Q1 MOSFET N Q4 MOSFET N 1 C4 0.1u 2 3.3V 3.3Vdual PWOK C6 1000u 5VDLEN S3 S5 STRdrv3 3 Q5 MOSFET N C7 0.1u 5VDLEN S3 14 (chipset) SLP_S5# 13 5VSB VSET0 VSET1 GN D SS C1 C2 Chr STRsen3 Pm p 4 1.8V C8 1000u VSET1 5 18 7 Connect VSET0 and VSET1 as following table to set operation mode and output voltage 8 C10 C9 0.1u Mode SDRAM 9 0.1u C11 0.1u VSET0 VSET1 STR1 STR2 STR3 5V 5V 2.5VDUAL 3.3VDUAL 1.8VDUAL 5V NC 2.6VDUAL 3.4VDUAL 1.8VDUAL 5V 0V 2.7VDUAL 3.5VDUAL 1.8VDUAL Confidential 5 Revision 0.6 W83301R Preliminary 6.Block Diagram Figure 4. W83301R Internal Block Diagram Vcc C1 C2 ChrPmp To POWMOS drivers Charge Pump SS STRDRV1/BTDRV STRSEN1/BTSEN 5VDRV Monitor and Control 5VDLSB STRDRV2/BTSINK +5VSB STRSEN2 +5VSB 1.26V STRDRV3 STRSEN3 VSET0 VSET1 Confidential S3# 5VDLEN# S5# 6 Revision 0.6 GND W83301R Preliminary 7.Functional Description 7.1 Mode Selection The W83301R supports two modes for customer’s multi-applications, as shown as Table1, the mode A and mode B can selected via VSET0 pin. If this pin connects to 5V, the chip will operate under mode A, otherwise the chip will operate under mode B when VSET0 connects to ground. Both mode A and B supports a linear switch to generate an ACPI-compliant 5VDL voltage from ATX power supply 5V/5VSB according to S5# and S3# signals. And user also can turn off the whole 5VDL output in S5 state via 5VDLEN# pin if needed. Under the mode A operation, the chip provide a linear controller STR1 that drives a N-channel MOSFET Q3 (refer to figure) to generate a regulated voltage 2.5VDUAL from an external power source 3.3VDUAL, the 2.5 VDUAL is provide for RDRAM/DDRAM ACPI suspend to RAM application. And In order to simply the circuit design and reduce customer’s cost, the W83301R also integrate a bus termination controller BT driving two external N-channel MOSFETs (Q4, Q5) to generate a specific ACPI-compliant voltage according to a half of STR1 output for sourcing and sinking bus redundant current. Under the mode B operation, the chip provide three linear controllers, that is STR12.5VDUAL, STR2- 3.3 VDUAL, and STR3- 1.8VDUAL, all of the three outputs drive a Nchannel MOSFET (Q3, Q4, and Q5) to generate an ACPI-compliant voltage by different applications. Such as STR1- 2.5VDUAL for clock generator application, STR2- 3.3 VDUAL for SDRAM application, and STR3- 1.8VDUAL chipset application. Besides, as shown in Table 1 the W83301R also provide a tri-state pin VSET1 to bias an extra voltage up to 0.2V in each output for more performance but under mode A operation, the BT output voltage will generated according to a half of STR1 output set by VSET1. Table 1. W83301R Control Table Mode VSET0 A VSET1 STR1 Bus Termination Controller 0V 0V 2.5VDUAL 1.25VDUAL 0V NC 2.6VDUAL 1.30VDUAL 0V 5V 2.7VDUAL 1.35VDUAL VSET1 STR1 STR2 STR3 5V 5V 2.5VDUAL 3.3VDUAL 1.8VDUAL 5V NC 2.6VDUAL 3.4VDUAL 1.8VDUAL 5V 0V 2.7VDUAL 3.5VDUAL 1.8VDUAL Mode VSET0 B Confidential 7 Revision 0.6 Remark -STR1 output for RDRAM/DDRAM voltage -Bus Termination Controller for memory bus redundant current sinking and sourcing. Remark -STR1 output for Clock Gen. voltage -STR2 output for SDRAM voltage -STR3 output for Chipset voltage W83301R Preliminary 7.2 ACPI State Control In order to meet the ACPI specification, the W83301R implement a state machine as shown as Figure 5 to generate ACPI-compliant power state transition. There are only five states in the state machine cause the W83301R only focus on the memory ACPI control, and the five states are G3 (Mechanical-Off State), S0 (Full-Power State), S3 (Sleeping State-Suspend to RAM), S5On (Soft-Off State), S5Off and all of these states changed to the other according to the condition of S3#, S5# and 5VDLEN#. On the other hand, cause of the W83301R allows customer to disable/enable the 5VDUAL output in S5 state via 5VDLEN# pin, there are two states, S5On and S5Off, corresponding to S5 state. A soft ramp-up mechanism is needed to protect the 5VDL output from the rush current attack during the S5Off to S5On state transition. Same as the 5VDL output, the W83301R also provides soft ramp-up mechanism during S5On to S0 state transition in each STR output. In the state machine, when the power on, and the 5V input from power supply arrive 4.5V, the chip will enter S5Off first from G3, and ramp-up into S5On state by two conditions, the one is when 5VDLEN#=0 under standby power supply to resume the 5VDL output, the other one is S3#=1 and S5#=1 the system will enter S1 state. During S5On state, the chip will return back to S5Off when the customer wants disabling the 5VSB output (5VDLEN#=1) to save some power. And the chip will drive all outputs into S0 state will S3#=1 and S5#=1. When the system under the S0 state, the system should enter the S3-sleeping (S3#=0, S5#=1) or S5-soft off (S5#=0) state when the system idle for a long time or user power-off. When the system suspend to RAM, the system will be wakeup and enter S0-full power state by (S3#=1, S5#=1,PWOK=1), or get into S5-sleeping soft off state by (S5#=0) Table 2. W83301R Outputs Table State G3 S5 (5VDL Off) S5 (5VDL On) S0 S3 5VDL Off Off On (Driven by 5VDLSB) On (Driven by 5VDRV) On (Driven by 5VDLSB) STR1 Off Off STR2 Off Off STR3 Off Off LUV Activity * No No Off Off Off No On On On Yes On On On Yes *When the STR2 & STR3 configured as bus termination controller, only STR1 has linear under voltage function. Confidential 8 Revision 0.6 W83301R Preliminary 7.3 Charge Pump In order to simply the design circuit and provide a good-price solution for customer, the W83301R integrate with a switched-capacitor voltage doubler charge pump to provide a higher driving voltage (Up to 10 volt) and can drive a single N-channel MOSFETs in each output. 7.4 Power OK The W83301R use a bi-direction Power OK signal to ensure the system can work normally. When the system jump from state S3 to state S0, the W83301R will monitor the input signal from PWOK pin to ensure that external system power is OK and then switch each outputs into S0 stage; In the other hand, the W83301R will pull down the Power OK signal to inform the system that a over current and induce under-voltage occurred. 7.5 Soft-Start During ‘S5off’ to ‘S5on’ and ‘S5on’ to ‘S0’ state transitions, the 5Vdual and STR voltages need to ramp up from 0 to their set values respectively. The charging current flowing to output capacitors must be limited to avoid supply drop-off. In W83301R, an internal 18 uA current source (Iss) charges an external capacitor (Css) to generate a linear ramp-up voltage on SS pin (Vss). The Vss slews from 0 to about 9V during the above-mentioned state transitions, and the Vss slew rate is used to clamp the ramp-up rate of 5Vdual and STR output voltages. This output clamping allows power-ups free of supply drop-off events. Since the outputs are ramped up in a constant slew-rate, the current dedicated to charge any output capacitor can be calculated with the following formula: ICOUT = Iss x (Cout / Css) Some technique is included in W83301R to further reduce the total charging current: In Mode B configuration, the start-up of ramp-up time STR3 (1.8V) will be advanced from that of STR1 to reduce the overlap time of charging. And in Mode A configuration, the bus-terminator is input clamped, and its output voltage slew-rate, so as its charging current, will be limited to half of that of STR1. Note that, too slow ramp-up rate is not recommended. If so, the state transition mentioned above will be prolonged to much. Before Vss ramps up to its upper limit (about 9V), the state transition will not be completed and will not go into next state. Confidential 9 Revision 0.6 W83301R Preliminary 8.Electrical Characteristics 8.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Parameter Voltage on any pin with respect to GND Rating - 0.5 V to + 7.0 V TSTG Pin# 1,2,3,4,8,15,16,18,19,20 Pin# 7,10,11,12,13,14,17 Storage Temperature - 0.5 V to + 12.0 V GND-0.3 V to VChr-Pmp + 0.3V GND-0.3 V to Vcc + 0.3V - 65°C to + 150°C TB Ambient Temperature - 55°C to + 125°C TA Operating Temperature 0°C to + 70°C Vss, Vcc ChrPmp Hi-V Pins Lo-V Pins 8.2 AC CHARACTERISTICS Vcc=5V ± 5 %, TA = 0°C to +70°C Parameter Symbol Vcc SUPPLY CURRENT Norminal Supply Current I5VSB POWER-ON RESET Rising V5VSB Threshold 5VSB Hysteresis Rising VChr_Pmp Threshold VChr_Pmp Hysteresis SOFT-START Soft-Start Current Iss VSS upper limit Confidential Min Typ 6 Units Test Conditions mA 4.3 1 V V V V 18 9 uA V 1 8.5 10 Revision 0.6 Max VChr_Pmp > 8.5V V5VSB > 4.3V W83301R Preliminary 8.2 AC CHARACTERISTICS (Continued) Vcc=5V ± 5 %, TA = 0°C to +70°C Parameter Symbol STR1 lINEAR REGULATOR Nominal Output Voltage Min Typ Max Units 2.5 V Nominal Output Voltage 2.6 V Nominal Output Voltage 2.8 V Regulation 5 STRSEN1 Under-Voltage Falling Threshold 80 MAX STRDRV1 Output Voltage STR2 LINEAR REGULATOR Nominal Output Voltage Nominal Output Voltage Nominal Output Voltage Regulation 6 3.3 3.4 3.5 5 STRSEN1 Under-Voltage Falling Threshold 80 MAX STRDRV1 Output Voltage STR3 LINEAR REGULATOR Nominal Output Voltage Regulation 6 1.8 5 STRSEN1 Under-Voltage Falling Threshold 83 MAX STRDRV1 Output 6 Voltage BUS TERMINATOR Nominal Output Voltage / VSTRSEN1 Regulation 5VDUAL SWITCH CONTROLLER 5VDRV Output High Voltage 9 5VDRV Sourcing Current 5VDRV Sinking Current 5VDLSB Output High Voltage 9 5VDLSB Sourcing Current 5VDLSB Sinking Current S3#,S5#,5VDLEN#, PWOK,CHARGE PUMP Confidential 50 5 VSET0=0V, VSET1=0V or VSET0=5V,VSET1=5V VSET0=0V, VSET1=NC or VSET0=5V,VSET1=NC VSET0=0V, VSET1=5V or VSET0=5V,VSET1=0V % % V I(STRDRV1) < 0.1mA V V V % % VSET0=5V,VSET1=5V VSET0=5V,VSET1=NC VSET0=5V,VSET1=0V V I(STRDRV1) < 0.1mA V % % VSET0=5V V I(STRDRV1) < 0.1mA % VSET0=0V % 7 400 mA uA 7 230 mA uA 11 Revision 0.6 Test Conditions Cload=3000p Cload=3000p Cload=3000p Cload=3000p Cload=3000p Cload=3000p W83301R Preliminary Input Logic High Input Logic Low PWOK Output Inpedence Charge Pump Frequency 2.2 0.8 150 200 V V ohm KHz LUV active 9.Package Specification 20L SSOP-209 mil D 11 20 DTEAIL A HE E 10 1 b A2 A SEATING PLANE Y q e SYMBO b MIN NO DETAIL A DIMENSION IN DIMENSION IN MAX. MIN NO MAX. 0.079 2.00 A A2 0.05 1.65 b 0.22 0.38 0.009 0.015 c 0.09 0.25 0.004 0.010 7.50 0.272 0.283 0.295 A1 1.75 1.85 0.002 0.065 0.069 0.073 D 6.90 7.20 E HE 5.00 5.30 5.60 0.197 0.209 0.220 7.40 7.80 0.65 8.20 0.291 0.307 0.323 e L L1 0.55 0.75 q 0.025 0.95 0.021 1.25 Y Confidential A1 Revision 0.6 8 0.037 0.004 0.10 0 0.030 0.050 12 0 8 L L1 SEATING PLANE W83301R Preliminary Confidential 13 Revision 0.6 W83301R Preliminary 10.Ordering Information Part Number W83301R Package Type 20-PIN SSOP Production Flow Commercial, 0°C to +70°C 11.How to Read the Top Marking inbond W83301R 1060B11039050-21NA 1st line: Winbond logo 2nd line: W883301R – the part number 3rd line: Tracking code Tracking code 106 O B 1 1039050-21NA 106: packages made in Year 01’, week 6 O: assembly house ID; O means OSE, G means GR, … A: the IC version 1: wafers manufactured in Winbond FAB I 1039050-21NA: wafer production series number Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. Confidential 14 Revision 0.6