Winbond ACPI-STR Controller W83301DR-O W83301DR-O Data Sheet Revision History 1 Pages Dates Version Version on Web N.A. 02/Jul. 1.0 1.0 Main Contents 1st Release Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83301DR-O 1. General Description The W83301DR-O is an ACPI-compliant controller for microprocessor and other computer applications. The part provides functions - two switch controllers to generate a 5VDL and a 3.3 V DL voltage from ATX power supply; a linear controller – STR1 (2.5VDUAL), and a bus termination controller – STR2 (1.25 VDUAL) for high-speed bus such as RDRAM/DDRAM current sinking and sourcing. Besides, the W83301DR-O also can provide extra voltage up to 0.4V in each regulator output for over-clocking application and more performance by two hardware pins - VSET2 , and VSET3 . In order to reduce the customer’s cost, and simplify the circuit design, the W83301DR-O integrates a chargepump engine into the chip to provide higher driving voltage to drive single N-channel MOSFETs. The W83301DR-O also offers PWOK and over current detection to protect each output and soft-start protects all linear controllers from rush current attack. The W83301DR-O is available in a 24-pin TSSOP package. 2. Features v Provides various voltages for DDR-STR applications § Provide a switch controller to generate 5VDUAL voltage § Provide a switch controller to generate 3.3VDUAL voltage § Linear controller STR1–2.5V DUAL for DDR application § Bus termination controller STR2 –1.25VDUAL for high speed bus termination to sink and drive redundant current v Provide a switch 5VDLEN pin to enable/disable 5VDL output in S5 state for USB application v Supports DDR ACPI-STR Functions v Drives all N-Channel MOSFETs v Power-Up Softstart for all controllers v Up to 0.4V/0.2V incremental voltage on STR1/STR2 for over-clocking application. v Under-Voltage Fault Monitor v Soft-Start function v 24-Pin TSSOP Package 1 Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 3. W83301DR-O Pin Configuration Reserved 1 24 Reserved BTDRV 2 23 STR1 DRV BTSEN 3 22 STR1SEN BTSINK 21 SS 4 Reserved 5 Vss 6 5VSB 7 inbond W83301DR-O 20 PWOK 19 3VDRV /5VDRV 18 5VDLSB C1 8 17 3VDLSB C2 9 16 3VSBSEN ChrPmp 10 15 S3# 5VDLEN# 11 14 S5# VSET3 12 13 VSET2 2 Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 4. Pin Description SYMBOL Reserved PIN Pin Reserved 1 BTDRV 2 BTSEN 3 BTSINK 4 Reserved Vss 5VSB 5 6 7 C1 8 C2 9 ChrPmp 10 5VDLEN# 11 VSET3 12 VSET2 13 S5# S3# 3VSBSEN 14 15 16 3VDLSB 17 5VDLSB 18 3VDRV /5VDRV 19 PWOK 20 SS 21 STR1SEN 22 STR1DRV 23 Reserved 24 FUNCTION BT Current Source. Connect this pin to the gate of a suitable N-channel MOSFET for driving bus termination regulator output. BT Sense. Connect this pin to the bus termination regulator output. BT Current Sink. This pin is used to drive a N-channel MOSFET to sink the redundant current in the high-speed bus. Function Reserved. Pull up this pin to +5VSB through a 1.5 Kohm resistor. Power Ground. Connect this pin to ground. Power 5VSB . Input 5VSB supply. Charge Pump Cap. Attach flying capacitor between this pin and C2 to generate internally used high voltage from 5V power supply. Charge Pump Cap. Attach flying capacitor between this pin and C1 to generate internally used high voltage from 5V power supply. Charge Pump output. This pin produces voltage doubled 5V supply by charge pumping. Bypass with a 0.1uF capacitor. 5VDL Enable. Control 5VDL voltage output. Pull-up internally. Voltage Selection. Combine with VSET2 to select output voltages of STR regulators. Voltage Selection. Combine with VSET3 to select output voltages of STR regulators. S5 Signal. Control signal governing the soft off state S5. Pull-up internally. S3 Signal. Control signal governing the soft off state S3. Pull-up internally. 3VDL Sense. Connect this pin to the STR1 output. 3VDL Drive. Connect this pin to the gate of a suitable N-channel MOSFET for driving STR1 output. 5VSB Output Control. Connect this pin to the gate of a N-MOSFET to output 5VSB power to 5VDL. 3.3V/5V Output Control. Connect this pin to the gate of a N-MOSFET to output 3.3V/5V power to 3.3VDL/5VDL. Power OK. Open collector input/output. Used to indicate the ready of 5Vin supply. If any STR supply occurs over current and induce under-voltage, PWOK will be pull down. Soft-Start. Attach a capacitor (0.033u) to this pin to determine the softstart rate. A ramp generated by charging this capacitor with internal soft -start current (18uA) is used to clamp the voltage rising slew rate of STR regulators and 5VDL. Soft starting avoids too much rush current during voltage setup. STR1 Sense. Connect this pin to the STR1 output. STR1 Drive. Connect this pin to the gate of a suitable N-channel MOSFET for driving STR1 output. Pin Reserved 3 Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 5. W83301DR-O Dual-Layout with W83301R/W83301DR 3.3VDL 2 MOSFET N 1 Q2 Reserved Reserved BTDRV STR DRV1 BTSEN STR SEN 1 24 23 3 Q1 MOSFET N 1 2 22 2.5VSTR C1 MOSFET N 1 Q3 C5 2200uF 2 3 3 1.25VSTR 3.3VDL U1 1 3 4 BTSINK SS 21 2 C4 2200uF 0.1u 5 5 VSB 1.5k R 1 6 7 Reserved PWOK VSS 20 PWOK 19 3 5VSB 3 VDRV/5 VDRV 5 VSB 5 VDLSB 18 5V 1 2 MOSFET N Q4 Q5 MOSFET N 1 3 2 C8 100uF 8 C2 0.1u C1 VSET0/3VDLSB C2 VSET1/3VSBSEN 5 VDL 17 VCC3 1 9 2 16 C3 10 ChrPmp S3# 5 VDLEN# S5# VSET3 VSET2 15 SLP_S3# 14 SLP_S5# 3 MOSFET N Q6 5VSB 3 0.1u 11 VSET3 12 DDR 20-pin Mode DDR 24-pin Q7 MOSFET N 1 13 VSET2 module Mode C6 470uF 2 3.3VDL VSET0 VSET1 VSET0 VSET1 STR1 0V 0V 2.5VSTR 1.25VSTR 0V NC 2.6VSTR 1.30VSTR 0V 5V 2.7VSTR 1.35VSTR VSET2 VSET3 STR1 0V 0V 2.5VSTR 5V 0V 2.63VSTR 1.325VSTR 0V 5V 2.77VSTR 1.385VSTR 5V 5V 2.9VSTR 4 C7 100uF Bus Termination Controller Bus Termination Controller 1.25VSTR 1.45VSTR Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 6. Internal Block Diagram 5VSB C1 C2 ChrPmp To POWMOS Drivers Charge Pump SS STR1 DRV STR1 SEN 3 V DRV /5V DRV 5VDLSB Monitor and Control 3VDLSB BTDRV BTSEN 3VSBSEN BTSink +5VSB +5VSB VSET2 VSET3 1.26V S3# S5# 5 5V DLEN# GND Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 7. Functional Description 7.1 ACPI State Control In order to meet the ACPI specification, the W83301DR-O implements an internal state machine to generate ACPI-compliant power state transition. There are five states in the state machine, the five states are G3 (Mechanical-Off State), S0 (Full-Power State), S3 (Sleeping State-Suspend to RAM), S5 On (Soft-Off State), S5Off and all of the state changes to the other according to the value of S3#, S5# and 5V DLEN#. On the other hand, cause of the W83301DR-O allows the user to disable/enable the 5V DUAL output in S5 state via the 5VDLEN# pin, there are two states - S5On and S5Off, corresponding to S5 state. Besides, a soft ramp-up mechanism is needed to protect the 5VDL output from the rush current attack during the S5 Off to S5On state transition. Same as the 5V DL output, the W83301DR-O also implements soft ramp-up mechanism in each STR outputs during the S5On state transfers to the S0 state. As the internal state machine, when the power turns on, the voltage of 5VSB of the ATX power supply ramps up to 4.5V, the chip will enters the S5Off state from the G3 state, and will enters the S5 On state if the signal of 5VDLEN#=0 and S5#=0; When the signals S3#=1 and S5#=1, the system will enters the S0 state from S5off . In the S5 On state, the chip will returns back to the S5 Off state if the 5VDLEN#=1 is set. When the system in the S0 state, the system will enters the S3 (S3#=0, S5#=1) or S5 (S5#=0) state when the system is idle for a long time or user presses the power button. When the system enters the S3 state, the system will waked up and enter the S0 state by (S3#=1, S5#=1,PWOK=1), or gets into S5 state by (S5#=0). Table 1. W83301DR-O Outputs Table State G3 5VDL Off 3VDL Off On S5 (5VDL Off) Off (Driven by 3V DLSB) On S5 (5VDL On) (Driven On by 5V DLSB) (Driven by 3V DLSB) On On S0 (Driven by 5V DRV) (Driven by 3V DRV) On On S3 (Driven by 5V DLSB) (Driven by 3V DLSB) * Only the STR1 has linear under voltage function. 6 STR1 Off STR2 Off LUV Activity * No Off Off No Off Off No On On Yes On On Yes Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 7.3 Charge Pump In order to simply the design circuit and provide a cost-effective solution for customer, the W83301DR-O integrates with a switched-capacitor voltage doublers charge pump to provide a higher driving voltage (Up to 10 volt) and can drive single N-channel MOSFETs in each output. 7.4 Power OK The W83301DR-O use a bi-direction Power OK signal to ensure the system can work normally. When the system jump from the state S3 to the state S0, the W83301DR-O will monitor the input signal from PWOK pin to ensure that external system power is OK and then will switches each outputs into the S0 state; In the other hand, the W83301DR-O will pulls down the Power OK signal to inform the system a over current and induce undervoltage occurred. 7.5 Soft-Start During the ‘S5off’ to the ‘S5on’ and the ‘S5on’ to the ‘S0’ state transitions, the 5Vdual/3Vdual and STR voltages need to ramp up from 0V to the setting values respectively. The charging current flowing to output capacitors must be limited to avoid supply drop-off. In W83301DR-O, an internal 18 uA current source (Iss) charges an external capacitor (Css) to generate a linear ramp-up voltage on SS pin (Vss). The Vss slews from 0V to about 9V during the above-mentioned state transitions, and the Vss slew rate is used to clamp the ramp-up rate of 5Vdual and STR output voltages. This output clamping allows power-ups free of supply drop-off events. Since the outputs are ramped up in a constant slew-rate, the current dedicated to charge any output capacitor can be calculated with the following formula: ICOUT = Iss x (Cout / Css) Some technique are included in W83301DR-O to further reduce the total charging current: the bus-terminator is input clamped, and its output voltage slew-rate, so as its charging current, will be limited to half of that of STR1. Note that, too slow ramp-up rate is not recommended. If so, the state transition mentioned above will be prolonged to much. Before Vss ramps up to its upper limit (about 9V), the state transition will not be completed and will not go into next state. 7 Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 8. Electrical Characteristics 8.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Vss, Vcc ChrPmp Hi-V Pins Parameter Voltage on any pin with respect to GND Lo-V Pins Pin# 8,11,12,13,14,15,16,20 TSTG TB TA Storage Temperature Ambient Temperature Operating Temperature Pin# 2,3,4,5,9,10,17,18,19,21,22,23 Rating - 0.5 V to + 7.0 V - 0.5 V to + 12.0 V GND-0.3 V to VChr-Pmp + 0.3V GND-0.3 V to Vcc + 0.3V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C 8.2 AC CHARACTERISTICS Vcc=5V ± 5 %, T A = 0°C to +70°C Parameter Symbol Min Vcc SUPPLY CURRENT I5VSB Norminal Supply Current POWER-ON RESET Rising V5VSB Threshold 5VSB Hysteresis Rising VChr_Pmp Threshold VChr_Pmp Hysteresis SOFT-START Soft-Start Current Iss VSS upper limit Typ Max 6 Test Conditions mA 4.3 1 8.5 8 Units V V V 1 V 18 9 uA V VChr_Pmp > 8.5V V5VSB > 4.3V Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 8.2 AC CHARACTERISTICS (Continued) Vcc=5V ± 5 %, TA = 0°C to +70°C Parameter Symbol STR1 LINEAR REGULATOR Nominal Output Voltage Nominal Output Voltage Nominal Output Voltage Nominal Output Voltage Regulation Min Max Units 2.5 2.63 2.77 2.90 3 3 STRSEN1 Under-Voltage Falling Threshold MAX STR DRV1 Output Voltage BUS TERMINATION REGULATOR Nominal Output Voltage / VSTRSEN1 Regulation 5VDUAL SWITCH CONTROLLER 5VDRV Output High Voltage 5VDRV Sourcing Current 5VDRV Sinking Current 5VDLSB Output High Voltage 5VDLSB Sourcing Current 5VDLSB Sinking Current 3VCC SWITCH CONTROLLER 3VDRV Output High Voltage 3VDRV Sourcing Current 3VDRV Sinking Current 3.3V SB LINEAR REGULATOR Nominal Output Voltage Regulation Typ 80 50 3 V I (STR1 DRV) < 0.1mA % The output is always the 50% of STR1 % 9 7 400 mA uA 7 230 mA uA Cload=3000p Cload=3000p Cload=3000p Cload=3000p Cload=3000p Cload=3000p 7 400 mA uA Cload=3000p Cload=3000p Cload=3000p 3.3 V % 9 9 3 3 STRSEN1 Under-Voltage Falling Threshold 80 MAX 3.3VDLSB Output 6 Voltage S3#,S5#,5VDLEN#, PWOK,CHARGE PUMP Input Logic High 2.2 Input Logic Low PWOK Output Inpedence 150 Charge Pump Frequency 9 Vset2=0V; Vset3=0V Vset2=5V; Vset3=0V Vset2=0V; Vset3=5V Vset2=5V; Vset3=5V % 6 -2 V V V V % Test Conditions % V 0.8 200 V V ohm KHz I (3.3VDLSB) < 0.1mA LUV active Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 9. Package Dimension 24-TSSOP 173mil 10 Publication Release Date: Jul., 2002 Revision 1.0 W83301DR-O 10. Ordering Information Part Number W83301DR-O Package Type 24-PIN TSSOP Production Flow Commercial, 0°C to +70°C 11. How to Read the Top Marking inbond W83301DR-O 1060B11039050-21NA 1st line: Winbond logo 2nd line: W83301DR-O – the part number 3rd line: Tracking code Tracking code 106 O B 1 1039050-21NA 106: packages made in Year 01’, week 6 O: assembly house ID; O means OSE, G means GR, … B: the IC version 1: wafers manufactured in Winbond FAB I 1039050-21NA: wafer production series number Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. 11 Publication Release Date: Jul., 2002 Revision 1.0