F72568
Advanced ACPI Controller IC Datasheet
Release Date: July, 2007
Version: 0.25P
Fintek
Feature Integration Technology Inc.
F72568
F72568 Datasheet Revision History
Version
Date
0.20P
Nov.2005
0.21P
2005/12/20
0.22P
2006/9
0.23P
2006/10
0.24P
2007/3
0.25P
2007/7
Page
Revision History
Preliminary version
-
Added schematic
1
Correct the description relative to Vref
4
Correct pin description, PIN 16
20
Application circuit updated
15
PLED, SLED register description
20
Application circuit updated
19
Update company address
Please note that all data and specifications are subject to change without notice. All the trade marks of products and
companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for use
in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such
improper use or sales.
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F72568
Table of Contents
1
GENERAL DESCRIPTION ........................................................................................................................................................ 1
2
FEATURE ..................................................................................................................................................................................... 1
3
PIN CONFIGURATION & BLOCK DIAGRAM...................................................................................................................... 2
4
SIMPLIFIED POWER SYSTEM DIAGRAM .......................................................................................................................... 3
5
PIN DESCRIPTION..................................................................................................................................................................... 3
6
FUNCTIONAL DESCRIPTION ................................................................................................................................................. 7
7
6.1
ACPI STATE .............................................................................................................................................................................. 7
6.2
CHARGE PUMP .......................................................................................................................................................................... 7
6.3
SOFT-START .............................................................................................................................................................................. 8
6.4
REFERENCE VOLTAGE ............................................................................................................................................................... 8
6.5
UNDER VOLTAGE PROTECTION ................................................................................................................................................. 8
6.6
OVER CURRENT PROTECTION ................................................................................................................................................... 8
6.7
ACCESS INTERFACE .................................................................................................................................................................. 9
REGISTER DESCRIPTION. .................................................................................................................................................... 10
7.1
REGISTER ⎯ INDEX 01H......................................................................................................................................................... 10
7.2
PWM_VRAM_11, PWM_VRAM_10 FINE TUNE VOLTAGE REGISTER ⎯ INDEX 02H .......................................................... 10
7.3
REGISTER ⎯ INDEX 03H......................................................................................................................................................... 11
7.4
PWM_VTT_10, PWM_VTT_11 FINE TUNE VOLTAGE REGISTER ⎯ INDEX 04H................................................................... 11
7.5
REGISTER ⎯ INDEX 05H......................................................................................................................................................... 11
7.6
LR_PCIE_10, LR_PCIE_11 FINE TUNE VOLTAGE REGISTER ⎯ INDEX 06H .......................................................................... 12
7.7
REGISTER ⎯ INDEX 07H......................................................................................................................................................... 12
7.8
LR3_10, LR3_11 FINE TUNE VOLTAGE REGISTER ⎯ INDEX 08H ........................................................................................... 13
7.9
LRPCIE_11, LR3_11 FINE TUNE VOLTAGE REGISTER ⎯ INDEX 09H .................................................................................... 13
7.10 PLED ACPI FREQUENCY SETTING REGISTER ⎯ INDEX 0AH ................................................................................................. 14
7.11 PLED ACPI FREQUENCY SETTING REGISTER ⎯ INDEX 0BH ................................................................................................. 15
7.12 SLED ACPI FREQUENCY SETTING REGISTER ⎯ INDEX 0CH ................................................................................................. 15
7.13 UNDER VOLTAGE, OVER CURRENT ENABLE PROTECTION REGISTER ⎯ INDEX 10H............................................................... 15
7.14 REGISTER ⎯ INDEX 11H ......................................................................................................................................................... 16
8
ELECTRICAL CHARACTERISTIC....................................................................................................................................... 17
9
ORDERING INFORMATION .................................................................................................................................................. 18
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10 PACKAGE DIMENSIONS (48LQFP)...................................................................................................................................... 19
11 APPLICATION CIRCUIT ........................................................................................................................................................ 20
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1 General Description
The F72568 is a fully compliant ACPI controller IC specific for Intel CPU platform. Used with an ATX power
supply, this chip integrates synchronous PWM controller and regulator, several linear controllers, switching signals,
monitoring and control function into 48 pin LQFP package. Its operation mode (sleep or active) is selectable
through some control signals. The F72568 provides 3 switching signals which can generate 5VDUAL, 5VUSB &
3.3VDUAL etc. The F72568 can also provide 6 linear controllers including VCCVID output with power good signal.
This chip integrates a charge pump engine to provide higher driving voltage for appropriate gate during standby. On
the other hand, this chip offers current limiting that protect each PWM outputs, and provides soft-start for linear
controller to avoid rush current. The power LED is programmable and compliant with PC2001. Moreover, this
high-performance chip integrates I2C interface to adjust VRAM, VTT, LR_PCIE, and LR_3 output. This chip is in
48pin LQFP package and powered by 5VSB.
2 Feature
ACPI compliant sleep state control
Provide 3 switching controlled signals for 5VDUAL, 5VUSB and 3.3VDUAL
Programmable 5VDUAL/5VSTR/5VCC for USB device wake up
Provide 6 linear controller and typically use for –
-- 1 channel for Dual power
-- 1 channel for PCI_E power
-- 3 channels for 0.8~5V voltage requirement
-- 1.2V VCCVID with VID_GD signal output
Provide one PWM controller for DDR VDDQ
Provide one PWM regulator for CPU/GMCH VTT termination
1 PWROK input signal(typically from ATXPWOKIN) and 1 PWROK output signal
Provide resume reset signal(RSMRST#)
Programmable power LED control
Provide VREF and VSB9V voltage for generating different voltage use
Power up soft-start and under-voltage monitoring for the linear regulators
Over current protection(OCP) on both PWM controller and regulator
Integrate I2C interface
Provide VREF/1.25V
48 pin LQFP package and 5VSB operation
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3 Pin Configuration & Block Diagram
PLED SLED S5# SS
PWOK
PWOKIN
FAULT#
TURBO#
PS_ONIN#
VID_GD
RSMRST#
VCCGATE
USBGATE
DUALGATE
DUAL3V_DRV
DUAL3V_SEN
VPCIE_DRV
VPCIE_SEN
1.25VREF
SCLK
SDATA
I2C
Interface
VREF
Control
Logic
VSB5V VCC3V
VTT PWM
Regulator
VRAM PWM
Controller
5VDUAL
Linear
F72568
5VUSB
Controller 1
3VDUAL
Linear
LR Controller
Controller 2
VPCIE
VID
LR Controller
LR Controller
Charge
Pump
VID_DRV VID_SEN CP C1 C2
2
Linear
Controller 3
VTT_PWM
VTT_COMP
VTT_OPS
VTT_FB
VRAM_UGATE
VRAM_LGATE
VRAM_OPS
VRAM_FB
LR1_DRV
LR1_SEN
LR2_DRV
LR2_SEN
LR3_DRV
LR3_SEN
GND VBAT
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4 Simplified Power System Diagram
12V
Multi-Phase
PWM
VID_GD
MOSFET
Driver
Intel
CPU
VID_PWR
(5VDUAL)
VRAM_UGATE
VDDQ
VRAM_LGATE
5VSB
3V
Fintek
VGMCH
VTT_PWM MOSFET
F72568DG
Driver
DRAM
GMCH
(NB)
PCIE x 16
ICH
(SB)
PCIE x 1
PCIE_PWR(1.5V)
5V
VREF
LR1~3
ATX
Power
5VDUAL
USB Device
5VUSB
Other Device
3VDUAL
5 Pin Description
I/OD12ts
- TTL level bi-directional pin. Open-drain schmitt trigger output with 16 mA sink capability
OUT5
- Output pin with 5 mA source-sink capability
OD12
- Open-drain output pin with 12 mA sink capability
OD16
- Open-drain output pin with 16 mA sink capability
OD24
- Open-drain output pin with 24 mA sink capability
INts
- TTL level input pin and schmitt trigger
AIN
- Input pin(Analog)
AOUT
- Output pin(Analog)
P
- Power
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Power Pins
PIN NO
PIN NAME
10
VSB5V
19
GND
30
GND
32
VSB5V
42
GND
44
VBAT
46
VCC3V
16
VCC_PWM
TYPE
DESCRIPTION
Power pins
P
VRAM_UGATE and VRAM_LGATE signal power, commend to connect to
12Vcc
Reset & Power Good & Control signal
PIN NO
PIN NAME
TYPE
PWR
48
FAULT#
INts
VCC3V
1
PWOKIN
INts
VSB5V
2
PS_ONIN#
INts
VSB5V
3
S5#
INts
VSB5V
9
VID_GD
OD12
VSB5V
43
RSMRST#
OD12
VBAT
45
PWOK
OD16
VBAT
47
TURBO#
INts
VCC3V
DESCRIPTION
Error input signal for power off.
Power Good Schmitt Trigger input signal. Typically connected to ATX power
good.
Normal power control signal input.
A low active ACPI control signal governing the S5 state. Typically connected to
chipset S5# signal.
This pin is the open drain output of the VCCVID power good comparator.
As VSB come in, this pin will generate RSMRST# signal output which is
delayed 66ms as VSB arrives at 3.3V
Power Good output signal.
Enable adjustable power signal.
Switching Signal & Linear/PWM Controller
PIN NO
PIN NAME
TYPE
PWR
DESCRIPTION
11
VTT_PWM
OUT5
VSB5V
External buffer PWM control output signal
12
VTT_FB
AIN
VSB5V
External buffer PWM feedback signal
13
COMP
AOUT
VSB5V
14
VRAM_FB
AIN
VSB5V
VRAM PWM feedback signal
15
VRAM_OPS
AOUT/AIN
VSB5V
VRAM PWM current protection signal
17
VRAM_LGATE
AOUT
VCC_PWM
VRAM PWM low gate control signal
18
VRAM_UGATE
AOUT
VCC_PWM
VRAM PWM up gate control signal
20
VTT_OPS
AOUT/AIN
VSB9V
21
VID_DRV
AOUT
VSB9V
Output of the error amplifier used to compensate the feedback
loop of the PWM controller.
External buffer PWM current protection signal
Connect this pin to the gate of a suitable N-channel MOSFET.
VID_SEN and VID_DRV act as a linear regulator and generate voltage
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for S0 state power.
22
VID_SEN
AIN
VSB5V
Sense the voltage of linear regulator. VID_SEN and VID_DRV act as a
linear regulator and generate voltage for S0 state power.
Sense the voltage of linear regulator. LR3_SEN and LR3_DRV act as a
24
LR3_SEN
AIN
VSB5V
linear regulator and generate voltage for standby or STR power. Default
for standby power. If VIN is main power, it can generate voltage for S0
sate power.
Connect this pin to the gate of a suitable N-channel MOSFET.
25
LR3_DRV
AOUT
VSB9V
LR3_SEN and LR3_DRV act as a linear regulator and generate voltage
for standby or STR power. Default for standby power. If VIN is main
power, it can generate voltage for S0 sate power.
Connect this pin to the gate of a suitable N-channel MOSFET.
26
LR2_DRV
AOUT
VSB9V
LR2_SEN and LR2_DRV act as a linear regulator and generate voltage
for standby or STR power. Default for standby power. If VIN is main
power, it can generate voltage for S0 sate power.
Sense the voltage of linear regulator. LR2_SEN and LR2_DRV act as a
27
LR2_SEN
AIN
VSB5V
linear regulator and generate voltage for standby or STR power. Default
for standby power. If VIN is main power, it can generate voltage for S0
sate power.
Sense the voltage of linear regulator. LR1_SEN and LR1_DRV act as a
33
LR1_SEN
AIN
VSB5V
linear regulator and generate voltage for standby or STR power. Default
for standby power. If VIN is main power, it can generate voltage for S0
sate power.
Connect this pin to the gate of a suitable N-channel MOSFET.
34
LR1_DRV
AOUT
VSB9V
LR1_SEN and LR1_DRV act as a linear regulator and generate voltage
for standby or STR power. Default for standby power. If VIN is main
power, it can generate voltage for S0 sate power.
Connect this pin to the gate of a suitable N-channel MOSFET.
35
VPCIE_DRV
AOUT
VSB9V
VPCIE_SEN and VPCIE_DRV act as A linear regulator and generate
voltage for S0 state power.
36
VPCIE_SEN
AIN
VSB5V
Sense the voltage of linear regulator. VPCIE_SEN and VPCIE_DRV
act as a linear regulator and generate voltage for S0 state power.
Sense
37
DAUL3V_SEN
AIN
VSB5V
the
voltage
of
linear
regulator.
VDUAL3V_SEN
and
VDUAL3V_DRV act as an adjustable linear regulator and this regulator
is typically incorporated with VCCGATE to generate dual voltage.
Connect this pin to the gate of a suitable N-channel MOSFET.
38
DUAL3V_DRV
AOUT
VSB9V
VDUAL3V_SEN and VDUAL3V_DRV act as an adjustable linear
regulator and this regulator is typically incorporated with VCCGATE to
generate dual voltage.
Connect this pin to the gate of a suitable N-channel MOSFET.
This
39
VCCGATE
AOUT
VSB9V
pin
is
incorporated
with
pin38
and
39
(DUAL3V_DRV+DUAL3V_SEN) to generate dual 3.3V voltage.
Besides, this pin can be incorporated with pin41 (USBGATE) to
generate USB voltage. Incorporated with pin 42 (DUALGATE) to
generate dual 5V voltage.
40
USBGATE
AOUT
VSB9V
Connect this pin to the gate of a suitable N-channel MOSFET.
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Incorporated with pin 40 (VCCGATE) to generate USB voltage.
41
DUALGATE
AOUT
VSB9V
Connect this pin to the gate of a suitable N-channel MOSFET.
Incorporated with pin 40 (VCCGATE) to generate dual 5V voltage.
Charge Pump
PIN NO
PIN NAME
TYPE
PWR
28
CP
P
VSB9V
DESCRIPTION
Charge pump output (9V nominal). Decouple this pin with 1uF ceramic
capacitor. VSB9V power output.
29
C2
AOUT
VSB9V
31
C1
AOUT
VSB5V
Positive end of charge pump capacitor
Negative end of charge pump capacitor. Connect a 1uF ceramic capacitor
between C1 and C2
Power LED
PIN NO
PIN NAME
TYPE
PWR
6
PLED
OD24
VSB5V
Power LED. Can be programmed by setting register
7
SLED
OD24
VSB5V
Suspend LED. Can be programmed by setting register
PIN NO
PIN NAME
TYPE
PWR
4
SCLK
INts
VSB5V
I C serial bus clock (Address 5Eh)
5
SDATA
I/OD12ts
VSB5V
I C serial bus data
8
VREF
AOUT
VSB5V
Provide 1.25V reference voltage
23
SS
AIN
VSB5V
DESCRIPTION
Others
DESCRIPTION
2
2
Soft-Start. Connect this pin to a small ceramic capacitor to determine the
soft-start rate. The value of capacitor is bigger, the slew rate is slower.
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6 Functional Description
6.1 ACPI state
The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use of power in a
computer. It lets computer manufacturer and user to determine the computer’s power usage dynamically.
There are three ACPI states that are of primary concern to the system designer and they are designated S0,
S3 and S5. S0 is a full-power state and in this state, the computer is being actively used. The other two are called
sleep states and reflect different power consumption when power-down. S3 is a state the processor is powered
down but the last state is being stored in memory which is still active. S5 is a state that memory is off and the last
state of the processor has been stored to the hard disk. Take S3 and S5 as comparison, since memory is fast, the
computer can quickly come back to full-power state. But the disk is slower than the memory, the computer takes
longer time to come back to full-power state. However, since the memory is off, S5 draws the minimal power
comparing to S0 and S3.
It is anticipated that only the following state transitions may happen: S0→S3, S0→S5, S5→S0, S3→S0 and
S3→S5. Among them, S3→S5 is illegal transition and won’t be allowed by state machine. In order to get to S5 from
S3, it is necessary to enter S0 first. As for transition S5→S3 will occur only as an immediate state during state
transition from S5→S0. It isn’t allowed in the normal state transition.
6.2 Charge pump
The F72568 incorporated with an embedded charge pump to provide higher driving voltage. Pin 29(CP)
supports 10mA driving current and ensures 9V output voltage or above. In main operation, the VSB9V signals of
F72568 are run from the +12V supplied by ATX power which also supplies to other MOSFET gates. However,
during standby state, the +12V will be off and it needs to provide power to the chip and the appropriate gates.
Therefore F72568 incorporated with a free running charge pump. As shown in schematic, there is a capacitor
connected between C1 and C2 of the F72568 acts as a charge pump with internal diodes. The 12V input must has
a serial diode to prevent back-feeding the charge pump to the +12V main when in standby. It also needs a bypass
capacitor connected with 12V input line to filter high-frequency noise.
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6.3 Soft-start
SS of the F72568 acts as soft-start function. As shown in schematic, a ceramic capacitor is attached between this pin and
ground. When power is first applied to the chip, a constant current is applied from the pin into an external capacitor, linearly
ramping up the voltage. This ramp in turn controls the internal reference of F72568 providing a soft-start for linear controller. As
for switches, they must be either on or off in the system therefore soft-start has no effect on them. It is important to know
soft-start is not an enable signal; pulling it low will not be sure to turn off all outputs. But if there are appropriate signals asserted,
the switches will be turn on at once. The actual state of F72568 on power up will be determined by the controlled input signal.
And the soft-start is effective only during power on.
6.4 Reference voltage
The pin9 (VREF) is an output pin that is driven by a small output buffer to provide the 1.25V reference voltage to
other devices in the system.
6.5 Under Voltage Protection
If the FB voltage drops below 0.5V, a fault signal is generated. When under voltage condition occurs, the related
linear controller will shut down.
6.6 Over Current Protection
Sense the low-side MOSFET’s RDS (ON) to set over-current trip point. Connect a resistor (ROCSET) from this pin to the
PHASE to set the over-current trip point. ROCSET, an internal 40μA current source, and the lower MOSFET on
resistance, RDS (ON), set the converter over-current trip point (IOCSET) according to the following equation:
If over current occurs, the F72568 will shut down the PWM
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6.7 Access Interface
The F72568 can be connected to a compatible 2-wire serial system Management Bus (SMBus) as a slave device
under the control of the master device, using two device terminals SCLK and SDATA. The controller can provide a
clock signal to the device SCLK pin and read/write data from/to the device through the device SDATA pin. The
address default is 0x5E(0101_1110) and the operation of device to the bus is described with details in the following
sections.
(a) SMBus write to internal address register followed by the data byte
0
7
8
0
7
8
SCLK
SDATA
0
1
0
Start By
Master
1
1
1
R/W
1
D7
D6
Ack
by
568
Frame 1
Serial Bus Address Byte
D5
D4
D3
D2
D1
D0
Ack
by
568
Frame 2
Internal Index Register Byte
0
7
8
SCLK (Continued)
SDATA (Continued)
D7
D6
D5
D4
D3
D2
D1
D0
Stop
by
Master
Frame 3
Data Byte
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
(b) Serial bus write to internal address register only
0
7
8
0
7
8
SCLK
SDATA
0
1
Start By
Master
0
1
1
1
1
R/W
D7
D6
Ack
by
568
Frame 1
Serial Bus Address Byte
D5
D4
D3
D2
D1
D0
Ack
by
568
Frame 2
Internal Index Register Byte
Stop by
Master
0
Figure 2. Serial Bus Write to Internal Address Register Only
(c) Serial bus read from a register with the internal address register prefer to desired location
0
7
8
0
7
8
SCLK
SDATA
0
Start By
Master
1
0
1
1
1
1
R/W
D7
Ack
by
568
Frame 1
Serial Bus Address Byte
D6
D5
D4
D3
D2
Frame 2
Internal Index Register Byte
D1
D0
Ack
Stop by
by
Master Master
1
Figure 3. Serial Bus Read from Internal Address Register
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7 Register Description.
7.1
Register ⎯ Index 01h
Reserved register. Do not write the reserced register to avoid the mis-action, please.
7.2
Bit
PWM_VRAM_11, PWM_VRAM_10 Fine tune Voltage Register ⎯ Index 02h
Name
R/W
Default
Description
According to Turbo1hardware pin setting to fine tune PWM_VRAM
reference voltage. If Turbo = 1, the PWM_VRAM Voltage table is set by
Register 02h bit 7:4.
7:4
PWMVRAM_11
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
According to Turbo hardware pin setting to fine tune PWM_VRAM
reference voltage. If Turbo = 0, the PWM_VRAM Voltage table is set by
Register 02h bit 3:0.
3:0
PWMVRAM_10
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
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7.3
Register ⎯ Index 03h
Reserved register. Do not write the reserved register to avoid the mis-action, please.
7.4
Bit
PWM_VTT_10, PWM_VTT_11 Fine tune Voltage Register ⎯ Index 04h
Name
R/W
Default
Description
According to Turbo hardware pin setting to fine tune PWM_VTT
reference voltage. If Turbo = 1, the PWM_VTT Voltage table is set by
Register 04h bit 7:4.
7:4
PWMVTT_11
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
According to Turbo hardware pin setting to fine tune PWM_VTT
reference voltage. If Turbo = 0, the PWM_VTT Voltage table is set by
Register 04h bit 3:0
3:0
PWMVTT_10
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
7.5
Register ⎯ Index 05h
Reserved register. Do not write the reserved register to avoid the mis-action, please.
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7.6
Bit
LR_PCIE_10, LR_PCIE_11 Fine tune Voltage Register ⎯ Index 06h
Name
R/W
Default
Description
According to Turbo hardware pin setting to fine tune LR_PCIE
reference voltage. If Turbo = 1, the LR_PCIE Voltage table is set by
Register 06h bit 7:4.
7:4
LRPCIE_11
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
According to Turbo hardware pin setting to fine tune LR_PCIE
reference voltage. If Turbo = 0, the LR_PCIE Voltage table is set by
Register 06h bit 3:0
3:0
LR_PCIE_10
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
7.7
Register ⎯ Index 07h
Reserved register. Do not write the reserved register to avoid the mis-action, please.
12
2007 V0.25P
Fintek
Feature Integration Technology Inc.
F72568
7.8
Bit
LR3_10, LR3_11 Fine tune Voltage Register ⎯ Index 08h
Name
R/W
Default
Description
According to Turbo hardware pin setting to fine tune LRPCIE reference
voltage. If Turbo = 1, the LRPCIE Voltage table is set by Register 08h
bit 7:4.
7:4
LR3_11
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
According to Turbo hardware pin setting to fine tune LR3 reference
voltage. If Turbo =0, the LR3 Voltage table is set by Register 08h bit 3:0
3:0
LR3_10
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
7.9
LRPCIE_11, LR3_11 Fine tune Voltage Register ⎯ Index 09h
Bit
Name
R/W
Default
Description
7-6
USBMODE
R/W
1
USB Power mode select, 00:DUAL 01:STR 10:OFF 11:OFF
5
VRAM_MODE
R/W
1
VRAM Power mode select, 0 : VCC
4
VTT_MODE
R/W
0
VTT Power mode select, 0 : VCC 1: STR
13
1:STR
2007 V0.25P
Fintek
Feature Integration Technology Inc.
F72568
TURBO function Enable, if set to 1 the register 01~08h will enable fine
3
TURBO_EN
R/W
0
tune function when the fine tune setting is Turbo mode (Register 0A bit
3)
2
TURBO_INV
R/W
0
TURBO function sequence inverter.
TURBO_INV=0: If TURBO value changes from 0 to 1, it will fine tune
directly, Otherwise, it will delay 20ms to fine tune reference voltage.
TURBO_INV=1: If TURBO value changes from 1 to 0, it will fine tune
directly. Otherwise, it will delay 20ms to fine tune reference voltage
1
Reserved
R/W
0
Reserved
When register 09H bit 1 is set to FAULT_N mode, Set this bit to 1 to
0
FAULT_EN
R/W
0
enable FAULT Function, When FAULT_N is low in S0 State, it will Shut
down PWM_VRAM, PWM_VTT, LR_PCIE, LR_VID directly,.
7.10
Bit
PLED ACPI Frequency setting Register ⎯ Index 0Ah
Name
R/W
Default
Description
PLED frequency setting, When PLED_SET[9:8] set equal to S3_N,
7-6
PLED_SET[9:8]
R/W
0
S5_N, the PLED pin will be tri-state (OD)
*note : {1,1} represent S0 State, {1,0} represent S3 State, {00} represent
S5 State, {01} the state is reserved
3
5-4
SLED_SET[9:8]
SLED frequency setting, When SLED_SET[9:8] set equal to S3_N,
S5_N, the PLED pin will be tri-state (OD)
R/W
*note : {1,1} represent S0 State, {1,0} represent S3 State, {00} represent
S5 State, {01} the state is reserved
0
Manual mode or Turbo mode selection, 0:turbo 1:Manual
If the setting is Turbo mode, set register 09H bit 3 to enable the fine tune
3
VFB_SEL
R/W
function.
If the setting is Manual mode, Write Register 02/04/06/08 Bit [7:4] to fine
tune voltage.
2
LED_INV
R/W
1
Set to 1 , the PLED and SLED CLK is inverted
1
VRAM_OCEN
R/W
1
PWM_VRAM Over current enable
0
VTT_OCEN
R/W
1
PWM_VTT Over current enable
14
2007 V0.25P
Fintek
Feature Integration Technology Inc.
F72568
7.11
Bit
PLED ACPI Frequency setting Register ⎯ Index 0Bh
Name
R/W
Default
Description
PLED frequency setting, When the
PLED_SET[7:6] = S3_N, S5_N, PLED will be 1HZ toggle pulse with 50
duty cycle
PLED_SET[5:4] = S3_N, S5_N, PLED will be 1/2 HZ toggle pulse with
7-0
PLED_SET[7:0]
R/W
9B
50 duty cycle
PLED_SET[3:2] = S3_N, S5_N, PLED will be 1/4HZ toggle pulse with 50
duty cycle
PLED_SET[1:0] = S3_N, S5_N, PLED will drive low
*note : {1,1} represent S0 State, {0,1} represents S3 State ,
{0,0} represent S5 State, {1,0} is tri-state ,
7.12
Bit
SLED ACPI Frequency setting Register ⎯ Index 0Ch
Name
R/W
Default
Description
SLED frequency setting, When the
SLED_SET[7:6] = S3_N, S5_N, SLED will be 1HZ toggle pulse with 50
duty cycle
SLED_SET[5:4] = S3_N, S5_N, SLED will be 1/2 HZ toggle pulse with
7-0
SLED_SET[7:0]
R/W
98
50 duty cycle
SLED_SET[3:2] = S3_N, S5_N, SLED will be 1/4HZ toggle pulse with 50
duty cycle
SLED_SET[1:0] = S3_N, S5_N, SLED will drive low
*note : {1,1} represent S0 State, {0,1} represents S3 State ,
{0,0} represent S5 State, {1,0} is tri-state ,
7.13
Under Voltage, Over Current Enable Protection Register ⎯ Index 10h
Bit
Name
R/W
Default
Description
7
VPCIE_UVEN
R/W
1
VPCIE Under voltage enable
6
VID_UVEN
R/W
1
VID Under voltage enable
5
VDUAL3V_UVEN
R/W
1
VDUAL3V Under voltage enable
4
LR1_UVEN
R/W
1
LR1 Under voltage enable
15
2007 V0.25P
Fintek
Feature Integration Technology Inc.
F72568
3
LR2_UVEN
R/W
1
LR2 Under voltage enable
2
LR3_UVEN
R/W
1
LR3 Under voltage enable
1
PWM_VTT_UVEN
R/W
1
PWM_VTT Under voltage enable
PWM_VRAM_UVEN R/W
1
PWM_VRAM Under voltage enable
0
7.14
Register ⎯ Index 11h
Bit
Name
R/W
Default
Description
7
Reserved
R/W
0
Reserved
6
Reserved
R/W
0
Reserved
5
Reserved
R/W
0
Reserved
4
Reserved
R/W
0
Reserved
3
Reserved
R/W
0
Reserved
2
Reserved
R/W
0
Reserved
0
Reserved Function: when set to 1, it can decrease regulators VFB
voltage, it must fix the related fine tune register bit2, bit 3 to zero, for
example 100XX, It provide 4 kinds decrease voltage
1
DEC_VFB
R/W
10000 : 0.72V
10001 : 0.70V
10010 : 0.68V
10011 : 0.66V
0
0
PROTECTION_SEL
R/W
Set to 1 can toggle S5_N to recovery, if VRAM, VTT, LR_PCIE, LR_VID
Shut down by Over current or Under voltage or Fault_N SD , Set to 0,
must power off to recovery.
16
2007 V0.25P
Fintek
Feature Integration Technology Inc.
F72568
8 Electrical Characteristic
Absolute Maximum Ratings
PARAMETER
SYMBOL
RATINGS
UNIT
IC supply voltage
VCC
7
V
ESD classification
HBM
2
kV
※ Maximum junction temperature (plastic package)
Tj
※ Maximum storage temperature
- 0°C to 125°C
°C
-65~150
°C
260
°C
TSTO
※ Maximum lead temperature (soldering 10s)
Note: If ICs are stressed beyond the limits listed in the “absolute maximum ratings”, they may be permanently destroyed. These are stress ratings
only and functional operation of the device at these or any other condition beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
DC and AC electrical characteristics (VCC = 12V, TA = 25°C)
PARAMETER
SYMBOL TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
6
15
mA
VCC SUPPLY CURRENT/Regulated Voltage
Nominal supply current 5VCC
ICC
UGATE, LGATE and DRIVE2 open
POWER-ON RESET
Rising VCC threshold
3.0
3.3
3.6
V
Falling VCC threshold
2.7
3.0
3.3
V
200
250
300
kHz
OSCILLATOR AND Soft-start
Free running frequency
※ Ramp Amplitude
FOSC
1.5
△VOSC
VP-P
Soft-start interval
TSS
Css=0.1u
8.4
12.4
17.4
ms
Dead time
TDT
2V to 2V
20
30
50
ns
VREF
VCC=5V, T= 25
0.784
0.8
0.816
V
REFERENCE VOLTAGE
Reference voltage
PWM CONTROLLER GATE DRIVERS
Upper Drive Source
RUGATE
VDS = 1V, VGS = 12V,
7
14
Ω
Upper Drive Sink
RUGATE
VDS = 1V, VGS = 12V
5
10
Ω
Lower Drive Source
RLGATE
VDS = 1V, VGS = 12V
7
14
Ω
Lower Drive Sink
RLGATE
VDS = 1V, VGS = 12V
5
10
Ω
17
2007 V0.25P
Fintek
Feature Integration Technology Inc.
F72568
PARAMETER
SYMBOL TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Error Amplifier
Slew Rate
SR
4.5
V/us
※ DC Gain
A0
34
dB
70
dB
1.86
MHz
Slew Rate
38
V/us
Drive High Output Voltage
12
V
Drive Low Output Voltage
0
V
Linear Regulator
DC Gain
Gain Bandwidth Product
Drive High Output Source Current
Vo=9V; VDDA=10V
Drive Low Output Sink Current
Vo=1V; VDDA=10V
-0.54
mA
0.52
mA
40
uA
Protection
OCSET Current Source
IOCSET
FB Under Voltage Trip
FB Falling
0.4
0.5
0.6
V
VRAM(VDDQ) UV Level
0.4
0.5
0.6
V
VTT_PWM (VGMCH) UV Level
0.4
0.5
0.6
V
Charge Pump
Charge Pump Frequency
250
KHz
Charge Pump Voltage
9.5
V
9.5
V
Switch Controller
DUALGATE Output High Voltage
VCCGATE Output High Voltage
10.8
12
13.2
V
USBGATE SS Source Current
10.8
12
13.2
V
※: Design Guarantee
9 Ordering Information
Part Number
Package Type
Production Flow
F72568DG
48-LQFP Green Package
Commercial, 0°C to +70°C
18
2007 V0.25P
Fintek
Feature Integration Technology Inc.
F72568
10 Package Dimensions (48LQFP)
HD
D
25
36
Dimension in inch
Symbol
E
48
HE
13
1
e
b
Nom.
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
24
37
Min.
12
0
Max.
Dimension in mm
Min.
Nom.
Max.
---
---
1.60
0.05
---
0.15
1.35
1.40
1.45
0.17
0.20
0.27
0.09
---
0.20
7.00
7.00
0.50
9.00
9.00
0.45
0.60
0.75
1.00
---
0.08
---
0
3.5
7
Notes:
c
A2
Seating Plane
See Detail F
A
A1
y
L
L1
Detail F
1. Dimensions D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
Feature Integration Technology Inc.
Headquarters
Taipei Office
3F-7, No 36, Tai Yuan St.,
Bldg. K4, 7F, No.700, Chung Cheng Rd.,
Chupei City, Hsinchu, Taiwan 302, R.O.C.
Chungho City, Taipei, Taiwan 235, R.O.C.
TEL : 886-3-5600168
TEL : 866-2-8227-8027
FAX : 886-3-5600166
FAX : 866-2-8227-8037
www: http://www.fintek.com.tw
Please note that all datasheet and specifications are subject to change without notice. All the trade
marks of products and companies mentioned in this datasheet belong to their respective owner
19
2007 V0.25P
Fintek
Feature Integration Technology Inc.
F72568
11 Application Circuit
DUAL5V
VRAM_PWM CONTROL
VCC12V
VTT_PWM CONTROL
ATX Power Connector
VSB5V
-5V -12V
VCC3V
11
12
13
14
15
16
17
18
19
20
PS_ON#
C30
0.1uF
C5
1500uF
C6
1500uF
C7
4.7uF
3.3V
3.3V
-12V
3.3V
COM
COM
PS_ON
5V
COM
COM
COM
5V
COM
COM
-5V
PWR_OK
5V
5VSB
5V
12V
ATX
1
2
3
4
5
6
7
8
9
10
C9
470uF
R24
3.9k
VTT_PWM
PWROK
U2
6612
C15
10uF
8
7
6
5
UGATE PHASE
BOOT
PVCC
PWM
VCC
GND
LGATE
R7
VTT_FB
VCC12V
C19
10uF
1
2
3
4
R9
VTT_COMP
R11 10.7K C16
C18
470uF
C17
47n
R12
3.9k
1.2n
C13
VRAM_LGATE
4.7u
Q4
R6
2
47n
VRAM_OPS
C12
470uF*3
L3
VRAM_PWR for 1.8V
4.7u
R5
20k
C11
470uF
PWM_GND
VRAM_FB
C14
R10
PWM_GND
R14
C4
0.1uF
VRAM_PWR
Q3
R4
2
R8 10
3.4k
VTT_OPS
Q1
VTT_PWR
L4
VTT_PWR for 1.25V
10
R1
2
Q2
R3
2
C10
0.1uF
C1
C2
C3
1500uF1500uF4.7uF
C8
0.1uF
VRAM_UGATE
U1
R2
4.7k
PS_ON#
L1
1.2uH
L2
1.2uH
VCC5V
VCC5VVSB5V
47n
2.7K
R13
2.2K
20k
VCC12V
VSB5V
C20
0.1uF
PCIE_PWR
Q6
VPCIE_SEN
VPCIE_DRV
LR1_DRV
LR1_SEN
VBAT
PWOK
Q7
TURBO#
R22
FAULT#
3.9k
DUAL3V
VDUAL3V_SEN
VCC3V
C29
1000uF
R23
4.7k
R29
4.7k
SCLK
SDATA
USB POWER
C25 C26
0.1uF 0.1uF
VCC5V
VCC3V
R26
4.7k
R25
4.7k
F72568DG
VID_SEN
VID_DRV
VTT_OPS
VRAM_UGATE
VRAM_LGATE
VCC_PWM
VRAM_OPS
VRAM_FB
VTT_COMP
C27
0.1uF
VSB5V
VID POWER
SLP_S5#
PCIE_PWR
C28
0.1uF
VID_PWR
VTT_PWM
C31
1uF
Q8
VID_PWR
MOSFET N
VID_DRV
VID_SEN
R27
4.7k
R28
100
R30
200
VID_GD
C32
1000uF
PLED
SLED
VSB5V VCC5V
Q9
Q10
LR3_SEN
24
23
22
21
20
19
18
17
16
15
14
13
VTT_FB
PWROK
PS_ON#
C33
0.1uF
C42
1u
VCCGATE
USBGATE
LR3_SEN
SS
VID_SEN
VID_DRV
VTT_OPS
GND
VRAM_UGATE
VRAM_LGATE
VCC_PWM
VRAM_OPS
VRAM_FB
VTT_COMP
PWOKIN
PS_ONIN#
S5#
SCLK
SDATA
PLED
SLED
VREF
VID_GD
VSB5V
VTT_PWM
VTT_FB
VSB5V VCC3V
VCCGATE
VDUAL3V_DRV
RSMRST#
VDUAL3V_SEN
VDUAL3V_DRV
VCCGATE
USBGATE
DUALGATE
GND
RSMRST#
VBAT
PWOK
VCC3V
TURBO#
FAULT#
1
2
3
4
5
6
7
8
9
10
11
12
R21
10k
37
38
39
40
41
42
43
44
45
46
47
48
G
D
8
6
5
2
7
F
VDUAL3V_SEN
VDUAL3V_DRV
VCC3V VCCGATE
USBGATE
R19
DUALGATE
4.7k
R20
4.7k
DUAL3V
VPCIE_SEN
VPCIE_DRV
LR1_DRV
LR1_SEN
VSB5V
C1
GND
C2
CP
LR2_SEN
LR2_DRV
LR3_DRV
U3
VCC12V
DUAL POWER
36
35
34
33
32
31
30
29
28
27
26
25
C24
1000uF
R18
220
1uF
R17
200
D2
C22
VPCIE_SEN
1uF
VPCIE_DRV
PCIE_PWR
VCC_PWM
C21
VPCIE_PWR for 1.5V
Q5
R15
10
D1
LR2_SEN
LR2_DRV
LR3_DRV
VRAM_PWR
VSB5V
USB5V
C34
220uF
USB5V default for STR
VTT_PWR
LR3_PWR
DUAL3V
LR1_PWR
LR2_PWR
Q11
LR1_DRV
Q13
LR3_DRV
DUAL POWER
LR3_SEN
VSB5V VCC5V
VCCGATE
DUALGATE
Q14
Q15
R40
R
R41
R
VCC5V VSB5V
LED CONTROL
DUAL3V
LR3_PWR
LR2_DRV
LR2_SEN
R36
100
C38
220uF
R38
330
R33
330
LR2_PWR
LR1_PWR
LR1_SEN
C40
220uF
Q12
LR1_PWR for 1.05V
R37
R
R39
R
D3
LED
C39
220uF
PLED
R34
330
D4
LED
SLED
This power can support standby power
DUAL5V
This power can support standby power
C41
1000uF
Title
Size
C
Date:
<Title>
Document Number
F72568DG
Monday , March 12, 2007
Figure F72568 application circuit
20
2007 V0.25P
Rev
1.0
Sheet
1
of
1