W9412G6IH
2M × 4 BANKS × 16 BITS DDR SDRAM
Table of Contents1.
GENERAL DESCRIPTION ......................................................................................................... 4
2.
FEATURES ................................................................................................................................. 4
3.
KEY PARAMETERS ................................................................................................................... 5
4.
PIN CONFIGURATION ............................................................................................................... 6
5.
PIN DESCRIPTION..................................................................................................................... 7
6.
BLOCK DIAGRAM ...................................................................................................................... 8
7.
FUNCTIONAL DESCRIPTION.................................................................................................... 9
7.1
Power Up Sequence....................................................................................................... 9
7.2
Command Function ...................................................................................................... 10
7.2.1
Bank Activate Command ........................................................................... 10
7.2.2
Bank Precharge Command........................................................................ 10
7.2.3
Precharge All Command............................................................................ 10
7.2.4
Write Command ......................................................................................... 10
7.2.5
Write with Auto-precharge Command........................................................ 10
7.2.6
Read Command ......................................................................................... 10
7.2.7
Read with Auto-precharge Command ....................................................... 10
7.2.8
Mode Register Set Command.................................................................... 11
7.2.9
Extended Mode Register Set Command ................................................... 11
7.2.10
No-Operation Command............................................................................ 11
7.2.11
Burst Read Stop Command ....................................................................... 11
7.2.12
Device Deselect Command ....................................................................... 11
7.2.13
Auto Refresh Command ............................................................................ 11
7.2.14
Self Refresh Entry Command .................................................................... 12
7.2.15
Self Refresh Exit Command....................................................................... 12
7.2.16
Data Write Enable /Disable Command ...................................................... 12
7.3
Read Operation............................................................................................................. 12
7.4
Write Operation............................................................................................................. 13
7.5
Precharge ..................................................................................................................... 13
7.6
Burst Termination.......................................................................................................... 13
7.7
Refresh Operation......................................................................................................... 13
7.8
Power Down Mode ....................................................................................................... 14
7.9
Input Clock Frequency Change during Precharge Power Down Mode........................ 14
7.10
Mode Register Operation.............................................................................................. 14
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8.
9.
10.
11.
7.10.1
Burst Length field (A2 to A0)...................................................................... 14
7.10.2
Addressing Mode Select (A3) .................................................................... 15
7.10.3
CAS Latency field (A6 to A4) ..................................................................... 16
7.10.4
DLL Reset bit (A8) ..................................................................................... 16
7.10.5
Mode Register/Extended Mode register change bits (BA0, BA1).............. 16
7.10.6
Extended Mode Register field.................................................................... 16
7.10.7
Reserved field ............................................................................................ 16
OPERATION MODE ................................................................................................................. 17
8.1
Simplified Truth Table................................................................................................... 17
8.2
Function Truth Table..................................................................................................... 18
8.3
Function Truth Table for CKE ....................................................................................... 21
8.4
Simplified Stated Diagram ............................................................................................ 22
ELECTRICAL CHARACTERISTICS......................................................................................... 23
9.1
Absolute Maximum Ratings .......................................................................................... 23
9.2
Recommended DC Operating Conditions .................................................................... 23
9.3
Capacitance .................................................................................................................. 24
9.4
Leakage and Output Buffer Characteristics.................................................................. 24
9.5
DC Characteristics ........................................................................................................ 25
9.6
AC Characteristics and Operating Condition................................................................ 26
9.7
AC Test Conditions....................................................................................................... 27
SYSTEM CHARACTERISTICS FOR DDR SDRAM................................................................. 30
10.1
Table 1: Input Slew Rate for DQ, DQS, and DM .......................................................... 30
10.2
Table 2: Input Setup & Hold Time Derating for Slew Rate ........................................... 30
10.3
Table 3: Input/Output Setup & Hold Time Derating for Slew Rate ............................... 30
10.4
Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate................ 30
10.5
Table 5: Output Slew Rate Characteristics (X16 Devices only) ................................... 30
10.6
Table 6: Output Slew Rate Matching Ratio Characteristics ......................................... 31
10.7
Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins......... 31
10.8
Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins.......... 32
10.9
System Notes:............................................................................................................... 33
TIMING WAVEFORMS ............................................................................................................. 35
11.1
Command Input Timing ................................................................................................ 35
11.2
Timing of the CLK Signals ............................................................................................ 35
11.3
Read Timing (Burst Length = 4) ................................................................................... 36
11.4
Write Timing (Burst Length = 4).................................................................................... 37
11.5
DM, DATA MASK (W9412G6IH) .................................................................................. 38
11.6
Mode Register Set (MRS) Timing................................................................................. 39
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12.
11.7
Extend Mode Register Set (EMRS) Timing .................................................................. 40
11.8
Auto-precharge Timing (Read Cycle, CL = 2) .............................................................. 41
11.9
Auto-precharge Timing (Read cycle, CL = 2), continued ............................................. 42
11.10
Auto-precharge Timing (Write Cycle).......................................................................... 43
11.11
Read Interrupted by Read (CL = 2, BL = 2, 4, 8) ........................................................ 44
11.12
Burst Read Stop (BL = 8) ............................................................................................ 44
11.13
Read Interrupted by Write & BST (BL = 8).................................................................. 45
11.14
Read Interrupted by Precharge (BL = 8) ..................................................................... 45
11.15
Write Interrupted by Write (BL = 2, 4, 8) ..................................................................... 46
11.16
Write Interrupted by Read (CL = 2, BL = 8) ................................................................ 46
11.17
Write Interrupted by Read (CL = 3, BL = 4) ................................................................ 47
11.18
Write Interrupted by Precharge (BL = 8) ..................................................................... 47
11.19
2 Bank Interleave Read Operation (CL = 2, BL = 2) ................................................... 48
11.20
2 Bank Interleave Read Operation (CL = 2, BL = 4) ................................................... 48
11.21
4 Bank Interleave Read Operation (CL = 2, BL = 2) ................................................... 49
11.22
4 Bank Interleave Read Operation (CL = 2, BL = 4) ................................................... 49
11.23
Auto Refresh Cycle ..................................................................................................... 50
11.24
Precharged/Active Power Down Mode Entry and Exit Timing .................................... 50
11.25
Input Clock Frequency Change during Precharge Power Down Mode Timing .......... 50
11.26
Self Refresh Entry and Exit Timing ............................................................................. 51
Package Specification............................................................................................................... 52
12.1
13.
66L TSOP – 400 mil ..................................................................................................... 52
REVISION HISTORY ................................................................................................................ 53
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1. GENERAL DESCRIPTION
W9412G6IH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM); organized as 2M words × 4 banks × 16 bits. W9412G6IH delivers a data bandwidth of up to
500M words per second (-4). To fully comply with the personal computer industrial standard,
W9412G6IH is sorted into the following speed grades: -4, -5, -5I, -6 and -6I. The -4 is compliant to the
DDR500/CL3 and CL4 specification. The -5/-5I is compliant to the DDR400/CL3 specification (the -5I
grade which is guaranteed to support -40°C ~ 85°C). The -6/-6I is compliant to the DDR333/CL2.5
specification (the -6I grade which is guaranteed to support -40°C ~ 85°C).
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. Write and
Read data are synchronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9412G6IH is ideal for main memory in
high performance applications.
2. FEATURES
•
2.5V ±0.2V Power Supply for DDR333/400
•
2.5V ±0.1V Power Supply for DDR500
•
Up to 250 MHz Clock Frequency
•
Double Data Rate architecture; two data transfers per clock cycle
•
Differential clock inputs (CLK and CLK )
•
DQS is edge-aligned with data for Read; center-aligned with data for Write
•
CAS Latency: 2, 2.5, 3 and 4
•
Burst Length: 2, 4 and 8
•
Auto Refresh and Self Refresh
•
Precharged Power Down and Active Power Down
•
Write Data Mask
•
Write Latency = 1
•
15.6µS Refresh interval (4K/64 mS Refresh)
•
Maximum burst refresh cycle: 8
•
Interface: SSTL_2
•
Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant
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W9412G6IH
3. KEY PARAMETERS
SYMBOL
DESCRIPTION
CL = 2
CL = 2.5
tCK
Clock Cycle Time
CL = 3
CL = 4
MIN./MAX.
-4
-5/-5I
-6/-6I
Min.
-
7.5 nS
7.5 nS
Max.
-
12 nS
12 nS
Min.
-
6 nS
6 nS
Max.
-
12 nS
12 nS
Min.
4 nS
5 nS
6 nS
Max.
12 nS
12 nS
12 nS
Min.
4 nS
-
-
Max.
12 nS
-
-
tRAS
Active to Precharge Command Period
Min.
40 nS
40 nS
42 nS
tRC
Active to Ref/Active Command Period
Min.
48 nS
50 nS
54 nS
Max.
130 mA
130 mA
120 mA
Max.
140 mA
140 mA
130 mA
IDD0
IDD1
Operating Current:
One Bank Active-Precharge
Operating Current:
One Bank Active-Read-Precharge
IDD4R
Burst Operation Read Current
Max.
185 mA
180 mA
170 mA
IDD4W
Burst Operation Write Current
Max.
185 mA
180 mA
170 mA
IDD5
Auto Refresh Current
Max.
200 mA
200 mA
190 mA
IDD6
Self Refresh Current
Max.
3 mA
3 mA
3 mA
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Publication Release Date: Sep. 16, 2009
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4. PIN CONFIGURATION
VDD
1
66
VSS
DQ15
DQ0
2
65
VDDQ
3
64
VSSQ
DQ1
4
63
DQ14
DQ2
5
62
DQ13
VSSQ
6
61
VDDQ
DQ3
7
60
DQ12
DQ4
8
59
DQ11
VDDQ
9
58
VSSQ
DQ5
10
57
DQ10
DQ6
11
56
DQ9
VSSQ
12
55
VDDQ
DQ7
13
54
DQ8
NC
14
53
NC
VDDQ
15
52
VSSQ
LDQS
16
51
UDQS
NC
17
50
NC
VDD
18
49
VREF
NC
19
48
VSS
LDM
20
47
UDM
WE
21
46
CLK
CAS
22
45
CLK
RAS
23
44
CKE
CS
24
43
NC
NC
25
42
NC
BA0
26
41
A11
BA1
27
40
A9
A10/AP
28
39
A8
A0
29
38
A7
A1
30
37
A6
A2
31
36
A5
A3
32
35
A4
VDD
33
34
VSS
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Publication Release Date: Sep. 16, 2009
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5. PIN DESCRIPTION
PIN NUMBER
PIN
NAME
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
28 − 32,
35 − 41
A0 − A11
26, 27
BA0, BA1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during column address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 54, 56, 57,
59, 60, 62, 63, 65
DQ0 −
DQ15
Data Input/ Output
The DQ0 – DQ15 input and output data are synchronized
with both edges of DQS.
16,51
LDQS,
UDQS
Data Strobe
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edgealigned with read data, Center-aligned with write data.
24
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
23, 22, 21
Address
Row address: A0 − A11.
Column address: A0 − A8. (A10 is used for Auto-precharge)
RAS ,
CAS , WE
Command Inputs
Command inputs (along with CS ) define the command
being entered.
LDM, UDM
Write Mask
When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
CLK,
CLK
Differential Clock
Inputs
All address and control input signals are sampled on the
crossing of the positive edge of CLK and negative edge of
CLK .
44
CKE
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
49
VREF
1, 18, 33
VDD
Power (+2.5V)
Power for logic circuit inside DDR SDRAM.
34, 48, 66
VSS
Ground
Ground for logic circuit inside DDR SDRAM.
3, 9, 15, 55, 61
VDDQ
6, 12, 52, 58, 64
VSSQ
Ground for I/O
Buffer
NC
No Connection
20, 47
45, 46
14, 17, 19, 25,
42, 43, 50, 53
Reference Voltage VREF is reference voltage for inputs.
Power (+2.5V) for Separated power from VDD, used for output buffer, to
improve noise.
I/O Buffer
Separated ground from VSS, used for output buffer, to
improve noise.
No connection (NC pin should be connected to GND or
floating)
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6. BLOCK DIAGRAM
CLK
CLK
DLL
CLOCK
BUFFER
CKE
CONTROL
CS
CAS
SIGNAL
GENERATOR
COMMAND
DECODER
COLUMN DECODER
ROW DECODER
WE
A10
MODE
REGISTER
A0
CELL ARRAY
BANK #0
COLUMN DECODER
ROW DECODER
RAS
CELL ARRAY
BANK #1
SENSE AMPLIFIER
SENSE AMPLIFIER
ADDRESS
BUFFER
PREFETCH REGISTER
DQ
DATA CONTROL
BUFFER
DQ0
DQ15
CIRCUIT
COLUMN
COUNTER
COUNTER
LDQS
UDQS
LDM
UDM
COLUMN DECODER
CELL ARRAY
BANK #2
COLUMN DECODER
ROW DECODER
REFRESH
ROW DECODER
A9
A11
BA0
BA1
SENSE AMPLIFIER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE: The cell array configuration is 4096 * 512 * 16
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7. FUNCTIONAL DESCRIPTION
7.1
Power Up Sequence
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Apply power and attempt to CKE at a low state ( ≤ 0.2V), all other inputs may be undefined
1) Apply VDD before or at the same time as VDDQ.
2) Apply VDDQ before or at the same time as VTT and VREF.
Start Clock and maintain stable condition for 200 µS (min.).
After stable power and clock, apply NOP and take CKE high.
Issue precharge command for all banks of the device.
Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type.
Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.
(An additional 200 cycles(min) of clock are required for DLL Lock before any executable
command applied.)
Issue precharge command for all banks of the device.
Issue two or more Auto Refresh commands.
Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low.
CLK
CLK
Command
PREA
EMRS
tRP
MRS
2 Clock min.
PREA
2 Clock min.
AREF
tRP
AREF
tRFC
ANY
CMD
MRS
tRFC
2 Clock min.
200 Clock min.
Inputs
maintain stable
for 200 µS min.
Enable DLL
Disable DLL reset with A8 = Low
DLL reset with A8 = High
Initialization sequence after power-up
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7.2
Command Function
7.2.1
Bank Activate Command
( RAS = “L”, CAS = “H”, WE = “H”, BA0, BA1 = Bank, A0 to A11 = Row Address)
The Bank Activate command activates the bank designated by the BA (Bank address) signal. Row
addresses are latched on A0 to A11 when this command is issued and the cell data is read out of
the sense amplifiers. The maximum time that each bank can be held in the active state is specified
as tRAS (max). After this command is issued, Read or Write operation can be executed.
7.2.2
Bank Precharge Command
( RAS = “L”, CAS = “H”, WE = “L”, BA0, BA1 = Bank, A10 = “L”, A0 to A9, A11 = Don’t Care)
The Bank Precharge command percharges the bank designated by BA. The precharged bank is
switched from the active state to the idle state.
7.2.3
Precharge All Command
( RAS = “L”, CAS = “H”, WE = “L”, BA0, BA1 = Don’t Care, A10 = “H”, A0 to A9, A11 = Don’t
Care)
The Precharge All command precharges all banks simultaneously. Then all banks are switched to
the idle state.
7.2.4
Write Command
( RAS = “H”, CAS = “L”, WE = “L”, BA0, BA1 = Bank, A10 = “L”, A0 to A8 = Column Address)
The write command performs a Write operation to the bank designated by BA. The write data are
latched at both edges of DQS. The length of the write data (Burst Length) and column access
sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write
operation.
7.2.5
Write with Auto-precharge Command
( RAS = “H”, CAS = “L”, WE = “L”, BA0, BA1 = Bank, A10 = “H”, A0 to A8 = Column Address)
The Write with Auto-precharge command performs the Precharge operation automatically after the
Write operation. This command must not be interrupted by any other commands.
7.2.6
Read Command
( RAS = “H”, CAS = “L”, WE = “H”, BA0, BA1 = Bank, A10 = “L”, A0 to A8 = Column Address)
The Read command performs a Read operation to the bank designated by BA. The read data are
synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode
and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the
Mode Register at power-up prior to the Read operation.
7.2.7
Read with Auto-precharge Command
( RAS = “H”, CAS = ”L”, WE = ”H”, BA0, BA1 = Bank, A10 = ”H”, A0 to A8 = Column Address)
The Read with Auto-precharge command automatically performs the Precharge operation after the
Read operation.
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1) READA ≥ tRAS (min) - (BL/2) x tCK
Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command.
2) tRCD(min) ≤ READA < tRAS(min) - (BL/2) x tCK
Data can be read with shortest latency, but the internal Precharge operation does not begin until
after tRAS (min) has completed.
This command must not be interrupted by any other command.
7.2.8
Mode Register Set Command
( RAS = “L”, CAS = “L”, WE = “L”, BA0 = “L”, BA1 = “L”, A0 to A11 = Register Data)
The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst
Length and DLL reset in the Mode Register. The default values in the Mode Register after powerup are undefined, therefore this command must be issued during the power-up sequence. Also,
this command can be issued while all banks are in the idle state. Refer to the table for specific
codes.
7.2.9
Extended Mode Register Set Command
( RAS = “L”, CAS = “L”, WE = “L”, BA0 = “H”, BA1 = “L”, A0 to A11 = Register data)
The Extended Mode Register Set command can be implemented as needed for function
extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL
enable/disable, decoded by A0. The default value of the extended mode register is not defined;
therefore this command must be issued during the power-up sequence for enabling DLL. Refer to
the table for specific codes.
7.2.10 No-Operation Command
( RAS = “H”, CAS = “H”, WE = “H”)
The No-Operation command simply performs no operation (same command as Device Deselect).
7.2.11 Burst Read Stop Command
( RAS = “H”, CAS = “H”, WE = “L”)
The Burst stop command is used to stop the burst operation. This command is only valid during a
Burst Read operation.
7.2.12 Device Deselect Command
( CS = “H”)
The Device Deselect command disables the command decoder so that the RAS , CAS ,
WE and Address inputs are ignored. This command is similar to the No-Operation command.
7.2.13 Auto Refresh Command
( RAS = “L”, CAS = “L”, WE = “H”, CKE = “H”, BA0, BA1, A0 to A11 = Don’t Care)
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS–
BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it
must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address
bits ”Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO RE-
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FRESH cycles at an average periodic interval of tREFI (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be
posted to any given DDR SDRAM, and the maximum absolute interval between any AUTO
REFRESH command and the next AUTO REFRESH command is 8 * tREFI.
7.2.14 Self Refresh Entry Command
( RAS = “L”, CAS = “L”, WE = “H”, CKE = “L”, BA0, BA1, A0 to A11 = Don’t Care)
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of
the system is powered down. When in the self refresh mode, the DDR SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF
REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is
enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command
can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is a
SSTL_2 input, VREF must be maintained during SELF REFRESH.
7.2.15 Self Refresh Exit Command
(CKE = “H”, CS = “H” or CKE = “H”, RAS = “H”, CAS = “H”)
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be
stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP
commands issued for tXSNR because time is required for the completion of any internal refresh in
progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for
200 clock cycles before applying any other command.
The use of SELF REFREH mode introduces the possibility that an internally timed event can be
missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an
extra auto refresh command is recommended.
7.2.16 Data Write Enable /Disable Command
(DM = “L/H” or LDM, UDM = “L/H”)
During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every
word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to
DQ15.
7.3
Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read
command is issued after tRCD from the Bank Activate command, the data is read out sequentially,
synchronized with both edges of DQS (Burst Read operation). The initial read data becomes
available after CAS Latency from the issuing of the Read command. The CAS Latency must be set
in the Mode Register at power-up.
When the Precharge Operation is performed on a bank during a Burst Read and operation, the
Burst operation is terminated.
When the Read with Auto-precharge command is issued, the Precharge operation is performed
automatically after the Read cycle then the bank is switched to the idle state. This command
cannot be interrupted by any other commands. Refer to the diagrams for Read operation.
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7.4
Write Operation
Issuing the Write command after tRCD from the bank activate command. The input data is latched
sequentially, synchronizing with both edges(rising & falling) of DQS after the Write command
(Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode
must be set in the Mode Register at power-up.
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst
operation is terminated.
When the Write with Auto-precharge command is issued, the Precharge operation is performed
automatically after the Write cycle, then the bank is switched to the idle state, The Write with Autoprecharge command cannot be interrupted by any other command for the entire burst data
duration.
Refer to the diagrams for Write operation.
7.5
Precharge
There are two Commands, which perform the precharge operation (Bank Precharge and
Precharge All). When the Bank Precharge command is issued to the active bank, the bank is
precharged and then switched to the idle state. The Bank Precharge command can precharge one
bank independently of the other bank and hold the unprecharged bank in the active state. The
maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each
bank must be precharged within tRAS(max) from the bank activate command.
The Precharge All command can be used to precharge all banks simultaneously. Even if banks
are not in the active state, the Precharge All command can still be issued. In this case, the
Precharge operation is performed only for the active bank and the precharge bank is then
switched to the idle state.
7.6
Burst Termination
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is
terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is
disabled after clock cycle of (CAS Latency) from the Precharge command. When the Burst Write
cycle is interrupted by the Precharge command, the input circuit is reset at the same clock cycle at
which the precharge command is issued. In this case, the DM signal must be asserted “high”
during tWR to prevent writing the invalided data to the cell array.
When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read
operation is terminated. The Burst read Stop command is not supported during a write burst
operation. Refer to the diagrams for Burst termination.
7.7
Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh.
By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh
operation must be performed 4096 times (rows) within 64mS. The period between the Auto
Refresh command and the next command is specified by tRFC.
Self Refresh mode enters issuing the Self Refresh command (CKE asserted “low”) while all banks
are in the idle state. The device is in Self Refresh mode for as long as CKE held “low”. In the case
of distributed Auto Refresh commands, distributed auto refresh commands must be issued every
15.6 µS and the last distributed Auto Refresh commands must be performed within 15.6 µS before
entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation
must be performed within 15.6 µS. In Self Refresh mode, all input/output buffers are disabled,
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Revision A06
W9412G6IH
resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh
operation.
7.8
Power Down Mode
Two types of Power Down Mode can be performed on the device: Active Standby Power Down
Mode and Precharge Standby Power Down Mode.
When the device enters the Power Down Mode, all input/output buffers are disabled resulting in
low power dissipation (except CKE buffer).
Power Down Mode enter asserting CKE “low” while the device is not running a burst cycle. Taking
CKE “high” can exit this mode. When CKE goes high, a No operation command must be input at
next CLK rising edge. Refer to the diagrams for Power Down Mode.
7.9
Input Clock Frequency Change during Precharge Power Down Mode
DDR SDRAM input clock frequency can be changed under following condition:
DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a
minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency
between minimum and maximum operating frequency specified for the particular speed grade.
During an input clock frequency change, CKE must be held LOW. Once the input clock frequency
is changed, a stable clock must be provided to DRAM before precharge power down mode may be
exited. The DLL must be RESET via EMRS after precharge power down exit. An additional MRS
command may need to be issued to appropriately set CL etc. After the DLL relock time, the DRAM
is ready to operate with new clock frequency.
7.10 Mode Register Operation
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all
banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to
A11 and BA0, BA1 address inputs.
The Mode Register designates the operation mode for the read or write cycle. The register is
divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode
selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set
the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode
Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented
the extended function (DLL enable/Disable mode).
The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the
Mode Register Set command must be issued before power operation.
7.10.1 Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2, 4 and 8 words.
A2
A1
A0
BURST LENGTH
0
0
0
Reserved
0
0
1
2 words
0
1
0
4 words
0
1
1
8 words
1
x
x
Reserved
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Revision A06
W9412G6IH
7.10.2 Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the
A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both
addressing Mode support burst length 2, 4 and 8 words.
A3
ADDRESSING MODE
0
Sequential
1
Interleave
7.10.2.1. Addressing Sequence of Sequential Mode
A column access is performed by incrementing the column address input to the device. The
address is varied by the Burst Length as the following.
Addressing Sequence of Sequential Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
n
2 words (address bits is A0)
Data 1
n+1
not carried from A0 to A1
Data 2
n+2
4 words (address bit A0, A1)
Data 3
n+3
Not carried from A1 to A2
Data 4
n+4
Data 5
n+5
8 words (address bits A2, A1 and A0)
Data 6
n+6
Not carried from A2 to A3
Data 7
n+7
7.10.2.2. Addressing Sequence for Interleave Mode
A Column access is started from the inputted column address and is performed by interleaving the
address bits in the sequence shown as the following.
Addressing Sequence of Interleave Mode
DATA
ACCESS ADDRESS
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
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BURST LENGTH
2 words
4 words
8 words
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
7.10.3 CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of CAS Latency depend on the frequency of CLK.
A6
A5
A4
CAS LATENCY
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
4
Reserved
2.5
Reserved
7.10.4 DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset.
7.10.5 Mode Register/Extended Mode register change bits (BA0, BA1)
These bits are used to select MRS/EMRS.
BA1
BA0
A11-A0
0
0
1
0
1
x
Regular MRS Cycle
Extended MRS Cycle
Reserved
7.10.6 Extended Mode Register field
1) DLL Switch field (A0)
This bit is used to select DLL enable or disable
A0
DLL
0
1
Enable
Disable
2) Output Driver Strength Control field (A6, A1)
The 100%, 60% and 30% or matched impedance driver strength are required Extended Mode
Register Set (EMRS) as the following:
A6
A1
BUFFER STRENGTH
0
0
1
1
0
1
0
1
100% Strength
60% Strength
Reserved
30% Strength
7.10.7 Reserved field
• Test mode entry bit (A7)
This bit is used to enter Test mode and must be set to “0” for normal operation.
• Reserved bits (A9, A10, A11)
These bits are reserved for future operations. They must be set to “0” for normal operation.
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Publication Release Date: Sep. 16, 2009
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W9412G6IH
8. OPERATION MODE
The following table shows the operation commands.
8.1
Simplified Truth Table
SYM.
COMMAND
ACT
DEVICE
STATE
Bank Active
PRE
Bank Precharge
PREA
Precharge All
Idle
(3)
(3)
Any
CKEn-1 CKEn
H
DM
X
(4)
X
BA0,
BA1
A10
A0-A9
,A11
CS
RAS
CAS
WE
V
V
V
L
L
H
H
H
X
X
V
L
X
L
L
H
L
H
X
X
X
H
X
L
L
H
L
(3)
H
X
X
V
L
V
L
H
L
L
(3)
H
X
X
V
H
V
L
H
L
L
(3)
H
X
X
V
L
V
L
H
L
H
(3)
Any
WRIT
Write
Active
WRITA
Write with Autoprecharge
Active
READ
Read
Active
READA
Read with Autoprecharge
Active
H
X
X
V
H
V
L
H
L
H
Mode Register Set
Idle
H
X
X
L, L
C
C
L
L
L
L
EMRS
Extended Mode
Register Set
Idle
H
X
X
H, L
V
V
L
L
L
L
NOP
No Operation
Any
H
X
X
X
X
X
L
H
H
H
BST
Burst Read Stop
Active
H
X
X
X
X
X
L
H
H
L
DSL
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AREF
Auto Refresh
Idle
H
H
X
X
X
X
L
L
L
H
SELF
Self Refresh
Entry
Idle
H
L
X
X
X
X
L
L
L
H
SELEX
Self Refresh Exit
Idle (Self
Refresh)
L
H
X
X
X
X
PD
Power Down
Mode Entry
Idle/
(5)
Active
H
L
X
X
X
X
Power Down
Mode Exit
Any
(Power
Down)
MRS
PDEX
L
H
X
X
X
X
H
X
X
X
L
H
H
X
H
X
X
X
L
H
H
X
H
X
X
X
L
H
H
X
WDE
Data Write Enable
Active
H
X
L
X
X
X
X
X
X
X
WDD
Data Write Disable
Active
H
X
H
X
X
X
X
X
X
X
Notes:
1. V = Valid
X = Don’t Care
L = Low level
H = High level
2. CKEn signal is input level when commands are issued.
CKEn-1 signal is input level one clock cycle before the commands are issued.
3. These are state designated by the BA0, BA1 signals.
4. LDM, UDM (W9412G6IH).
5. Power Down Mode can not entry in the burst cycle.
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
8.2
Function Truth Table
(Note 1)
CURRENT
STATE
Idle
Row Active
Read
Write
CS RAS
CAS
WE
ADDRESS
COMMAND
ACTION
NOTES
H
X
X
X
X
DSL
NOP
L
H
H
X
X
NOP/BST
NOP
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
Row activating
L
L
H
L
BA, A10
PRE/PREA
NOP
L
L
L
H
X
AREF/SELF
Refresh or Self refresh
2
L
L
L
L
Op-Code
MRS/EMRS
Mode register accessing
2
H
X
X
X
X
DSL
NOP
L
H
H
X
X
NOP/BST
NOP
L
H
L
H
BA, CA, A10
READ/READA
Begin read: Determine AP
4
L
H
L
L
BA, CA, A10
WRIT/WRITA
Begin write: Determine AP
4
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
Precharge
5
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
Burst stop
L
H
L
H
BA, CA, A10
READ/READA
Term burst, new read: Determine AP
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE/PREA
Term burst, Precharging
6
3
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
Term burst, start read: Determine AP
6, 7
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst, start read: Determine AP
6
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
Term burst, Precharging
8
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
Function Truth Table, continued
CURRENT
STATE
CS
H
Read with
Autoprecharge
Write with
Autoprecharge
Precharging
Row
Activating
RAS
X
CAS
WE
X
X
ADDRESS
X
COMMAND
DSL
ACTION
NOTES
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
NOP-> Idle after tRP
L
H
H
H
X
NOP
NOP-> Idle after tRP
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
Idle after TRP
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
NOP-> Row active after tRCD
L
H
H
H
X
NOP
NOP-> Row active after tRCD
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
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3
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
Function Truth Table, continued
CURRENT
STATE
Write
Recovering
Write
Recovering
with Autoprecharge
Refreshing
Mode
Register
Accessing
CS
RAS
CAS
WE
ADDRESS
COMMAND
ACTION
NOTES
H
X
X
X
X
DSL
NOP->Row active after tWR
L
H
H
H
X
NOP
NOP->Row active after tWR
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
NOP->Enter precharge after
tWR
L
H
H
H
X
NOP
NOP->Enter precharge after
tWR
L
H
H
L
X
BST
ILLEGAL
3
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
NOP->Idle after tRC
H
X
X
X
X
DSL
L
H
H
H
X
NOP
NOP->Idle after tRC
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
X
READ/WRIT
ILLEGAL
L
L
H
X
X
ACT/PRE/PREA
ILLEGAL
L
L
L
X
X
AREF/SELF/MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
NOP->Row after tMRD
L
H
H
H
X
NOP
NOP->Row after tMRD
L
H
H
L
X
BST
ILLEGAL
L
H
L
X
X
READ/WRIT
ILLEGAL
X
ACT/PRE/PREA/ARE
F/SELF/MRS/EMRS
ILLEGAL
L
L
X
X
Notes:
1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle.
2. Illegal if any bank is not idle.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
4. Illegal if tRCD is not satisfied.
5. Illegal if tRAS is not satisfied.
6. Must satisfy burst interrupt condition.
7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.
8. Must mask preceding data which don’t satisfy tWR
Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
8.3
Function Truth Table for CKE
CURRENT
STATE
Self Refresh
Power Down
All banks Idle
Row Active
Any State
Other Than
Listed Above
CKE
n-1
n
CS
RAS
CAS WE
ADDRESS
ACTION
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self Refresh->Idle after tXSNR
NOTES
L
H
L
H
H
X
X
Exit Self Refresh->Idle after tXSNR
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
Maintain Self Refresh
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power down->Idle after tIS
L
L
X
X
X
X
X
Maintain power down mode
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
H
X
X
X
X
Enter Power down
2
H
L
L
H
H
X
X
Enter Power down
2
1
H
L
L
L
L
H
X
Self Refresh
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Power down
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
H
X
X
X
X
Enter Power down
3
H
L
L
H
H
X
X
Enter Power down
3
H
L
L
L
L
H
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Power down
H
H
X
X
X
X
X
Refer to Function Truth Table
Notes:
1. Self refresh can enter only from the all banks idle state.
2. Power Down occurs when all banks are idle; this mode is referred to as precharge power down.
3. Power Down occurs when there is a row active in any bank; this mode is referred to as active power down.
Remark:
H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
8.4
Simplified Stated Diagram
SELF
REFRESH
SREF
SREFX
MRS/EMRS
MODE
REGISTER
SET
AREF
IDLE
AUTO
REFRESH
PD
PDEX
ACT
POWER
DOWN
ACTIVE
POWERDOWN
PDEX
PD
ROW
ACTIVE
BST
Read
Write
Write
Read
Write
Read
Read
Read A
Write A
Read A
Write A
Read A
PRE
Write A
POWER
APPLIED
POWER
ON
PRE
PRE
PRE
Read A
PRE
CHARGE
Automatic Sequence
Command Sequence
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
9. ELECTRICAL CHARACTERISTICS
9.1
Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
Input/Output Voltage
VIN, VOUT
-0.3 ~ VDDQ + 0.3
V
Power Supply Voltage
VDD, VDDQ
-0.3 ~ 3.6
V
Operating Temperature (-4/-5/-6)
TOPR
0 ~ 70
°C
Operating Temperature (-5I/-6I)
TOPR
-40 ~ 85
°C
Storage Temperature
TSTG
-55 ~ 150
°C
TSOLDER
260
°C
PD
1
W
IOUT
50
mA
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
Note: Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
9.2
Recommended DC Operating Conditions
(TA = 0 to 70°C for -4/-5/-6, TA = -40 to 85°C for -5I/-6I)
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
VDD
Power Supply Voltage (for -5/-6)
2.3
2.5
2.7
V
2
VDD
Power Supply Voltage (for -4)
2.4
2.5
2.6
V
2
VDDQ
I/O Buffer Supply Voltage (for -5/-6)
2.3
2.5
2.7
V
2
VDDQ
I/O Buffer Supply Voltage (for -4)
2.4
2.5
2.6
V
2
VREF
Input reference Voltage
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2, 3
VTT
PARAMETER
Termination Voltage (System)
VREF - 0.04
VREF
VREF + 0.04
V
2, 8
VIH (DC)
Input High Voltage (DC)
VREF + 0.15
-
VDDQ + 0.3
V
2
VIL (DC)
Input Low Voltage (DC)
-0.3
-
VREF - 0.15
V
2
Differential Clock DC Input Voltage
-0.3
-
VDDQ + 0.3
V
15
0.36
-
VDDQ + 0.6
V
13, 15
Input High Voltage (AC)
VREF + 0.31
-
-
V
2
Input Low Voltage (AC)
-
-
VREF - 0.31
V
2
0.7
-
VDDQ + 0.6
V
13, 15
Differential AC input Cross Point Voltage
VDDQ/2 - 0.2
-
VDDQ/2 + 0.2
V
12, 15
Differential Clock AC Middle Point
VDDQ/2 - 0.2
-
VDDQ/2 + 0.2
V
14, 15
VICK (DC)
VID (DC)
VIH (AC)
VIL (AC)
VID (AC)
VX (AC)
VISO (AC)
Input Differential Voltage.
CLK and CLK inputs (DC)
Input Differential Voltage.
CLK and CLK inputs (AC)
Notes: Undershoot Limit: VIL (min) = -1.5V with a pulse width < 5 nS
Overshoot Limit: VIH (max) = VDDQ +1.5V with a pulse width < 5 nS
VIH (DC) and VIL (DC) are levels to maintain the current logic state.
VIH (AC) and VIL (AC) are levels to change to the new logic state.
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Revision A06
W9412G6IH
9.3
Capacitance
(VDD = VDDQ = 2.5V ±0.2V, f = 1 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V)
MIN.
MAX.
DELTA
(MAX.)
UNIT
Input Capacitance (except for CLK pins)
2.0
4.0
0.5
pF
CCLK
Input Capacitance (CLK pins)
3.0
5.0
0.25
pF
CI/O
DQ, DQS, DM Capacitance
1.5
5.5
0.5
pF
CNC
NC Pin Capacitance
-
1.5
-
pF
SYMBOL
CIN
PARAMETER
Notes: These parameters are periodically sampled and not 100% tested.
The NC pins have additional capacitance for adjustment of the adjacent pin capacitance.
9.4
Leakage and Output Buffer Characteristics
SYMBOL
II (L)
IO (L)
VOH
PARAMETER
UNIT
-2
2
µA
-5
5
µA
VTT +0.76
-
V
-
VTT -0.76
V
-15.2
-
mA
4, 6
15.2
-
mA
4, 6
60%
Strength
-10.4
-
mA
5
10.4
-
mA
5
-
mA
5
mA
5
(0V < VIN < VDDQ, All other pins not under test = 0V)
Output Leakage Current
(Output disabled, 0V < VOUT < VDDQ)
Output High Voltage
(under AC test load condition)
IOH (DC)
IOL (DC)
Output Minimum Sink DC Current
IOH (DC)
Output Minimum Source DC Current
IOL (DC)
Output Minimum Sink DC Current
IOH (DC)
Output Minimum Source DC Current
IOL (DC)
MAX.
Input Leakage Current
Output Low Voltage
(under AC test load condition)
Output Minimum Source DC Current
VOL
MIN.
Output Minimum Sink DC Current
100%
Strength
NOTES
30%
-7.2
Strength
7.2
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Revision A06
W9412G6IH
9.5
DC Characteristics
MAX.
SYM.
PARAMETER
IDD0
Operating current: One Bank Active-Precharge;
tRC = tRC min; tCK = tCK min;
DQ, DM and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles.
IDD1
-4
Operating current: One Bank Active-Read-Precharge;
Burst = 4; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA;
UNIT
NOTES
-5/-5I
-6/-6I
130
130
120
7
140
140
130
7, 9
20
20
20
45
45
45
20
20
20
Address and control inputs changing once per clock cycle.
IDD2P
Precharge Power Down standby current:
All Banks Idle; Power down mode;
CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM.
Idle standby current:
IDD2N
CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min;
Address and other control inputs changing once per clock cycle;
7
Vin > VIH min or Vin < VIL max for DQ, DQS and DM.
IDD3P
Active Power Down standby current:
One Bank Active; Power down mode;
CKE < VIL max; tCK = tCK min;
Vin = VREF for DQ, DQS and DM.
Active standby current:
mA
CS > VIH min; CKE > VIH min; One Bank Active-Precharge;
IDD3N
60
60
60
7
IDD4R
Operating current:
Burst = 2; Reads; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle;
CL=2; tCK = tCK min; IOUT = 0mA.
185
180
170
7, 9
IDD4W
Operating current:
Burst = 2; Write; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle;
CL = 2; tCK = tCK min;
DQ, DM and DQS inputs changing twice per clock cycle.
185
180
170
7
IDD5
Auto Refresh current: tRC = tRFC min.
200
200
190
7
IDD6
Self Refresh current: CKE < 0.2V; external clock on; tCK = tCK min.
3
3
3
IDD7
Random Read current: 4 Banks Active Read with activate every
20nS, Auto-Precharge Read every 20 nS;
Burst = 4; tRCD = 3; IOUT = 0mA;
DQ, DM and DQS inputs changing twice per clock cycle;
Address changing once per clock cycle.
320
320
300
tRC = tRAS max; tCK = tCK min;
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle.
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
9.6
AC Characteristics and Operating Condition
SYM.
-4
PARAMETER
MIN.
-5/-5I
MAX.
MIN.
-6/-6I
MAX.
MIN.
tRC
Active to Ref/Active Command Period
48
50
54
tRFC
Ref to Ref/Active Command Period
60
70
70
tRAS
Active to Precharge Command Period
40
tRCD
Active to Read/Write Command Delay Time
16
15
18
tRAP
Active to Read with Auto-precharge Enable
16
15
18
tCCD
Read/Write(a) to Read/Write(b) Command
Period
1
1
1
tRP
Precharge to Active Command Period
16
15
18
tRRD
Active(a) to Active(b) Command Period
12
10
12
tWR
Write Recovery Time
12
15
15
tDAL
Auto-precharge Write Recovery + Precharge
Time
-
-
-
70000
40
70000
42
MAX.
100000
tCK
-
7.5
12
7.5
12
CL = 2.5
-
-
6
12
6
12
CL = 3
4
12
5
12
6
12
CL = 4
4
12
-
-
-
-
Data Access Time from CLK, CLK
-0.65
0.65
-0.7
0.7
-0.7
0.7
tDQSCK
DQS Output Access Time from CLK, CLK
-0.55
0.55
-0.6
0.6
-0.6
0.6
tDQSQ
Data Strobe Edge to Output Data Edge Skew
tAC
0.4
0.4
0.45
0.55
0.45
0.55
0.45
0.55
tCL
CLK Low Level Width
0.45
0.55
0.45
0.55
0.45
0.55
tHP
CLK Half Period (minimum of actual tCH, tCL)
min
min,
min,
(tCL,tCH)
(tCL,tCH)
(tCL,tCH)
tHP
tHP
tHP
-0.5
-0.5
-0.5
DQS Read Preamble Time
0.9
1.1
0.9
1.1
0.9
1.1
tRPST
DQS Read Postamble Time
0.4
0.6
0.4
0.6
0.4
0.6
tDS
DQ and DM Setup Time
0.4
0.4
0.4
tDH
DQ and DM Hold Time
0.4
0.4
0.4
tDIPW
DQ and DM Input Pulse Width (for each input)
1.75
1.75
1.75
tDQSH
DQS Input High Pulse Width
0.35
0.35
0.35
tDQSL
DQS Input Low Pulse Width
0.35
0.35
0.35
tDSS
DQS Falling Edge to CLK Setup Time
0.2
0.2
0.2
tDSH
DQS Falling Edge Hold Time from CLK
0.2
0.2
0.2
0
0
0
Clock to DQS Write Preamble Set-up Time
- 26 -
tCK
11
nS
tRPRE
tWPRES
nS
0.4
CLk High Level Width
DQ Output Data Hold Time from DQS
18
16
tCH
tQH
nS
nS
-
CLK Cycle Time
NOTES
tCK
CL = 2
tCK
UNIT
tCK
11
nS
tCK
11
nS
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
AC Characteristics and Operating Condition, continued
SYM.
-4
PARAMETER
MIN.
-5/-5I
MAX.
MIN.
MAX.
-6/-6I
MIN.
MAX.
tWPRE
DQS Write Preamble Time
0.25
tWPST
DQS Write Postamble Time
0.4
0.6
0.4
0.6
0.4
0.6
tDQSS
Write Command to First DQS Latching
0.85
Transition
1.15
0.75
1.25
0.75
1.25
0.25
UNIT
NOTES
tCK
11
0.25
tIS
Input Setup Time (fast slew rate)
0.6
0.6
0.75
19, 21-23
tIH
Input Hold Time (fast slew rate)
0.6
0.6
0.75
19, 21-23
tIS
Input Setup Time (slow slew rate)
0.7
0.7
0.8
20-23
Input Hold Time (slow slew rate)
0.7
0.7
0.8
20-23
Control & Address Input Pulse Width (for each
input)
2.2
2.2
2.2
tIH
tIPW
tHZ
tLZ
Data-out
High-impedance
Time
from
Low-impedance
Time
from
CLK, CLK
Data-out
CLK, CLK
nS
-0.7
0.7
-0.7
0.7
-0.7
0.7
-0.7
0.7
-0.7
0.7
-0.7
0.7
0.5
1.5
0.5
1.5
0.5
1.5
tT(SS)
SSTL Input Transition
tWTR
Internal Write to Read Command Delay
tXSNR
Exit Self Refresh to non-Read Command
72
75
75
nS
tXSRD
Exit Self Refresh to Read Command
200
200
200
tCK
tREFi
Refresh Interval Time (4k/ 64mS)
tMRD
Mode Register Set Cycle Time
9.7
2
2
1
15.6
8
15.6
10
tCK
15.6
12
µS
17
nS
AC Test Conditions
PARAMETER
SYMBOL
VALUE
UNIT
Input High Voltage (AC)
VIH
VREF + 0.31
V
Input Low Voltage (AC)
VIL
VREF - 0.31
V
Input Reference Voltage
VREF
0.5 x VDDQ
V
Termination Voltage
VTT
0.5 x VDDQ
V
Differential Clock Input Reference Voltage
VR
Vx (AC)
V
VID (AC)
1.5
V
VOTR
0.5 x VDDQ
V
Input Difference Voltage. CLK and CLK Inputs (AC)
Output Timing Measurement Reference Voltage
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Revision A06
W9412G6IH
VDDQ
VIH min (AC)
VREF
V SWING (MAX)
VIL max (AC)
VSS
T
T
Output
SLEW = (VIH min (AC) - VILmax (AC)) / T
Notes:
(1)
Conditions outside the limits listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
(2)
All voltages are referenced to VDD, VDDQ. ( 2.5V±0.1V for DDR500)
(3)
Peak to peak AC noise on VREF may not exceed ±2% VREF(DC).
(4)
VOH = 1.95V, VOL = 0.35V
(5)
VOH = 1.9V, VOL = 0.4V
(6)
The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V.
The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V.
(7)
These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values
of tCK and tRC.
(8)
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set
equal to VREF and must track variations in the DC level of VREF.
(9)
These parameters depend on the output loading. Specified values are obtained with the output open.
(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed
slope.
(11) IF the result of nominal calculation with regard to Tck contains more than one decimal place, the result is rounded up to
the nearest decimal place.
(i.e., tDQSS = 0.75 × tCK, tCK = 7.5 nS, 0.75 × 7.5 nS = 5.625 nS is rounded up to 5.6 nS.)
(12) VX is the differential clock cross point voltage where input timing measurement is referenced.
(13) VID is magnitude of the difference between CLK input level and CLK input level.
(14) VISO means {VICK(CLK)+VICK( CLK )}/2.
(15) Refer to the figure below.
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
CLK
VX
VX
VX
VICK
VX
VICK
VX
VID(AC)
CLK
VICK
VICK
VSS
VID(AC)
0 V Differential
VISO
VISO(min)
VISO(max)
VSS
(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
(17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
(18) tDAL = (tWR/tCK) + (tRP/tCK)
(19) For command/address input slew rate ≥1.0 V/nS.
(20) For command/address input slew rate ≥0.5 V/nS and <1.0 V/nS.
(21) For CLK & CLK slew rate ≥1.0 V/nS (single--ended).
(22) These parameters guarantee device timing, but they are not necessarily tested on each device. They may be
guaranteed by device design or tester correlation.
(23) Slew Rate is measured between VOH(ac) and VOL(ac).
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
10. SYSTEM CHARACTERISTICS FOR DDR SDRAM
The following specification parameters are required in systems using DDR500, DDR400 & DDR333
devices to ensure proper system performance. These characteristics are for system simulation
purposes and are guaranteed by design.
10.1 Table 1: Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
PARAMETER
SYMBOL
DDR500
MIN. MAX.
DQ/DM/DQS input slew rate
measured between VIH(DC), DCSLEW
VIL(DC) and VIL(DC), VIH(DC)
0.5
4.0
DDR400
DDR333
MIN.
MAX.
MIN.
MAX.
0.5
4.0
0.5
4.0
UNIT NOTES
V/nS
a, m
10.2 Table 2: Input Setup & Hold Time Derating for Slew Rate
INPUT SLEW RATE
ΔtIS
ΔtIH
UNIT
NOTES
0.5 V/nS
0.4 V/nS
0.3 V/nS
0
+50
+100
0
0
0
pS
pS
pS
i
i
i
10.3 Table 3: Input/Output Setup & Hold Time Derating for Slew Rate
INPUT SLEW RATE
ΔtDS
ΔtDH
UNIT
NOTES
0.5 V/nS
0.4 V/nS
0.3 V/nS
0
+75
+150
0
0
0
pS
pS
pS
k
k
k
10.4 Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
INPUT SLEW RATE
ΔtDS
ΔtDH
UNIT
NOTES
±0.0 nS/V
0
0
pS
j
±0.25 nS/V
+50
0
pS
j
±0.5 nS/V
+100
0
pS
j
10.5 Table 5: Output Slew Rate Characteristics (X16 Devices only)
SLEW RATE
CHARACTERISTIC
TYPICAL
RANGE (V/NS)
MINIMUM
(V/NS)
MAXIMUM
(V/NS)
NOTES
Pullup Slew Rate
Pulldown Slew Rate
1.2 ~ 2.5
1.2 ~ 2.5
0.7
0.7
5.0
5.0
a, c, d, f, g, h
b, c, d, f, g, h
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Revision A06
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10.6 Table 6: Output Slew Rate Matching Ratio Characteristics
SLEW RATE CHARACTERISTIC
DDR500
DDR400
DDR333
PARAMETER
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Output Slew Rate Matching Ratio
(Pullup to Pulldown)
0.67
1.5
0.67
1.5
0.67
1.5
NOTES
e, m
10.7 Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins
SPECIFICATION
PARAMETER
DDR500
DDR400
DDR333
Maximum peak amplitude allowed for overshoot
1.5 V
1.5 V
1.5 V
Maximum peak amplitude allowed for undershoot
1.5 V
1.5 V
1.5 V
The area between the overshoot signal and VDD
must be less than or equal to Max. area in Figure 3
3.0 V-nS
3.0 V-nS
3.6 V-nS
The area between the undershoot signal and GND
must be less than or equal to Max. area in Figure 3
3.0 V-nS
3.0 V-nS
3.6 V-nS
VDD
Overshoot
5
Max. amplitude = 1.5V
4
3
2
Max. area
1
0
-1
-2
-3
Max. amplitude = 1.5V
GND
-4
-5
0 0.5 0.68751.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.06.3125 6.5 7.0
Time (nS)
Undershoot
Figure 3: Address and Control AC Overshoot and Undershoot Definition
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W9412G6IH
10.8 Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins
SPECIFICATION
PARAMETER
DDR500
DDR400
DDR333
Maximum peak amplitude allowed for overshoot
1.2 V
1.2 V
1.2 V
Maximum peak amplitude allowed for undershoot
1.2 V
1.2 V
1.2 V
The area between the overshoot signal and VDD
must be less than or equal to Max. area in Figure 4
1.44 V-nS
1.44 V-nS
2.25 V-nS
The area between the undershoot signal and GND
must be less than or equal to Max. area in Figure 4
1.44 V-nS
1.44 V-nS
2.25 V-nS
VDD
Overshoot
5
Max. amplitude = 1.2V
4
3
2
Max. area
1
0
-1
-2
Max. amplitude = 1.2V
-3
GND
-4
-5
0
0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0
Time (nS)
Undershoot
Figure 4: DQ/DM/DQS AC Overshoot and Undershoot Definition
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W9412G6IH
10.9 System Notes:
a. Pullup slew rate is characterized under the test conditions as shown in Figure 1.
Figure 1: Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
Figure 2: Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV ± 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs
switching and only one output switching.
Example: For typical slew rate, DQ0 is switching
For minimum slew rate, all DQ bits are switching worst case pattern
For maximum slew rate, only one DQ is switching from either high to low, or low to high
The remaining DQ bits remain the same as for previous state
d. Evaluation conditions
Typical:
25 oC (T Ambient), VDDQ = nominal, typical process
Minimum:
70 oC (T Ambient), VDDQ = minimum, slow-slow process
Maximum:
0 oC (T Ambient), VDDQ = maximum, fast-fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and
voltage, over the entire temperature and voltage range. For a given output, it represents the
maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
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g. TSOP II package devices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below
0.5 V/nS as shown in Table 2. The Input slew rate is based on the lesser of the slew rates
determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew
rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise,
fall rate and DC-DC delta rise, fall rate. Input slew rate is based on the lesser of the slew rates
determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)}-{1/(slew Rate2)}
For example: If Slew Rate 1 is 0.5 V/nS and Slew Rate 2 is 0.4 V/nS, then the delta rise, fall rate is
-0.5 nS/V. Using the table given, this would result in the need for an increase in tDS and tDH of 100
pS.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/nS. The
I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The input
slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC)
to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve
setup and hold times. Signal transitions through the DC region must be monotonic.
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11. TIMING WAVEFORMS
11.1 Command Input Timing
11.2 Timing of the CLK Signals
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Revision A06
W9412G6IH
11.3 Read Timing (Burst Length = 4)
tCH
tCL
tCK
CLK
CLK
tIS
CMD
tIH
READ
tIH
tIS
ADD
Col
tDQSCK
tDQSCK
tRPST
tDQSCK
CAS Latency = 2
tRPRE
Hi-Z
DQS
Hi-Z
Preamble
Hi-Z
Output
(Data)
tDQSQ
tQH
QA0
DA0
QA1
DA1
tQH
Postamble
tDQSQ
tDQSQ
QA2
DA2
QA3
DA3
tAC
Hi-Z
tHZ
tDQSCK
tLZ
tDQSCK
tDQSCK
tRPRE
CAS Latency = 3
tRPST
Hi-Z
Hi-Z
DQS
Preamble
Hi-Z
Output
(Data)
tDQSQ
tQH
QA0
DA0
QA1
DA1
tQH
Postamble
tDQSQ
tDQSQ
QA2
DA2
QA3
DA3
Hi-Z
tAC
tLZ
tHZ
Notes: The correspondence of LDQS, UDQS to DQ. (W9412G6IH)
LDQS
DQ0~7
UDQS
DQ8~15
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.4 Write Timing (Burst Length = 4)
tCK
tCL
tCH
CLK
CLK
tIH
tIS
CMD
WRIT
tIH
tIS
ADD
x4, x8 device
tDSH
tDSS
tDSH
tDSS
tDQSH
tDQSL
tDQSH
tWPST
Col
tWPRES
tWPRE
DQS
Preamble
tDS
tDS
tDH
Input
(Data)
DA
DA0
0
tDH
DA
DA2
2
DA1
tDSS
tDQSL
tDQSH
tWPRES
Postamble
tDH
tDSH
tDQSS
x16 device
tDS
DA
DA3
3
tDSH
tDSS
tDQSH
tWPST
tWPRE
LDQS
Preamble
tDS
tDS
tDS
tDH
tDH
DA
DA1
1
DA
DA0
0
DQ0~7
Postamble
DA
DA2
2
tDH
DA
DA3
3
tDQSS
tDSH
tDQSL
tDQSH
tWPRES
tDSH
tDSS
tDSS
tDQSH
tWPST
tWPRE
UDQS
Preamble
tDS
tDH
DA
DA0
0
DQ8~15
tDS Postamble
tDS
tDH
DA
DA1
1
DA
DA2
2
tDH
DA
DA3
3
tDQSS
Note: x16 has two DQSs (UDQS for upper byte and LDQS for lower byte). Even if one of the 2 bytes is not used, both UDQS
and LDQS must be toggled.
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.5 DM, DATA MASK (W9412G6IH)
- 38 -
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.6 Mode Register Set (MRS) Timing
CLK
CLK
tMRD
CMD
MRS
ADD
Register Set data
NEXT CMD
Burst Length
A0
Burst Length
A1
A2
Addressing Mode
A3
A4
A5
CAS Latency
A2
A1
A0
Sequential
Interleaved
0
0
0
Reserved
Reserved
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
1
1
0
1
1
1
A6
A7
"0"
A8
A9
A10
A11
Addressing Mode
A3
Reserved
DLL Reset
"0"
"0"
Reserved
"0"
BA0
"0"
BA1
"0"
Mode Register Set
or
Extended Mode
Register Set
0
Sequential
1
Interleaved
CAS Latency
A6
A5
A4
0
0
0
0
0
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
Reserved
1
1
0
2.5
1
1
1
Reserved
DLL Reset
A8
* "Reserved" should stay "0" during MRS cycle.
- 39 -
Reserved
0
No
1
Yes
BA1
BA0
MRS or EMRS
0
0
Regular MRS cycle
0
1
Extended MRS cycle
1
0
1
1
Reserved
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.7 Extend Mode Register Set (EMRS) Timing
CLK
CLK
tMRD
CMD
EMRS
ADD
Register Set data
A0
NEXT CMD
A1
Buffer Strength
A2
"0"
A3
"0"
A4
"0"
Reserved
A5
"0"
A6
"0"
A7
"0"
A8
"0"
Buffer Strength
Reserved
A9
"0"
A10
"0"
A11
"0"
BA0
"0"
BA1
"0"
DLL Switch
A0
DLL Switch
0
Enable
1
Disable
A6
A1
Buffer Strength
0
0
100% Strength
0
1
60% Strength
1
0
Reserved
1
1
30% Strength
BA1
BA0
MRS or EMRS
0
0
Regular MRS cycle
0
1
Extended MRS cycle
1
0
1
1
Mode Register Set
or
Extended Mode
Register Set
* "Reserved" should stay "0" during EMRS cycle.
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.8 Auto-precharge Timing (Read Cycle, CL = 2)
1) tRCD (READA) ≥ tRAS (min) – (BL/2) × tCK
tRAS
tRP
CLK
CLK
BL=2
CMD
ACT
READA
ACT
AP
DQS
DQ
Q0
Q1
BL=4
CMD
ACT
AP
READA
ACT
DQS
DQ
Q0
Q1
Q2
Q3
BL=8
CMD
ACT
AP
READA
ACT
DQS
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Notes: CL=2 shown; same command operation timing with CL = 2,5 and CL=3
In this case, the internal precharge operation begin after BL/2 cycle from READA command.
AP
Represents the start of internal precharging.
The Read with Auto-precharge command cannot be interrupted by any other command.
- 41 -
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.9 Auto-precharge Timing (Read cycle, CL = 2), continued
2) tRCD/RAP(min) ≤ tRCD (READA) < tRAS (min) – (BL/2) × tCK
tRAS
tRP
CLK
CLK
BL=2
CMD
ACT
READA
AP
ACT
AP
ACT
tRAP
tRCD
DQS
DQ
Q0
Q1
BL=4
CMD
ACT
READA
tRAP
tRCD
DQS
DQ
Q0
Q1
Q2
Q3
BL=8
CMD
ACT
AP
READA
ACT
tRAP
tRCD
DQS
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Notes: CL2 shown; same command operation timing with CL = 2.5, CL=3.
In this case, the internal precharge operation does not begin until after tRAS(min) has command.
AP
Represents the start of internal precharging.
The Read with Auto-precharge command cannot be interrupted by any other command.
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Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.10 Auto-precharge Timing (Write Cycle)
CLK
CLK
tDAL
BL=2
CMD
WRITA
AP
ACT
DQS
DQ
D0
D1
tDAL
BL=4
CMD
WRITA
AP
ACT
DQS
DQ
D0
D1
D2
D3
tDAL
BL=8
CMD
WRITA
AP
ACT
DQS
DQ
D0
D1
D2
D3
D4
D5
D6
D7
The Write with Auto-precharge command cannot be interrupted by any other command.
AP
Represents the start of internal precharging.
- 43 -
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8)
11.12 Burst Read Stop (BL = 8)
- 44 -
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.13 Read Interrupted by Write & BST (BL = 8)
Burst Read cycle must be terminated by BST Command to avoid I/O conflict.
11.14 Read Interrupted by Precharge (BL = 8)
CLK
CLK
CMD
READ
PRE
CAS Latency = 2
DQS
CAS Latency
DQ
Q0
Q1
Q2
Q3
Q4
Q5
CAS Latency = 3
DQS
CAS Latency
DQ
Q0
Q1
Q2
- 45 -
Q3
Q4
Q5
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.15 Write Interrupted by Write (BL = 2, 4, 8)
11.16 Write Interrupted by Read (CL = 2, BL = 8)
CLK
CLK
CMD
WRIT
READ
DQS
DM
tWTR
DQ
D0
D1
D2
D3
Data must be
masked by DM
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Data masked by READ command,
DQS input ignored.
- 46 -
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.17 Write Interrupted by Read (CL = 3, BL = 4)
CLK
CLK
CMD
WRIT
READ
DQS
DM
tWTR
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
Data must be masked by DM
11.18 Write Interrupted by Precharge (BL = 8)
CLK
CLK
CMD
WRIT
PRE
ACT
tWR
tRP
DQS
DM
DQ
D0
D1
D2
D3
D4
D5
Data must be
masked by DM
D6
D7
Data masked by PRE
command, DQS input ignored.
- 47 -
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.19 2 Bank Interleave Read Operation (CL = 2, BL = 2)
CLK
CLK
tRC(b)
tRC(a)
tRRD
CMD
tRRD
ACTa
ACTb
READAa
READAb
tRCD(a)
tRAS(a)
ACTa
ACTb
tRP(a)
tRCD(b)
tRAS(b)
tRP(b)
DQS
Preamble
Postamble
CL(a)
DQ
Q0a
ACTa/b
: Bank Act. CMD of bank a/b
READAa/b : Read with Auto Pre.CMD of bank a/b
APa/b
: Auto Pre. of bank a/b
Preamble
Postamble
CL(b)
APa
Q1a
Q0b
Q1b
APb
11.20 2 Bank Interleave Read Operation (CL = 2, BL = 4)
CLK
CLK
tRC(b)
tRC(a)
tRRD
tRRD
CMD
ACTa
ACTb
READAa
READAb
ACTa
ACTb
tRCD(a)
tRP(a)
tRAS(a)
tRCD(b)
tRP(b)
tRAS(b)
DQS
Preamble
Postamble
CL(b)
CL(a)
DQ
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
ACTa/b
: Bank Act. CMD of bank a/b
READAa/b : Read with Auto Pre.CMD of bank a/b
APa/b
: Auto Pre. of bank a/b
- 48 -
APa
APb
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.21 4 Bank Interleave Read Operation (CL = 2, BL = 2)
CLK
CLK
tRC(a)
tRRD
CMD
ACTa
tRRD
ACTb
tRRD
ACTc
READAa
tRRD
ACTd
READAb
ACTa
READAc
tRCD(a)
tRAS(a)
tRP
tRCD(b)
tRAS(b)
tRCD(c)
tRAS(c)
tRCD(d)
tRAS(d)
DQS
Preamble
CL(a)
Postamble
DQ
Q0a Q1a
ACTa/b/c/d
: Bank Act. CMD of bank a/b/c/d
READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d
APa/b/c/d
: Auto Pre. of bank a/b/c/d
Preamble
CL(b)
Q0b Q1b
APb
APa
11.22 4 Bank Interleave Read Operation (CL = 2, BL = 4)
- 49 -
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.23 Auto Refresh Cycle
Note: CKE has to be kept “High” level for Auto-Refresh cycle.
11.24 Precharged/Active Power Down Mode Entry and Exit Timing
Note:
1. If power down occurs when all banks are idle, this mode is referred to as precharge power down.
2. If power down occurs when there is a row active in any bank, this mode is referred to as active power down.
11.25 Input Clock Frequency Change during Precharge Power Down Mode Timing
CLK
CLK
CMD
NOP
NOP
NOP
NOP
NOP
CMD
tIS
Frequency Change
Occurs here
CKE
DLL
RESET
200 clocks
tRP
Minmum 2 clocks
required before
changing frequency
Stable new clock
before power down exit
- 50 -
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
11.26 Self Refresh Entry and Exit Timing
Note:
If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.
- 51 -
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
12. PACKAGE SPECIFICATION
12.1 66L TSOP – 400 mil
E1
E
D
O
O1
L
L1
O
O1
- 52 -
Publication Release Date: Sep. 16, 2009
Revision A06
W9412G6IH
13. REVISION HISTORY
VERSION
DATE
PAGE
A01
Apr. 11, 2008
All
A02
May 07, 2008
30, 31, 32,
33, 34
A03
Jun. 06, 2008
DESCRIPTION
Formally data sheet
27
27
Detailed descriptions of slew rate and
overshoot/undershoot is added in system AC
characteristics
Revise -5 speed grade AC parameter tWTR from 1 tCK
to 2 tCK
Revise -5 and -6 speed grades AC parameter tWPRE
from 0.3 tCK to 0.25 tCK
A04
Mar. 02, 2009
4, 5, 23,
25, 26, 27
Add -5I and -6I industrial grade parts
A05
Apr. 01, 2009
4, 23, 28
Modify DDR500 -4 speed grade power supply voltage
range from 2.6V ±0.1V to 2.5V ±0.1V
A06
Sep. 16, 2009
16, 24, 40
Add 30% driver strength support
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
- 53 -
Publication Release Date: Sep. 16, 2009
Revision A06