W988D6FB / W988D2FB

W988D6FB / W988D2FB
256Mb Mobile LPSDR
Table of Contents1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 4
FEATURES ................................................................................................................................. 4
ORDER INFORMATION ............................................................................................................. 4
BALL CONFIGURATION ............................................................................................................ 5
4.1
Ball Assignment: LPSDR x16 ......................................................................................... 5
4.2
Ball Assignment: LPSDR x32 ......................................................................................... 6
BALL DESCRIPTION .................................................................................................................. 7
5.1
Signal Description ........................................................................................................... 7
5.2
Addressing Table ............................................................................................................ 8
BLOCK DIAGRAM ...................................................................................................................... 9
FUNCTIONAL DESCRIPTION.................................................................................................. 10
7.1
Command Function ...................................................................................................... 10
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.12
7.1.13
7.1.14
7.1.15
7.1.16
7.1.17
7.1.18
7.1.19
7.1.20
7.1.21
8.
Table 1. Truth Table (Note (1) and (2)) ................................................................... 10
Functional Truth Table (See Note 1) ...................................................................... 11
Functional Truth Table for CKE .............................................................................. 14
Bank Activate Command ........................................................................................ 15
Bank Precharge Command .................................................................................... 15
Precharge All Command ........................................................................................ 15
Write Command...................................................................................................... 15
Write with Auto Precharge Command .................................................................... 15
Read Command ..................................................................................................... 15
Read with Auto Precharge Command .................................................................... 15
Extended Mode Register Set Command ................................................................ 16
Mode Register Set Command ................................................................................ 16
No-Operation Command ........................................................................................ 16
Burst Stop Command ............................................................................................. 16
Device Deselect Command .................................................................................... 16
Auto Refresh Command ......................................................................................... 16
Self Refresh Entry Command ................................................................................. 16
Self Refresh Exit Command ................................................................................... 17
Clock Suspend Mode Entry/Power Down Mode Entry Command .......................... 17
Clock Suspend Mode Exit/Power Down Mode Exit Command ............................... 17
Data Write/Output Enable, Data Mask/Output Disable Command.......................... 17
OPERATION ............................................................................................................................. 17
8.1
Read Operation............................................................................................................. 17
8.2
Write Operation ............................................................................................................. 18
8.3
Precharge ..................................................................................................................... 18
8.3.1
8.3.2
Auto Precharge....................................................................................................... 18
READ with auto precharge interrupted by a READ (with or without auto precharge)
19
Publication Release Date: Sep. 22, 2014
Revision: A01-006
-1-
W988D6FB / W988D2FB
8.3.3
READ with auto precharge interrupted by a WRITE (with or without auto precharge)
19
8.3.4
WRITE with auto precharge interrupted by a READ (with or without auto precharge)
20
8.3.5
WRITE with auto precharge interrupted by a WRITE (with or without auto
precharge) 20
8.4
8.5
Burst Termination.......................................................................................................... 21
Mode Register Operation.............................................................................................. 22
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
9.
8.6
Extended Mode Register Description ........................................................................... 25
8.7
Simplified State Diagram .............................................................................................. 26
ELECTRICAL CHARACTERISTICS ......................................................................................... 27
9.1
Absolute Maximum Ratings .......................................................................................... 27
9.2
Operating Conditions .................................................................................................... 27
9.3
Capacitance .................................................................................................................. 27
9.4
DC Characteristics ........................................................................................................ 28
9.5
Automatic Temperature Compensated Self Refresh Current Feature ......................... 28
9.6
AC Characteristics and Operating Condition ................................................................ 29
9.6.1
9.6.2
9.6.3
10.
11.
Burst Length field (A2~A0) ..................................................................................... 22
Addressing Mode Select (A3) ................................................................................. 22
Addressing Sequence for Sequential Mode ........................................................... 22
Addressing Sequence for Interleave Mode ............................................................. 23
Addressing Sequence Example (Burst Length = 8 and Input Address is 13) ......... 23
Read Cycle CAS Latency = 3 ................................................................................. 23
CAS Latency field (A6~A4) ..................................................................................... 24
Mode Register Definition ........................................................................................ 24
AC Characteristics .................................................................................................. 29
AC Test Condition .................................................................................................. 30
AC Latency Characteristics .................................................................................... 31
CONTROL TIMING WAVEFORMS .......................................................................................... 32
10.1 Command Input Timing ................................................................................................ 32
10.2 Read Timing.................................................................................................................. 33
10.3 Control Timing of Input Data (x16)................................................................................ 34
10.4 Control Timing of Output Data (x16) ............................................................................. 35
10.5 Control Timing of Input Data (x32)................................................................................ 36
10.6 Control Timing of Output Data (x32) ............................................................................. 37
10.7 Mode Register Set (MRS) Cycle................................................................................... 38
10.8 Extended Mode register Set (EMRS) Cycle ................................................................. 39
OPERATING TIMING EXAMPLE ............................................................................................. 40
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ...................................... 40
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ........... 41
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ...................................... 42
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ........... 43
11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 44
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 45
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 46
Publication Release Date: Sep. 22, 2014
Revision: A01-006
-2-
W988D6FB / W988D2FB
12.
13.
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ................................... 47
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ........................................ 48
11.10 Auto-precharge Write (Burst Length = 4) .................................................................... 49
11.11 Auto Refresh Cycle ..................................................................................................... 50
11.12 Self Refresh Cycle ....................................................................................................... 51
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)............................ 52
11.14 Power Down Mode ...................................................................................................... 53
11.15 Deep Power Down Mode Entry ................................................................................... 54
11.16 Deep Power Down Mode Exit ..................................................................................... 55
11.17 Auto-precharge Timing (Read Cycle) .......................................................................... 56
11.18 Auto-precharge Timing (Write Cycle) .......................................................................... 57
11.19 Timing Chart of Read to Write Cycle ........................................................................... 58
11.20 Timing Chart of Write to Read Cycle ........................................................................... 58
11.21 Timing Chart of Burst Stop Cycle (Burst Stop Command) .......................................... 59
11.22 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 59
11.23 CKE/DQM Input Timing (Write Cycle) ......................................................................... 60
11.24 CKE/DQM Input Timing (Read Cycle) ......................................................................... 61
PACKAGE SPECIFICATION .................................................................................................... 62
12.1 LPSDR x16 ................................................................................................................... 62
12.2 LPSDR x32 ................................................................................................................... 63
REVISION HISTORY ................................................................................................................ 64
Publication Release Date: Sep. 22, 2014
Revision: A01-006
-3-
W988D6FB / W988D2FB
1. GENERAL DESCRIPTION
The Winbond 256Mb Low Power SDRAM is a low power synchronous memory containing
268,435,456 memory cells fabricated with Winbond high performance process technology.
It is designed to consume less power than the ordinary SDRAM with low power features essential for
applications which use batteries. It is available in two organizations: 2,097,152 words × 4 banks × 32
bits or 4,194,304 words × 4 banks × 16 bits. The device operates in a fully synchronous mode, and the
output data are synchronized to positive edges of the system clock and is capable of delivering data at
clock rate up to 166MHz. The device supports special low power functions such as Partial Array Self
Refresh (PASR) and Automatic Temperature Compensated Self Refresh (ATCSR).
The Low Power SDRAM is suitable for 2.5G / 3G cellular phone, PDA, digital still camera, mobile
game consoles and other handheld applications where large memory density and low power
consumption are required. The device operates from 1.8V power supply, and supports the 1.8V
LVCMOS bus interface.
2. FEATURES














Power supply VDD = 1.7V~1.95V
VDDQ = 1.7V~1.95V
Frequency: 166MHz(-6),133MHz(-75)
Standard Self Refresh Mode
Programmable Partial Array Self Refresh
Power Down Mode
Deep Power Down Mode (DPD)
Programmable output buffer driver strength
Automatic Temperature Compensated Self
Refresh
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Refresh: refresh cycle 64mS
Interface: LVCMOS
Support package:
54 balls VFBGA (x16)
90 balls VFBGA (x32)
 Operating Temperature Range:
Extended (-25°C ~ +85°C)
Industrial (-40°C ~ +85°C)
3. ORDER INFORMATION
Part Number
VDD/VDDQ
I/O Width
Package
Others
W988D6FBGX6I
1.8V/1.8V
16
54 balls VFBGA 166MHz, -40°C~85°C, Low Power
W988D6FBGX6E
1.8V/1.8V
16
54 balls VFBGA 166MHz, -25°C~85°C, Low Power
W988D6FBGX7E
1.8V/1.8V
16
54 balls VFBGA 133MHz, -25°C~85°C, Low Power
W988D6FBGX7G
1.8V/1.8V
16
54 balls VFBGA 133MHz, -25°C~85°C
W988D6FBGX7I
1.8V/1.8V
16
54 balls VFBGA 133MHz, -40°C~85°C, Low Power
W988D2FBJX6I
1.8V/1.8V
32
90 balls VFBGA 166MHz, -40°C~85°C, Low Power
W988D2FBJX6E
1.8V/1.8V
32
90 balls VFBGA 166MHz, -25°C~85°C, Low Power
W988D2FBJX7E
1.8V/1.8V
32
90 balls VFBGA 133MHz, -25°C~85°C, Low Power
W988D2FBJX7G
1.8V/1.8V
32
90 balls VFBGA 133MHz, -25°C~85°C
Publication Release Date: Sep. 22, 2014
Revision: A01-006
-4-
W988D6FB / W988D2FB
4. BALL CONFIGURATION
4.1 Ball Assignment: LPSDR x16
Top View
1
2
3
VSS
DQ15
DQ14
4
5
6
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
DQ8
NC
VSS
VDD
LDQM
DQ7
UDQM
CLK
CKE
/CAS
/RAS
/WE
A12
A11
A9
BA0
BA1
/CS
A8
A7
A6
A0
A1
A10
VSS
A5
A4
A3
A2
VDD
A
B
C
D
E
F
G
H
J
Publication Release Date: Sep. 22, 2014
Revision: A01-006
-5-
W988D6FB / W988D2FB
4.2
Ball Assignment: LPSDR x32
Top View
1
2
3
4
5
6
7
8
9
A
DQ26 DQ24
VDD
VSS
DQ23 DQ21
B
DQ28 VDDQ VSSQ
VDDQ VSSQ DQ19
VSSQ DQ27 DQ25
DQ22 DQ20 VDDQ
VSSQ DQ29 DQ30
DQ17 DQ18 VDDQ
C
D
E
VDDQ DQ31
NC
NC
DQ16 VSSQ
F
VSS
DQM3
A3
A2
DQM2
VDD
A4
A5
A6
A10
A0
A1
A7
A8
NC
NC
BA1
A11
CLK
CKE
A9
BA0
/CS
/RAS
DQM1
NC
NC
/CAS
/WE
DQM0
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
DQ1
DQ3
VDDQ
G
H
J
K
L
M
N
VSSQ DQ12 DQ14
P
VDDQ VSSQ
DQ11 VDDQ VSSQ
DQ4
R
DQ13 DQ15
VSS
VDD
DQ0
DQ2
Publication Release Date: Sep. 22, 2014
Revision: A01-006
-6-
W988D6FB / W988D2FB
5. BALL DESCRIPTION
5.1 Signal Description
Ball Name
Function
A [n:0]
Address
BA0, BA1
Bank Select
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
Description
Multiplexed pins for row and column address.
A10 is Auto Precharge Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
Data Input/ Output Multiplexed pins for data output and input.
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is ignored
and previous operation continues.
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of the
clock, RAS , CAS and WE define the operation to be
executed.
CAS
Column Address
Strobe
Referred to RAS
WE
Write Enable
Referred to WE
The output buffer is placed at Hi-Z (with latency of 2 in
CL=2, 3;) when DQM is sampled high in read cycle. In
write cycle, sampling DQM high will block the write
operation with zero latency
UDQM / LDQM(x16)
DQM0~DQM3 (x32)
I/O Mask
CLK
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
CKE
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode or Self
Refresh mode is entered.
VDD
Power
Power supply for input buffers and logic circuit inside
DRAM.
VSS
Ground
Ground for input buffers and logic circuit inside DRAM.
VDDQ
Power for I/O Buffer
VSSQ
Ground for I/O
Buffer
Separated ground from VSS, used for output buffers to
improve noise.
NC
No Connection
No connection
Power supply separated from VDD, used for output
buffers to improve noise.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
-7-
W988D6FB / W988D2FB
5.2
Addressing Table
x16
x32
Item
256 Mb
Number of banks
4
Bank address pins
BA0,BA1
Auto precharge pin
A10/AP
Type
Package
Row addresses
A0-A12
Column addresses
A0-A8
Row addresses
A0-A11
Column addresses
A0-A8
Publication Release Date: Sep. 22, 2014
Revision: A01-006
-8-
W988D6FB / W988D2FB
6. BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
RAS
GENERATOR
COMMAND
CAS
DECODER
ROW DECODER
A10
COLUMN
DECODER
ROW DECODER
COLUMN
DECODER
WE
CELL ARRAY
BANK #0
MODE
REGISTER
A0
SENSE AMPLIFIER
SENSE AMPLIFIER
ADDRESS
BUFFER
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ0
DQn
COLUMN
COUNTER
DQM
COLUMN
DECODER
COLUMN
DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
ROW DECODER
REFRESH
COUNTER
ROW DECODER
An
BA0
BA1
CELL ARRAY
BANK #1
CELL ARRAY
BANK #3
SENSE AMPLIFIER
Publication Release Date: Sep. 22, 2014
Revision: A01-006
-9-
W988D6FB / W988D2FB
7. FUNCTIONAL DESCRIPTION
7.1 Command Function
7.1.1
Table 1. Truth Table (Note (1) and (2))
Device State CKEn-1 CKEn DQM(5) BA0, 1 A10 A0-An
Symbol
Command
ACT
Bank Activate
Idle(3)
H
X
X
V
CS
RAS
CAS
WE
V
V
L
L
H
H
PRE
Bank Precharge
Any
H
X
X
V
L
X
L
L
H
L
PREA
Precharge All
Any
H
X
X
X
H
X
L
L
H
L
WRIT
Write
Active(3)
H
X
X
V
L
V
L
H
L
L
WRITA
Write with Auto
Precharge
Active(3)
H
X
X
V
H
V
L
H
L
L
(3)
H
X
X
V
L
V
L
H
L
H
READ
Read
READA
Read with Auto
Precharge
Active
Active(3)
H
X
X
V
H
V
L
H
L
H
MRS
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
EMRS
Extended Mode
Register Set
Idle
H
X
X
V
V
V
L
L
L
L
NOP
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
BST
Burst stop
H
X
X
X
X
X
L
H
H
L
DSL
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AREF
Auto-Refresh
Idle
H
H
X
X
X
X
L
L
L
H
SELF
Self-Refresh Entry
Idle
H
L
X
X
X
X
H
Self-Refresh Exit
Idle
(Self Refresh)
L
SELEX
Active
(4)
H
X
X
X
L
L
L
H
X
X
X
L
H
H
H
X
X
X
X
X
CSE
Clock Suspend
Mode Entry
Active
H
L
X
X
X
X
PD
Power Down Mode
Entry
Idle/Active(6)
H
L
X
X
X
X
CSEX
Clock Suspend
Mode Exit
Active
L
H
X
X
X
X
PDEX
Power Down Mode
Exit
Any
(Power Down)
L
H
X
X
X
X
DE
Data Write/Output
Enable
Active
H
X
L
X
X
DD
Data Write/Output
Disable
Active
H
X
H
X
DPD
Deep Power Down
Mode Entry
Idle
H
L
X
DPDE
Deep Power Down
Mode Exit
Idle (DPD)
L
H
X
H
X
X
X
L
H
H
H
X
X
X
X
H
X
X
X
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
H
L
X
X
X
X
X
X
X
Notes:
(1) v = valid, x = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BA0, BA1 signals.
(4) Device state is full page burst operation.
(5) x32: DQM0-3, x16 : LDQM / UDQM
(6) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 10 -
W988D6FB / W988D2FB
7.1.2
Functional Truth Table (See Note 1)
Current
State
Idle
Row active
Read
Write
CS
RAS
CAS
WE
Address
Command
Action
Notes
H
X
X
X
X
DSL
Nop
L
H
H
X
X
NOP/BST
Nop
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE/PREA
Nop
L
L
L
H
X
AREF/SELF
Refresh or Self refresh
2
L
L
L
L
Op-Code
MRS/EMRS
Mode register accessing
2
Row activating
H
X
X
X
X
DSL
Nop
L
H
H
X
X
NOP/BST
Nop
L
H
L
H
BA, CA, A10
READ/READA
Begin read: Determine AP
4
L
H
L
L
BA, CA, A10
WRIT/WRITA
Begin write: Determine AP
4
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
Precharge
5
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
Burst stop
L
H
L
H
BA, CA, A10
READ/READA
Term burst, new read: Determine
AP
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst, begin write:
Determine AP
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE/PREA
Term burst, precharging
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Continue burst to end.
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
Burst stop, row active
L
H
L
H
BA, CA, A10
READ/READA
Term burst, start read: Determine
AP
6, 7
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst, new write: Determine
AP
6
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
Term burst. precharging
8
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
ILLEGAL
6
6, 7
3
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 11 -
W988D6FB / W988D2FB
Current
State
Read with
auto
precharge
Write with
auto
precharge
Precharging
Row
activating
CS
RAS
CAS
WE
Address
Command
Action
Notes
H
X
X
X
X
DSL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Nop → Idle after tRP
L
H
H
H
X
NOP
Nop → Idle after tRP
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
Nop → Idle after tRP
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Nop → Row active after tRCD
L
H
H
H
X
NOP
Nop → Row active after tRCD
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 12 -
W988D6FB / W988D2FB
Current
State
Write
recovering
Write
recovering
with auto
precharge
Refreshing
Mode
register
accessing
CS
RAS
CAS
WE
Address
Command
Action
Notes
H
X
X
X
X
DSL
Nop → Maintain Row active after tWR
L
H
H
H
X
NOP
Nop → Maintain Row active after tWR
L
H
H
L
X
BST
Nop → Maintain Row active after tWR
L
H
L
H
BA, CA, A10
READ/READA
Begin Read
L
H
L
L
BA, CA, A10
WRIT/WRITA
Begin new Write
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
7
H
X
X
X
X
DSL
Nop → Enter precharge after tWR
L
H
H
H
X
NOP
Nop → Enter precharge after tWR
L
H
H
L
X
BST
Nop → Enter precharge after tWR
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Nop → Idle after tRFC
L
H
H
H
X
NOP
Nop → Idle after tRFC
L
H
H
L
X
BST
Nop → Idle after tRFC
L
H
L
X
X
READ/WRIT
ILLEGAL
L
L
H
X
X
ACT/PRE/PREA
ILLEGAL
L
L
L
X
X
AREF/SELF/
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Nop → Idle after tMRD
L
H
H
H
X
NOP
Nop → Idle after tMRD
L
H
H
L
X
BST
ILLEGAL
L
H
L
X
X
READ/WRIT
ILLEGAL
L
L
X
X
X
ACT/PRE/PREA/
AREF/SELF/
MRS/ EMRS
ILLEGAL
Notes:
1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. (CKEn-1 =
CKEn = ”1”)
2. Illegal if any bank is not idle.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
4. Illegal if tRCD is not satisfied.
5. Illegal if tRAS is not satisfied.
6. Must satisfy burst interrupt condition.
7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.
8. Must mask preceding data which don’t satisfy tWR.
Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 13 -
W988D6FB / W988D2FB
7.1.3
Functional Truth Table for CKE
Current
State
Self refresh
Power-Down
Deep PowerDown
All banks idle
Row Active
Any state
other than
listed above
CKE
CS
RAS
CAS
WE
Address
X
X
X
X
X
X
N/A
L
H
H
X
X
X
X
Exit Self Refresh → Idle after tRFC
L
H
L
H
H
H
X
Exit Self Refresh → Idle after tRFC
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
Maintain Self Refresh
H
X
N/A
n-1
n
H
L
H
X
X
X
X
X
H
X
X
X
X
L
H
H
H
X
Action
Notes
Exit Power Down → Idle after 1 clock cycle
L
L
X
X
X
X
X
Maintain Power-Down
H
X
X
X
X
X
X
N/A
L
H
X
X
X
X
X
Exit Deep Power-Down → Exit Sequence
L
L
X
X
X
X
X
Maintain Deep Power-Down
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
H
X
X
X
X
Enter Power-down
2
H
L
L
H
H
H
X
Enter Power-Down
2
H
L
L
H
H
L
X
Enter Deep Power-Down
3
H
L
L
L
L
H
X
Self Refresh
1
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Power-Down
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
H
X
X
X
X
Enter Power down
2
H
L
L
H
H
H
X
Enter Power down
2
H
L
L
L
L
H
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Power-Down → Row Active or Maintain PD
H
H
X
X
X
X
X
Refer to Function Truth Table
2
Notes:
1. Self refresh can enter only from the all banks idle state.
2. Power-down can enter only from the all banks idle or row active state.
3. Deep power-down can enter only from the all banks idle state.
Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 14 -
W988D6FB / W988D2FB
7.1.4
Bank Activate Command
( RAS = L, CAS = H, WE = H, BA0, BA1 = Bank, A0~An = Row Address)
The Bank Activate command activates the bank designated by the BA (Bank Select) signal.
Row addresses are latched on A0~An when this command is issued and the cell data is read out to the sense
amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max).
7.1.5
Bank Precharge Command
( RAS = L, CAS = H, WE = L, BA0, BA1 = Bank, A10 = L)
The Bank Precharge command is used to close (or precharge) the bank that is activated. Using this command,
systems can designated the bank to be closed by specifying the BA address bit setting in the command set. A
Precharge command can be used to precharge each bank separately (Bank Precharge) or all four banks
simultaneously (Precharge All). After the Bank Precharge command is issued, any one bank can close, and the
closed bank transitions from the active state to the idle state. To re-activate the closed bank, a system has to wait
the minimum tRP delay after issuing the Precharge command before issuing the Active Command for the device
to complete the Precharge operation.
7.1.6
Precharge All Command
( RAS = L, CAS = H, WE = L, BA0, BA1 = Don’t care, A10 = H)
The Precharge All command is used to precharge all banks simultaneously. After this command is issued, all four
banks close and transition from the active state to the idle state.
7.1.7
Write Command
( RAS = H, CAS = L, WE = L, BA0, BA1 = Bank, A10 = L)
The Write command initiates a Write operation to the bank selected by BA0 and BA1 address inputs. The write
data is latched at the positive edge of CLK. Users should preprogram the length of the write data (Burst Length)
and the column access sequence (Addressing Mode) by setting the Mode Resister at power-up prior to using the
Write command.
7.1.8
Write with Auto Precharge Command
( RAS = H, CAS = L, WE = L, BA0, BA1 = Bank, A10 = H)
The Write with Auto Precharge command performs the Precharge operation automatically after the Write
operation. The internal precharge starts in the cycles immediately following the cycle in which the last data is
written independent of CAS Latency.
7.1.9
Read Command
( RAS = H, CAS = L, WE = H, BA0, BA1 = Bank, A10 = L)
The Read command performs a Read operation to the bank designated by BA0-1. The read data is issued
sequentially synchronized to the positive edges of CLK. The length of read data (Burst Length), Addressing Mode
and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode
Register at power-up prior to the Write operation.
7.1.10 Read with Auto Precharge Command
( RAS = H, CAS = L, WE = H, BA0, BA1 = Bank, A10 = H)
The Read with Auto Precharge command automatically performs the Precharge operation after the Read
operation. When the CAS Latency = 3, the internal precharge starts two cycles before the last data is output.
When the CAS Latency = 2, the internal precharge starts one cycle before the last data is output.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 15 -
W988D6FB / W988D2FB
7.1.11 Extended Mode Register Set Command
( RAS = L, CAS = L, WE = L, BA1, A0~An = Register Data)
The Extended Mode Register Set command is designed to support Partial Array Self Refresh, Temperature
Compensated Self Refresh, and Output Driver Strength/Size by allowing users to program each value by setting
predefined address bits. The default values in the Extended Mode Register after power-up are undefined;
therefore this command must be issued during the power-up sequence. Also, this command can be issued while
all banks are in the idle state.
7.1.12 Mode Register Set Command
( RAS = L, CAS = L, WE = L, BA1, A0~An = Register Data)
The Mode Register Set command is used to program the values of CAS latency, Addressing Mode and Burst
Length in the Mode Register. The default values in the Mode Register after power-up are undefined; therefore this
command must be issued during the power-up sequence and re-issued after the Deep Power Down Exit
Command. Also, this command can be issued while all banks are in the idle state.
7.1.13 No-Operation Command
( RAS = H, CAS = H, WE = H)
The No-Operation command is used in cases such as preventing the device from registering unintended
commands. The device performs no operation when this command is registered. This command is functionally
equivalent to the Device Deselect command.
7.1.14 Burst Stop Command
( RAS = H, CAS = H, WE = L)
The Burst stop command is used to stop the already activated burst operation. The activated page is left unclosed
and future commands can be issued to access the same page of the active bank. If this command is issued
during a burst read operation, the read data will go to a Hi-Z state after a delay equal to the CAS latency. If a
burst stop command is issued during a burst write operation, then the burst data is terminated and data bus goes
to Hi-Z at the same clock that the burst command is activated. Any remaining data from the burst write cycle is
ignored.
7.1.15 Device Deselect Command
( CS = H)
The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address
inputs are ignored. This command is similar to the No-Operation command.
7.1.16 Auto Refresh Command
( RAS = L, CAS = L, WE = H, CKE = H, BA0, BA1, A0~An = Don’t care)
The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The
Refresh operation must be performed 8192 / 4096 (W988D6FB / W988D2FB) times within 64 mS. The next
command can be issued after tRC from the end of the Auto Refresh command. When the Auto Refresh command
is issued, All banks must be in the idle state. The Auto Refresh operation is equivalent to the CAS -before- RAS
operation in a conventional DRAM.
7.1.17 Self Refresh Entry Command
( RAS = L, CAS = L, WE = H, CKE = L, BA0, BA1, A0~An = Don’t care)
When the Self Refresh Entry command is issued, the device enters the Self Refresh mode. While the device is in
Self Refresh mode, the device automatically refreshes memory cells, and all input and I/O buffers (except the
CKE buffer) are disabled. By asserting the CKE signal “high” (and by issuing the Self Refresh Exit command), the
device exits the Self Refresh mode.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 16 -
W988D6FB / W988D2FB
7.1.18 Self Refresh Exit Command
(CKE = H, CS = H or CKE = H, RAS = H, CAS = H)
This command is issued to exit out of the Self Refresh mode. One tRC delay is required prior to issuing any
subsequent command from the end of the Self Refresh Exit command.
7.1.19 Clock Suspend Mode Entry/Power Down Mode Entry Command
(CKE = L)
The internal CLK is suspended for one cycle when this command is issued (when CKE is asserted “low”). The
device state is held intact while the CLK is suspended. On the other hand, when the device is not operating the
Burst cycle, this command performs entry into Power Down mode. All input and output buffers (except the CKE
buffer) are turned off in Power Down mode.
7.1.20 Clock Suspend Mode Exit/Power Down Mode Exit Command
(CKE = H)
When the internal CLK has been suspended, operation of the internal CLK is resumed by providing this command
(asserting CKE “high”). When the device is in Power Down mode, the device exits this mode and all disabled
buffers are turned on to the active state. Any subsequent commands can be issued after one clock cycle from the
end of this command.
7.1.21 Data Write/Output Enable, Data Mask/Output Disable Command
(DQM = L/H or LDQM, UDQM = L/H or DQM0-3=L/H)
During a Write cycle, the DQM or LDQM, UDQM or DQM0-3 signals mask write data. Each of these signals
control the input buffers per byte. During a Read cycle, the DQM or LDQM, UDQM or DQM0-3 signals control of
the output buffers per byte.
I/O Org.
×16
×32
Mask Pin
Masked DQs
LDQM
DQ0~DQ7
UDQM
DQ8~DQ15
DQM0
DQ0~DQ7
DQM1
DQ8~DQ15
DQM2
DQ16~DQ23
DQM3
DQ24~DQ31
8. OPERATION
8.1
Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is
issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized to the positive
edges of CLK (a Burst Read operation). The initial read data becomes available after CAS Latency from the
issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. In addition, the
burst length of read data and Addressing Mode must be set. Each bank is held in the active state unless the
Precharge command is issued, so that the sense amplifiers can be used as secondary cache.
When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically
after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other
commands. Also, when the Burst Length is 1 and tRCD (min), the timing from the RAS command to the start of
the Auto Precharge operation is shorter than tRAS (min). In this case, tRAS (min) must be satisfied by extending
tRCD.
When the Precharge operation is performed on a bank during a Burst Read operation, the Burst operation is
terminated.
When the Burst Length is full-page, column data is repeatedly read out until the Burst Stop command or
Precharge command is issued.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 17 -
W988D6FB / W988D2FB
8.2
Write Operation
Issuing the Write command after tRCD from the Bank Activate command, the input data is latched sequentially,
synchronizing with the positive edges of CLK after the Write command (Burst Write operation). The burst length of
the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up.
When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically
after the Write cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other
command for the entire burst data duration. Also, when the Burst Length is 1 and tRCD (min), the timing from the
RAS command to the start of the Auto Precharge operation is shorter than tRAS (min). In this case, tRAS (min)
must be satisfied by extending tRCD.
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is
terminated.
When the Burst Length is full-page, the input data is repeatedly latched until the Burst Stop command or the
Precharge command is issued.
When the Burst Read and Single Write mode is selected, the write burst length is 1 regardless of the read burst
length.
8.3
Precharge
There are two commands which perform the Precharge operation: Bank Precharge and Precharge All. When the
Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle
state. The Bank Precharge command can precharge one bank independently of the other bank and hold the
unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified
as tRAS (max). Therefore, each bank must be precharged within tRAS (max) from the Bank Activate command.
The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the
active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed
only for the active bank and the precharged bank is then switched to the idle state.
8.3.1
Auto Precharge
Auto precharge is a feature that performs the same individual-bank PRECHARGE function described previously,
without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in
conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in
the continuous page burst mode where auto precharge does not apply. In the specific case of write burst mode
set to single location access with burst length set to continuous, the burst length setting is the overriding setting
and auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for
each individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. Another command
cannot be issued to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time.
Winbond SDRAM supports concurrent auto precharge; cases of concurrent auto precharge for READs and
WRITEs are defined below.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 18 -
W988D6FB / W988D2FB
8.3.2
READ with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a READ on bank n following the programmed CAS latency. The precharge to
bank n begins when the READ to bank m is registered.
T1
T0
T2
T3
T4
T5
T6
T7
CLK
Command
NOP
Bank n
READ-AP
Bank n
Page active
READ-AP
Bank m
NOP
READ with burst of 4
NOP
NOP
NOP
NOP
Interrupt burst, precharge
Internal
states
Idle
tRP-bank n
Page active
Bank m
Precharge
READ with burst of 4
Bank n,
Col a
Address
tRP-bank m
Bank m,
Col d
Dout
a
DQ
Dout
a+1
Dout
d
Dout
d+1
CL=3 (bank n)
CL=3 (bank m)
Don’t Care
Note: DQM is LOW.
8.3.3
READ with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the
WRITE command to prevent bus contention. The precharge to bank n begins when the WRITE to bank m is
registered.
T1
T0
T2
T3
T4
T5
T6
T7
CLK
Command
Bank n
READ-AP
Bank n
Page
active
NOP
NOP
NOP
READ with burst of 4
WRITE-AP
Bank m
NOP
NOP
Interrupt burst, precharge
Internal
states
Idle
tWR-bank m
tRP-bank n
Page active
Bank m
Address
NOP
WRITE with burst of 4
Bank n,
Col a
Write-back
Bank m,
Col d
DQM
DOUT
a
DQ
Din
d
Din
d+1
Din
d+2
CL=3 (bank n)
Din
d+3
Don’t Care
Note: DQM is HIGH at T2 to prevent DOUTa + 1 from contending with DINd at T4.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 19 -
W988D6FB / W988D2FB
8.3.4
WRITE with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The
last valid WRITE to bank n will be data in registered one clock prior to the READ to bank m.
T1
T0
T2
T3
T4
T5
T6
T7
CLK
Command
Bank n
NOP
WRITE-AP
Bank n
Page active
READ-AP
Bank m
NOP
NOP
NOP
Interrupt burst, write-back
WRITE with burst of 4
Internal
states
NOP
NOP
precharge
tRP-bank n
tWR-bank n
tRP-bank m
Bank m
READ with burst of 4
Page active
Bank n,
Col a
Address
Dout
d+1
Dout
d
Din
a+1
Din
a
DQ
Bank m,
Col d
CL=3 (bank m)
Don’t Care
Note: DQM is LOW.
8.3.5
WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)
A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The
last valid WRITE to bank n will be data in registered one clock prior to the READ to bank m.
T1
T0
T2
T3
T4
T5
T6
T7
CLK
Command
Bank n
NOP
WRITE-AP
Bank n
NOP
NOP
NOP
Interrupt burst, write-back
WRITE with burst of 4
Page active
WRITE-AP
Bank m
Internal
states
tWR-bank n
NOP
NOP
precharge
tRP-bank n
tWR-bank m
Bank m
Address
DQ
Bank m,
Col d
Bank n,
Col a
Din
a
Write-back
WRITE with burst of 4
Page active
Din
a+1
Din
a+2
Din
d
Din
d+1
Din
d+2
Din
d+3
Don’t Care
Note: DQM is LOW.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 20 -
W988D6FB / W988D2FB
8.4
Burst Termination
The Read or Write command can be issued on any clock cycle. Whenever a Read operation is to be interrupted
by a Write command, the output data must be masked by DQM to avoid I/O conflict. Also, when a Write operation
is to be interrupted by a Read command, only the input data before the Read command is enable and the input
data after the Read command is disabled.
- Read Interrupted by a Precharge
A Precharge command can be issued to terminate a Burst cycle early. When a Burst Read cycle is
interrupted by a Precharge command, the read operation is terminated after (CAS latency-1) clock cycles
from the Precharge command.
- Write Interrupted by a Precharge
A burst Write cycle can be interrupted by a Precharge command, the input circuit is reset at the same clock
cycle at which the Precharge command is issued. In this case, the DQM signal must be asserted high to
prevent writing the invalid data to the cell array.
- Read Interrupted by a Burst Stop
When the Burst Stop command is issued for the bank in a Burst cycle, the Burst operation is terminated.
When the Burst Stop command is issued during a Burst Read cycle, the read operation is terminated after
clock cycle of (CAS latency-1) from the Burst Stop command.
- Write Interrupted by a Burst Stop
When the Burst Stop command is issued during a Burst Write cycle, the write operation is terminated at the
same clock cycle that the Burst Stop command is issued.
- Write Interrupted by a Read
A burst of write operation can be interrupted by a read command. The read command interrupts the write
operation on the same clock that the read command is issued. All the burst writes that are presented on the
data bus before the read command is issued will be written to the memory. Any remaining burst writes will
be ignored once the read command is activated. There must be at least one clock bubble (Hi-Z state) on the
data bus to avoid bus contention.
- Read Interrupted by a Write
A burst of read operation can be interrupted by a write command by driving output drivers in a Hi-Z state using
DQM before write to avoid data conflict. DQM should be utilized if there is data from a Read command on the first
and second cycles of the subsequent write cycles to ensure the read data are tri-stated. From the third clock
cycle, the write command will control the data bus and DQM is not needed.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 21 -
W988D6FB / W988D2FB
8.5
Mode Register Operation
The Mode register designates the operation mode for the Read or Write cycle. This register is divided into three
fields; A Burst Length field to set the length of burst data, an Addressing Mode selected bits to designate the
column access sequence in a Burst cycle, and a CAS Latency field to set the access time in clock cycle.
The Mode Register is programmed by the Mode Register Set command when all banks are in the idle state. The
data to be set in the Mode Register is transferred using the A0~An, BA0, BA1 address inputs. The initial value of
the Mode Register after power-up is undefined; therefore the Mode Register Set command must be issued before
proper operation.
8.5.1
Burst Length field (A2~A0)
This field specifies the data length for column access using the A2~A0 pins and sets the Burst Length to be 1, 2,
4, 8, words, or full-page.
8.5.2
A2
A1
A0
Bust Length
0
0
0
1 word
0
0
1
2 words
0
1
0
4 words
0
1
1
8 words
1
1
1
Full-Page
Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential mode. When the A3 bit is 0,
Sequential mode is selected. When the A3 bit is 1, Interleave mode is selected. Both Addressing modes support
burst length of 1, 2, 4 and 8 words. Additionally, Sequential mode supports the full-page burst.
8.5.3
A3
Addressing Mode
0
Sequential
1
Interleave
Addressing Sequence for Sequential Mode
A column access is performed by incrementing the column address input to the device. The address is varied by
the Burst Length shown as below table.
DATA
Access Address
Burst Length
Data 0
n
2 words (Address bit is A0)
Data 1
n+1
not carried from A0 to A1
Data 2
n+2
4 words (Address bit is A1, A0)
Data 3
n+3
not carried from A1 to A2
Data 4
n+4
Data 5
n+5
8 words (Address bit is A2, A1, A0)
Data 6
n+6
not carried from A2 to A3
Data 7
n+7
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 22 -
W988D6FB / W988D2FB
8.5.4
Addressing Sequence for Interleave Mode
A column access is started from the input column address and is performed by inverting the address bits in the
sequence shown as below table.
DATA
8.5.5
Access Address
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
Burst Length
2 words
4 words
8 words
Addressing Sequence Example (Burst Length = 8 and Input Address is 13)
Interleave Mode
Data
A8
A7
A6
Data0
0
0
Data1
0
Data2
Sequential Mode
A5
A4
A3
A2
A1
0
0
0
1
1
0
1
13
13
13
0
0
0
0
1
1
0
0
12
13 + 1
14
0
0
0
0
0
1
1
1
1
15
13 + 2
15
Data3
0
0
0
0
0
1
1
1
0
14
13 + 3
8
Data4
0
0
0
0
0
1
0
0
1
9
13 + 4
9
Data5
0
0
0
0
0
1
0
0
0
8
13 + 5
10
Data6
0
0
0
0
0
1
0
1
1
11
13 + 6
11
Data7
0
0
0
0
0
1
0
1
0
10
13 + 7
12
8.5.6
A0
ADD
ADD
calculated using
A2, A1 and A0 bits
not carry from
A2 to A3 bit.
Read Cycle CAS Latency = 3
0
Command
Address
1
2
3
4
5
6
7
8
9
10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
13
13
12
14
15
15
14
8
9
9
8
10
11
11
10
12
11
Read
13
DQ0~DQ7
Data Address {
Interleave mode
Sequential mode
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 23 -
W988D6FB / W988D2FB
8.5.7
CAS Latency field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The
minimum values of CAS Latency depends on the frequency of CLK. The minimum value which satisfies the
following formula must be set in this field.
A6
A5
A4
CAS Latency
0
1
0
2 clock
0
1
1
3 clock
 Reserved bits (A7, A8, A10, A11, An, BA0, BA1)
These bits are reserved for future operations. They must be set to 0 for normal operation.
 Single Write mode (A9)
This bit is used to select the write mode. When the A9 bit is 0, Burst Read and Burst Write mode are selected.
When the A9 bit is 1, Burst Read and Single Write mode are selected.
8.5.8
A9
Write Mode
0
Burst Read and Burst Write
1
Burst Read and Single Write
Mode Register Definition
Burst Length
A0
A1
Burst Length
A2
0
A1
0
A0
0
Sequential
1
Addressing Mode
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
2
4
8
1
1
1
A2
A3
A4
A5
CAS Latency
A6
A7
A0
"0"
Reserved
A8
"0"
Reserved
0
1
0
1
0
1
0
"0"
0
1
A12
"0"
BA0
"0"
BA1
"0"
Sequential
Interleave
A4
A11
Reserved
Reserved
Full
A0Page
Addressing Mode
0
0
1
"0"
Reserved
0
1
A5
A10
Write Mode
2
4
8
A3
A0
A6
0
0
0
A9
A0
Interleave
1
CAS Latency
Reserved
Reserved
2
3
Reserved
A9
A0
Single Write Mode
0
1
Burst read and Burst write
Burst read and single write
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 24 -
W988D6FB / W988D2FB
8.6
Extended Mode Register Description
The Extended Mode Register designates the operation condition while SDRAM is in Self Refresh
Mode and selects the output driver strength as full, 1/2, 1/4, or 1/8 strength. The register is divided into
two fields; (1) Partial Array Self Refresh field selects how much banks or which part of a bank need to
be refreshed during Self Refresh. (2) Driver Strength selected bit to control the size of output buffer.
The initial value of the Extended Mode Register after power-up is Full Driver Strength, and all banks
are refreshed during Self Refresh Mode.
A2 A1 A0
A0
Self-Refresh coverage
0
0
0
0
0
1
Banks 0 and 1 (BA1=0)
A2
0
1
0
A3
"0"
0
1
1
Bank 0 (BA1=BA0=0)
Reserved
1
0
0
Reserved
A4
"0"
1
0
1
1
1
0
Reserved
Reserved
1
1
1
Reserved
A1
Partial Array
Self Refresh
Reserved
A5
A6
Output Driver
A7
"0"
A8
"0"
A9
"0"
A10
"0"
A11
"0"
A12
"0"
BA0
"0"
All banks
Reserved
BA1
"1"
Extended
Mode
Register Set
A6
A5
Driver Strength
0
0
Full strength
0
1
1/2 strength
1
0
1/4 strength
1
1
1/8 strength
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 25 -
W988D6FB / W988D2FB
Simplified State Diagram
SELF
REFRESH
LF
SE
MODE
REGISTER
SET
AREF
PD
PD
EX
X
DE
DP
POWER
DOWN
ACT
DEEP
POWER
DOWN
POWER
DOWN
PD
ROW
ACTIVE
R
IT
T
BS
BS
T
PDEX
WR
ITA
D
EA
CSE
A
AD
RE
WRIT
CSE
READ
WRIT
CSEX
CSE
READA
WRITEA
PRE
PRE
CSEX
READA
SUSPEND
PR
E
CSEX
POWER
ON
READ
SUSPEND
READA
CSE
E
PR
POWER
APPLIED
READ
READ
WRITE
CSEX
WRITA
WRITEA
SUSPEND
AUTO
REFRESH
IDLE
D
DP
WRITE
SUSPEND
X
LE
SE
MRS/EMRS
W
R
8.7
PRECHARGE
Automatic sequence
Command sequence
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 26 -
W988D6FB / W988D2FB
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
Parameter
Values
Symbol
Unit
Min
Max
VDD
−0.5
2.3
V
Voltage on VDDQ relative to VSS
VDDQ
−0.5
2.3
V
Voltage on any pin relative to VSS
VIN, VOUT
−0.5
2.3
V
-25
85
-40
85
-55
150
°C
Voltage on VDD relative to VSS
Operating Temperature
TCASE
Storage Temperature
TSTG
Short Circuit Output Current
IOUT
±50
mA
PD
1.0
W
Power Dissipation
°C
Note:
stresses greater than those listed in “absolute maximum ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability
9.2
Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
VDD
1.7
1.8
1.95
V
VDDQ
1.7
1.8
1.95
V
Input High level Voltage
VIH
0.8 x VDDQ
-
VDDQ + 0.3
V
Input Low level Voltage
VIL
-0.3
-
+0.3
V
LVCOMS Output “H” Level Voltage (IOUT = -0.1 mA )
VOH
0.9 x VDDQ
-
-
V
LVCMOS Output “L” Level Voltage (IOUT = +0.1 mA )
VOL
-
-
0.2
V
Input Leakage Current
(0V ≤ VIN ≤ VDD, all other pins not under test = 0V)
II(L)
-1
-
1
A
Output Leakage Current (Output disable , 0V ≤ VOUT
≤ VDDQ)
IO(L)
-5
-
5
A
Supply Voltage
Supply Voltage (for I/O Buffer)
Note: VIH(max) = VDD/ VDDQ+1.2V for pulse width ≤ 5 nS
VIL(min) = VSS/ VSSQ-1.2V for pulse width ≤ 5 nS
9.3
Capacitance
Parameter
Symbol
Min.
Max.
Unit
CI
1.5
3.0
pf
Input Capacitance (CLK)
CCLK
1.5
3.5
pf
Input/Output Capacitance
CIO
3.0
5.0
pf
Input Capacitance
( A[n:0], BA0, BA1, CS , RAS , CAS , WE , DQM, CKE)
Note: These parameters are periodically sampled and not 100% tested.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 27 -
W988D6FB / W988D2FB
9.4
DC Characteristics
(x16, x32)
Sym.
-6
Max.
-75
Max.
IDD1
38
35
0.3
0.3
0.4
0.4
IDD2N
10
10
mA
Active mode; CKE = LOW; CS = HIGH; All banks active;
No accesses in progress
Standby current:
IDD3P
3
3
mA
3,4,6
Active mode; CKE = HIGH; CS = HIGH; All banks active
after tRCD met; No accesses in progress
Operating current:
Burst mode; READ or WRITE; All banks active; Half of DQ
toggling every cycle
Auto refresh current: tRFC = tRFC (min)
Auto refresh command cycling
IDD3N
20
15
mA
3,4,6
IDD4
75
70
mA
2,3,4
IDD5
50
50
mA
2,3,4,6
IZZ
10
10
μA
5,8
Parameter
Operating current:
Active mode; burst = 1; READ or WRITE; tRC = tRC (min)
Standby current:
Power-down mode, All banks idle, CKE = LOW.
Standby current:
Nonpower-down mode; All banks idle; CKE = HIGH
Standby current:
IDD2P
Deep Power Down Mode
9.5
Low
power
Normal
power
Unit Notes
mA
2,3,4
mA
5
Automatic Temperature Compensated Self Refresh Current Feature
IDD6
Normal Power
Low Power
TCSR Range
45°C
85°C
45°C
85°C
Full Array
200
300
250
400
1/2 Array
170
250
200
300
1/4 Array
150
220
180
250
Unit
μA
Notes:
1.
2.
A full initialization sequence is required before proper device operation is ensured.
IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs
open.
3. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition.
4. Address transitions average one transition every 2 clocks.
5. Measurement is taken 500mS after entering into this operating mode to provide tester measuring unit settling time.
6. Other input signals can transition only one time for every 2 clocks and are otherwise at valid Vih or Vil levels.
7. CKE is HIGH during the REFRESH command period tRFC (min) else CKE is LOW.
8. Typical values at 25°C (not a maximum value).
9. Enables on-die refresh and address counters.
10.Values for IDD6 85°C full array and partial array are guaranteed for the entire temperature range. All other IDD6 values are
estimated.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 28 -
W988D6FB / W988D2FB
9.6
9.6.1
AC Characteristics and Operating Condition
AC Characteristics
(Notes: 5, 6, 7)
Parameter
Sym.
-6
Min.
60
Active(a) to Active(b) Command Period
tRC
tRAS
tRCD
tCCD
tRP
tRRD
Write Recovery Time
Write-Recovery Time (Last data to Read)
Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Active to Read/Write Command Delay Time
Read/Write(a) to Read/Write(b) Command Period
Precharge to Active Command Period
CLK Cycle Time
CL* = 3
CL* = 2
CLK Low Level width
Access Time from CLK
CL* = 3
CL* = 2
Output Data High Impedance Time
CL* = 3
CL* = 2
Output Data Low Impedance Time
8
8
1
1
tCK
8
18
18
nS
8
12
15
nS
8
tWR
15
15
nS
tLDR
1
1
tCK
tCK
6
12
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode Register Set Cycle Time
Ref to Ref/Active Command Period
Self Refresh Exit to next valid Command Delay
7.5
12
100000
8
nS
1000
1000
50
nS
nS
1000
1000
nS
nS
2
2.5
nS
2
2.5
nS
5.4
6
tAC
2.5
5.4
8
2.5
5.4
6
tHZ
tLZ
tSB
tT
tDS
tDH
tAS
tAH
tCKS
tCKH
tCMS
tCMH
tREF
tMRD
tRFC
tXSR
100000
Notes
18
tOH
Output Data Hold Time
72.5
Unit
18
tCH
tCL
CLK High Level width
42
Max.
-75
Min. Max.
1
nS
nS
nS
5.4
6
1
nS
nS
nS
0
6
0
7.5
nS
0.3
1.2
0.3
1.2
nS
1.5
1.5
nS
1
1
nS
1.5
1.5
nS
1
1
nS
1.5
1.5
nS
1
1
nS
1.5
1.5
nS
1
1
64
2
7
7
nS
64
mS
2
tCK
72
72
nS
115
115
nS
8
* CL = CAS Latency
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 29 -
W988D6FB / W988D2FB
9.6.2
AC Test Condition
Symbol
Parameter
Value
Unit
VIH(min)
Input High Voltage Level (AC)
0.8 x VDDQ
V
VIL(max)
Input Low Voltage Level (AC)
0.2 x VDDQ
V
VOTR
Output Signal Reference Level
0.5 x VDDQ
V
I/O
Z0 = 50 Ohms
20pF
Time Reference Load
Input signal transition time between VIH and VIL is assumed as 1 Volts/nS.
Notes:
1. Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent
damage to the device. Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended
periods may affect deice reliability.
2. All voltages are referenced to VSS and VSSQ.
3. These parameters depend on the cycle rate. These values are measured at a cycle rate with the
minimum values of tCK and tRC . Input signals transition once per tCK period.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in note 9.
6. AC Test Conditions: (refer to 9.6.2).
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to
output voltage levels.
8. These parameters account for the number of clock cycles and depend on the operating frequency of
the clock, as follows: The number of clock cycles = specified value of timing / clock period (count
fractions as a whole number).
9. Power up Sequence: The SDRAM should be powered up by the following sequence of operations.
a. Power must be applied to VDD before or at the same time as VDDQ while all input signals are
held in the “NOP” state. The CLK signal will be applied at power up with power.
b. After power-up a pause of at least 200 μS is required. It is required that DQM and CKE signals
must be held “High” (VDD levels ) to ensure that the DQ output is in High-impedance state.
c. All banks must be precharged.
d. The Mode Register Set command must be issued to initialize the Mode Register.
e. The Extended Mode Register Set command must be issued to initialize the Extended Mode
Register.
f. Issue two or more Auto Refresh dummy cycles to stabilize the internal circuitry of the device.
The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 30 -
W988D6FB / W988D2FB
9.6.3
AC Latency Characteristics
CKE to clock disable (CKE Latency)
1
DQM to output to HI-Z (Read DQM Latency)
2
DQM to output to HI-Z (Write DQM Latency)
0
Write command to input data (Write Data Latency)
0
CS to Command input ( CS Latency)
0
Precharge to DQ Hi-Z Lead time
Precharge to Last Valid data out
Bust Stop Command to DQ Hi-Z Lead time
Bust Stop Command to Last Valid Data out
Read with Auto-precharge Command to Active/Ref Command
Write with Auto-precharge Command to Active/Ref Command
CL = 2
2
CL = 3
3
CL = 2
1
CL = 3
2
CL = 2
2
CL = 3
3
CL = 2
1
CL = 3
2
CL = 2
BL + tRP
CL = 3
BL + tRP
CL = 2
(BL+1) + tRP
CL = 3
(BL+1) + tRP
Cycle
Cycle + nS
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 31 -
W988D6FB / W988D2FB
10. CONTROL TIMING WAVEFORMS
10.1 Command Input Timing
tCK
tCL
tCH
VIH
CLK
VIL
tT
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tAS
tAH
tCMH
tT
tCMS
CS
RAS
CAS
WE
Address
BA0, BA1
tCKS
tCKH
tCKS
tCKH
tCKS
tCKH
CKE
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 32 -
W988D6FB / W988D2FB
10.2 Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
Address
BA0, BA1
tAC
tLZ
Valid
Data-Out
DQ
Read Command
tHZ
tAC
tOH
tOH
Valid
Data-Out
Burst Length
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 33 -
W988D6FB / W988D2FB
10.3 Control Timing of Input Data (x16)
(Word Mask)
CLK
tCMH
tCMS
tCMH
tCMS
LDQM
tCMH
tCMS
tCMH
tCMS
UDQM
tDS
DQ0~DQ7
tDS
Input
Data Valid
tDS
DQ8~DQ15
tDH
tDH
Input
Data Valid
tDH
Input
Data Valid
tDH
tDS
Input
Data Valid
tDS
tDS
tDH
tDS
Input
Data Valid
Input
Data Valid
tDS
tDH
tDH
Input
Data Valid
tDH
Input
Data Valid
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tDH
tDS
tDH
tCKS
CKE
tDS
DQ0~DQ7
Input
Data Valid
tDS
DQ8~DQ15
tDH
Input
Data Valid
tDS
Input
Data Valid
tDS
tDH
tDS
Input
Data Valid
tDS
tDH
Input
Data Valid
tDH
Input
Data Valid
tDH
Input
Data Valid
tDS
tDH
Input
Data Valid
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 34 -
W988D6FB / W988D2FB
10.4 Control Timing of Output Data (x16)
(Output Enable)
CLK
tCMS
tCMH
tCMH
tCMS
tCMH
tCMS
LDQM
tCMH
tCMS
UDQM
tAC
Output
Data Valid
tAC
tAC
tOH
Output
Data Valid
Output
Data Valid
Output
Data Valid
tHZ
tOH
tAC
tAC
tOH
OPEN
tOH
tOH
DQ8~DQ15
tLZ
tOH
Output
Data Valid
DQ0~DQ7
tAC
tHZ
tAC
tOH
tOH
Output
Data Valid
tAC
tLZ
OPEN
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tCKS
CKE
tAC
tOH
Output
Data Valid
DQ0~DQ7
tAC
tOH
DQ8~DQ15
tAC
tOH
tAC
tOH
tAC
tOH
Output
Data Valid
Output Data Valid
tAC
tAC
tOH
tOH
Output
Data Valid
Output Data Valid
tAC
tOH
Output
Data Valid
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 35 -
W988D6FB / W988D2FB
10.5 Control Timing of Input Data (x32)
(Word Mask)
CLK
tCMH
tCMS
tCMH
tCMS
DQM0
tCMH
tCMH
tCMS
tCMS
DQM1
tDS
Input
Data Valid
DQ0~DQ7
tDS
DQ8~DQ15
tDH
Input
Data Valid
tDS
DQ24~DQ31
tDH
tDH
Input
Data Valid
tDH
tDS
tDS
tDH
tDS
tDH
Input
Data Valid
tDS
tDH
Input
Data Valid
tDS
tDS
tDH
tDS
tDH
tDH
tDH
Input
Data Valid
tDH
tDS
tDS
Input
Data Valid
Input
Data Valid
tDS
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
tDS
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
tDS
DQ16~DQ23
tDS
tDH
tDS
Input
Data Valid
tDH
tDH
Input
Data Valid
tDS
Input
Data Valid
tDH
Input
Data Valid
*DQM2, 3 = “L”
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tDH
tDS
tDH
tCKS
CKE
tDS
DQ0~DQ7
Input
Data Valid
tDS
DQ8~DQ15
tDH
Input
Data Valid
tDS
DQ24~DQ31
Input
Data Valid
tDS
tDH
Input
Data Valid
tDS
tDS
tDH
Input
Data Valid
tDS
tDH
tDS
tDH
tDS
tDS
tDH
Input
Data Valid
Input
Data Valid
tDH
Input
Data Valid
tDS
Input
Data Valid
tDH
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
tDS
tDH
Input
Data Valid
tDH
Input
Data Valid
tDS
DQ16~DQ23
tDH
tDS
tDH
Input
Data Valid
tDS
tDH
Input
Data Valid
*DQM2, 3 = “L”
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 36 -
W988D6FB / W988D2FB
10.6 Control Timing of Output Data (x32)
(Output Enable)
CLK
tCMS
tCMH
tCMH
tCMS
tCMH
tCMS
DQM0
tCMH
tCMS
DQM1
tHZ
tAC
tAC
tAC
tAC
Output
Data Valid
Output
Data Valid
DQ8~DQ15
tAC
tOH
tAC
tAC
Output
Data Valid
tOH
tOH
Output
Data Valid
tAC
tAC
tOH
Output
Data Valid
DQ24~DQ31
tAC
tOH
Output
Data Valid
tAC
tOH
tOH
OPEN
tOH
Output
Data Valid
Output
Data Valid
tAC
tLZ
tAC
tOH
tOH
DQ16~DQ23
Output
Data Valid
tAC
tAC
Output
Data Valid
tHZ
tOH
tOH
tAC
tOH
OPEN
tAC
tOH
tOH
tLZ
Output
Data Valid
Output
Data Valid
DQ0~DQ7
tAC
tOH
tOH
tOH
Output
Data Valid
Output
Data Valid
DQM2, 3 = “L”
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tCKS
CKE
tAC
tOH
Output
Data Valid
DQ0~DQ7
tAC
Output
Data Valid
tAC
tAC
tAC
tAC
tOH
Output
Data Valid
tOH
tOH
Output Data Valid
tOH
DQ16~DQ23
tAC
tAC
Output
Data Valid
tOH
Output
Data Valid
tOH
tOH
DQ8~DQ15
tAC
tOH
Output Data Valid
tAC
tAC
tOH
DQ24~DQ31
tAC
tAC
tOH
tOH
tOH
Output
Data Valid
Output Data Valid
tAC
tAC
tOH
tOH
Output
Data Valid
Output Data Valid
tAC
tOH
Output
Data Valid
DQM2, 3 = “L”
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 37 -
W988D6FB / W988D2FB
10.7 Mode Register Set (MRS) Cycle
tRSC
CLK
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tAS
tAH
CS
RAS
CAS
WE
Address
BA0,BA1
Register
set data
next
command
A0
A1
Burst Length
A2
A3
Addressing Mode
A4
A5
CAS Latency
A2
0
0
0
0
1
1
1
1
A6
A0
A7
"0"
(Test Mode)
A8
"0"
Reserved
WriteA0
Mode
A9
A10
"0"
A0
A11
"0"
An
"0"
BA0
"0"
BA1
"0"
A1
A0 A0
A0
0
0
A0
0
1
A0
1
0
A0
1
1
A0
0
0
A0
0
1
A0
1
0
A0
1
1
A0
A3
0
1
A6
0
0
0
0
1
Reserved
A5
A0 A4
A0
0
0
A0
0
1
A0
1
0
A0
1
1
A0
0
0
A0
A9
0
1
Burst Length
Sequential
Interleave
1
1
2
2
4
4
8
8
Reserved
Reserved
Full Page
Addressing Mode
Sequential
Interleave
CAS Latency
Reserved
Reserved
2
3
Reserved
Single Write Mode
Burst read and Burst write
Burst read and single write
* "Reserved" should stay "0" during MRS cycle.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 38 -
W988D6FB / W988D2FB
10.8 Extended Mode register Set (EMRS) Cycle
tRSC
CLK
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tAS
tAH
CS
RAS
CAS
WE
Address
BA0,BA1
Register
set data
next
command
A0
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PASR
A1
A2
A3
0
A4
0
A5
Reserved
Output Driver
A6
A7
0
A8
0
A9
0
A10
0
A11
0
An
0
BA0
0
BA1
1
Partial Self Refresh
All banks
Bank0,1 (BA1=0)
Bank0 (BA0= BA1=0)
Reserved
Reserved
A6
0
0
1
1
Extended
Mode
Register Set
A5
0
1
0
1
Output Driver Strength
Full Strength
1/2 Strength
1/4 Strength
1/8 Strength
* "Reserved" should stay "0" during EMRS cycle.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 39 -
W988D6FB / W988D2FB
11. OPERATING TIMING EXAMPLE
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
tRC
tRC
RAS
tRAS
tRP
tRP
tRAS
tRAS
tRP
tRAS
CAS
WE
BA0
BA1
tRCD
A10
RAa
Address
RAa
tRCD
tRCD
RBb
CAw
tRCD
RAc
CBx
RBb
RAe
RBd
RAc
CAy
RBd
CBz
RAe
DQM
CKE
tAC
DQ
tRRD
Bank #0
Active
Bank #1
aw1
aw2
aw3
bx0
tRRD
Read
Precharge
Active
bx1
bx3
bx2
cy0
tRRD
Active
cy1
cy2
cy3
tRRD
Precharge
Read
Precharge
Read
tAC
tAC
tAC
aw0
Active
Active
Read
Bank #2
Idle
Bank #3
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 40 -
W988D6FB / W988D2FB
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)
0
1
2
3
4
5
6
7
8
9
11
10
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
tRC
tRC
RAS
tRAS
tRP
tRAS
tRAS
tRP
tRAS
tRP
CAS
WE
BA0
BA1
tRCD
A10
Address
tRCD
tRCD
RAa
RBb
RAa
CAw RBb
tRCD
RBd
RAc
CBx
RAc
RAe
RBd
CAy
CBz
RAe
DQM
CKE
tAC
DQ
tRRD
Bank #0
Active
Bank #1
aw1
aw2
aw3
bx0
bx1
tRRD
Active
AP*
bx2
bx3
cy0
cy1
tRRD
Read
Active
tAC
tAC
tAC
aw0
cy3
dz0
tRRD
Read
AP*
Read
cy2
Active
Active AP*
Read
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 41 -
W988D6FB / W988D2FB
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
tRP
CAS
WE
BA0
BA1
tRCD
A10
RAa
Address
RAa
tRCD
tRCD
RBb
CAx
RAc
RBb
RAc
CBy
CAz
DQM
CKE
tAC
DQ
tAC
ax0
ax1
tRRD
Bank #0
Active
Bank #1
ax2
ax3
ax4
ax5
tAC
by0
by4
by1
by5
by6
by7
CZ0
tRRD
Read
Precharge
ax6
Precharge
Active
Read
Active
Read
Precharge
Bank #2
Idle
Bank #3
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 42 -
W988D6FB / W988D2FB
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tRC
CS
RAS
tRAS
tRP
tRAS
tRAS
tRP
CAS
WE
BA0
BA1
tRCD
A10
RAa
Address
RAa
tRCD
tRCD
RAc
RBb
CAx
CBy
RBb
RAc
CAz
DQM
CKE
tAC
DQ
ax0
ax1
ax2
Active
ax4
ax5
AP*
Read
Active
Bank #1
ax3
ax6
ax7
by0
by1
by4
Active
Read
by5
by6
CZ0
tRRD
tRRD
Bank #0
tAC
tAC
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 43 -
W988D6FB / W988D2FB
11.5 Interleaved Bank Write (Burst Length = 8)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
CAS
tRCD
tRCD
tRCD
WE
BA0
BA1
A10
Address
RBb
RAa
RAa
CAx
RAc
CBy
RBb
RAc
CAz
DQM
CKE
DQ
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
tRRD
Bank #0
Active
Bank #1
Bank #2
Bank #3
by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
Precharge
Write
Active
Write
Active
Write
Precharge
Idle
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 44 -
W988D6FB / W988D2FB
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRP
tRAS
tRAS
CAS
WE
BA0
BA1
tRCD
A10
Address
tRCD
RAa
RAa
tRCD
RBb
CAx
RAb
CBy
RBb
RAc
CAz
DQM
CKE
ax0
DQ
ax1
ax4
ax5
ax6
ax7
by0
by1
AP*
Write
Active
Bank #1
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
tRRD
Bank #0 Active
by2
Write
Active
Write
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 45 -
W988D6FB / W988D2FB
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tCCD
tCCD
tCCD
CS
tRAS
tRAS
RAS
CAS
WE
BA0
BA1
tRCD
A10
RAa
Address
RAa
tRCD
RBb
CAI
RBb
CBx
CAy
CAm
CBz
DQM
CKE
DQ
a0
a1
a2
a3
tAC
tAC
tAC
tAC
bx0
bx1
tAC
Ay0
Ay1
Ay2
am0
am1
am2
bz0
bz1
bz2
bz3
tRRD
Bank #0
Active
Read
Active
Bank #1
Read
Read
Read
Precharge
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 46 -
W988D6FB / W988D2FB
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)
0
1
2
3
5
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRAS
RAS
CAS
WE
BA0
BA1
tRCD
A10
RAa
Address
RAa
CAx
CAy
DQM
CKE
tAC
DQ
tWR
ax0
Q Q
Bank #0
Active
ax1
ax3
ax2
Q
Q
ax5
ax4
Q
Q
Read
ay1
ay0
D
D
Write
ay2
D
ay3
D
ay4
D
Precharge
Bank #1
Bank #2
Bank #3
Idle
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 47 -
W988D6FB / W988D2FB
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
CAS
WE
BA0
BA1
tRCD
A10
RAa
Address
RAa
tRCD
RAb
CAw
RAb
CAx
DQM
CKE
tAC
DQ
tAC
aw0
Bank #0
Active
Read
aw1
aw2
aw3
AP*
bx0
Active
Read
bx1
bx2
bx3
AP*
Bank #1
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 48 -
W988D6FB / W988D2FB
11.10 Auto-precharge Write (Burst Length = 4)
0
1
2
3
6
5
4
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
CAS
WE
BA0
BA1
tRCD
tRCD
A10
RAa
Address
RAa
RAb
CAw
RAb
RAc
CAx
RAc
DQM
CKE
DQ
aw0
Active
Bank #0
Write
aw1
aw2
aw3
bx0
AP*
Active
Write
bx1
bx2
bx3
AP*
Active
Bank #1
Bank #2
Idle
* AP is the internal precharge start timing
Bank #3
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 49 -
W988D6FB / W988D2FB
11.11 Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tRP
tRC
tRC
CS
RAS
CAS
WE
BA0,BA1
A10
Address
DQM
CKE
DQ
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 50 -
W988D6FB / W988D2FB
11.12 Self Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRP
RAS
CAS
WE
BA0,BA1
A10
Address
DQM
tSB
tCKS
tCKS
CKE
tCKS
DQ
tRFC
All Bank
Precharge
Self Refresh
Entry
Device Deselect (DSL) Cycle
Self Refresh
Exit
Arbitrary Cycle
Note: The device exit the Self Refresh mode asynchronously at the rising edge of the CKE signal.
After CKE goes high, the Device Deselect or No-operation command must be registered at the immediately following
CLK rising edge, and CKE must remain high at least for tCKS delay immediately after exit the Self Refresh Mode.
A bust of 8K auto refeesh cycle within 7.8μs before entering and exiting is necessary if the system does not use the
auto refresh function.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 51 -
W988D6FB / W988D2FB
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
t RCD
WE
BA0
BA1
A10
Address
RBa
RBa
CBv
CBw
CBx
CBy
CBz
aw0
ax0
ay0
az0
az1
az2
az3
D
D
D
Q
Q
Q
Q
DQM
CKE
tAC
tAC
DQ
Bank #0
Active
av0
av1
av2
av3
Q
Q
Q
Q
Read
Single Write Read
Bank #1
Bank #2
Idle
Bank #3
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 52 -
W988D6FB / W988D2FB
11.14 Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BA
A10
RAa
Address
RAa
RAa
CAa
RAa
CAx
DQM
tSB
tSB
CKE
tCKS
tCKS
DQ
ax0
Active
tCKS
tCKS
ax1
ax2
DSL
ax3
Active
Precharge
&
Power Down Mode Entry
Power Down Power Down
Mode Entry
Mode Exit
Device Deselect
Power Down Mode Exit
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Violating refresh requirements during power-down may result in a loss of data.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 53 -
W988D6FB / W988D2FB
11.15 Deep Power Down Mode Entry
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRP
RAS
CAS
WE
BA0,BA1
A10
Address
DQM
tSB
CKE
tCKS
DQ
Active Banks Precharge
Deep Power Down Entry
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 54 -
W988D6FB / W988D2FB
11.16 Deep Power Down Mode Exit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRP
tMRD
tMRD
RAS
CAS
WE
A10
OP-Code
OP-Code
Address
DQM
CKE
tCKS
DQ
200μs
DSL
All Banks Precharge
Auto Refresh
tRFC
tRFC
Auto Refresh
Extended Mode
Mode Register Set Register Set Arbitrary Cycle
Deep Power Down Exit
Issue Auto Refresh cycle two or more
Note:
The device exits the Deep Power Down Mode asynchronously at the rising edge of the CKE signal.
After CKE goes high, the Device Deselect or No-operation command must be register at the immediately
following CLK rising edge, and CKE must remain high at least for tCKS delay immediately after exiting
the Deep Power Down Mode.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 55 -
W988D6FB / W988D2FB
11.17 Auto-precharge Timing (Read Cycle)
0
1
Read
AP
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) burst length = 1
Command
Act
tRP
DQ
Q0
( b ) burst length = 2
Command
Read
AP
Act
tRP
DQ
Q0
Q1
( c ) burst length = 4
Command
Read
AP
Act
tRP
DQ
Q0
Q1
Q0
Q1
Q2
Q3
( d ) burst length = 8
Command
Read
AP
DQ
Q2
Q3
Q4
Q5
Q6
Act
tRP
Q7
(2) CAS Latency=3
( a ) burst length = 1
Command
Read
AP
Act
tRP
Q0
DQ
( b ) burst length = 2
Command
Read
AP
Act
tRP
Q0
DQ
Q1
( c ) burst length = 4
Command
Read
AP
Act
tRP
Q0
DQ
Q1
Q2
Q3
( d ) burst length = 8
Command
Read
AP
Act
tRP
Q0
DQ
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Note:
Read
AP
Act
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activ ate command.
When the Auto precharge command is asserted, the period f rom Bank Activ ate command to
the start of internal precgarging must be at leastRAS
t (min).
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 56 -
W988D6FB / W988D2FB
11.18 Auto-precharge Timing (Write Cycle)
0
(1) burst length = 1
1
Write
2
3
Write/A
AP
8
10
11
12
Act
tWR
Command
Act
AP
Write/A
tWR’
D0
tRP
D1
(3) burst length = 4
PRE
Write
tWR
Command
Act
AP
Write/A
D0
tWR’
D1
D2
tRP
D3
PRE
Write
tWR
Write/A
tWR’
Command
DQ
9
PRE
Write
DQ
7
D0
(2) burst length = 2
(4) burst length = 8
6
tRP
tWR’
DQ
5
tWR
Command
DQ
4
PRE
Act
AP
D0
Note:
1.
D1
Write
Write/A
D2
D3
D4
D5
D6
tRP
D7
represents the write command.
represents the Write with Auto precharge command.
AP
represents the start of internal precharging.
PRE
represents the Precharge command.
Act
represents the Bank Activate command.
2. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal
precgarging must be at least tRAS (min).
3. For WRITE without auto-precharge, tWR = 15nS.
4. For WRITE with auto-precharge, tWR = 2tCK.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 57 -
W988D6FB / W988D2FB
11.19 Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
1
0
2
3
4
5
D1
D2
D3
D0
D1
D2
D1
D2
D3
D1
D2
6
7
8
9
10
11
(1) CAS Latency=2
Read
( a ) Command
Write
DQM
DQ
D0
( b ) Command
Read
Write
DQM
DQ
(2) CAS Latency=3
Read
( a ) Command
D3
Write
DQM
D0
DQ
Read
( b ) Command
Write
DQM
D0
DQ
D3
Note: The Output data must be masked by DQM to avoid I/O conflict.
11.20 Timing Chart of Write to Read Cycle
In the case of Burst
Length = 4
(1) CAS latency = 2
(a) Command
0
1
3
2
4
5
6
7
QO
Q1
Q2
Q3
QO
Q1
Q2
Q3
QO
Q1
Q2
Q3
QO
Q1
Q2
8
9
10
11
Read
Write
tLDR
DQM
DQ
(b) Command
DO
Write
Read
tLDR
DQM
DQ
(2) CAS latency = 3
(a) Command
D1
DO
Read
Write
tLDR
DQM
DQ
(b) Command
DO
Write
Read
tLDR
DQM
DQ
DO
D1
Q3
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 58 -
W988D6FB / W988D2FB
11.21 Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a ) CAS latency =2
C omma nd
Read
BST
Q0
DQ
Q1
Q2
Q0
Q1
Q3
Q4
( b )CAS latency = 3
C omma nd
Read
BST
DQ
Q2
Q3
Q4
(2) Write cycle
C omma nd
DQ
Write
Q0
BST
Q1
Q2
Note:
Q3
Q4
BST
represents the Burst stop command
11.22 Timing Chart of Burst Stop Cycle (Precharge Command)
In the case of
Burst Length = 8
(1) Read cycle
(a) CAS latency =2
Command
0
1
2
3
4
Read
5
6
7
8
9
10
11
PRCG
DQ
Q0
Q1
Q2
Q3
Q4
(b) CAS latency =3
Command
Read
PRCG
DQ
Q0
Q1
Q2
(2) Write cycle
(a) CAS latency =2
Command
Q3
Q4
PRCG
Write
Write DQM Latency = 0
tWR
DQM
DQ
(b) CAS latency =3
Command
Q0
Q1
Q2
Q3
Q4
PRCG
Write
tWR
Write DQM Latency = 0
DQM
DQ
Q0
Q1
Q2
Q3
Q4
Note: PRCG represents the Precharge command.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 59 -
W988D6FB / W988D2FB
11.23 CKE/DQM Input Timing (Write Cycle)
CLK cycle No.
1
2
3
D1
D2
D3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
D5
DQM MASK
D6
CKE MASK
( 1)
CLK cycle No.
1
2
3
D1
D2
D3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
DQM MASK
D5
D6
5
6
7
D4
D5
D6
CKE MASK
( 2)
CLK cycle No.
1
2
3
D1
D2
D3
4
External
CLK
Internal
CKE
DQM
DQ
CKE MASK
( 3)
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 60 -
W988D6FB / W988D2FB
11.24 CKE/DQM Input Timing (Read Cycle)
CLK cycle No.
1
2
3
4
Q1
Q2
Q3
Q4
6
5
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Open
Open
(1)
CLK cycle No.
1
2
3
Q1
Q2
Q3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q4
Q6
Open
(2)
CLK cycle No.
1
2
Q1
Q2
3
4
5
6
7
Q4
Q5
Q6
External
CLK
Internal
CKE
DQM
DQ
Q3
(3)
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 61 -
W988D6FB / W988D2FB
12. PACKAGE SPECIFICATION
12.1 LPSDR x16
Package Outline VFBGA 54 Balls (8x9 mm2, Ball pitch:0.8mm, Ø =0.42mm)
–A–
D1
aaa
D
PIN #1
e
–B–
J
H
G
E
E1
F
E
D
C
Φb
B
A
1
2
3
4
5
6
7
8
aaa
9
Note: Dimensions apply to Solder Balls Post-Reflow.
The Pre-Reflow diameter is 0.42 on a 0.4 SMD Ball Pad.
CAVITY
NOM
MAX
MIN
NOM
MAX
---
---
1.025
---
---
0.040
A1
0.275
0.300
0.325
0.011
0.012
0.013
A2
0.61
0.66
0.71
0.024
0.026
0.028
D
7.90
8.00
8.10
0.311
0.315
0.319
E
8.90
9.00
9.10
0.350
0.354
0.358
D1
---
6.40
---
---
0.252
---
E1
---
6.40
---
---
0.252
---
e
---
0.80
---
---
0.031
---
b
0.40
0.45
0.50
0.016
0.018
0.020
aaa
0.15
0.006
bbb
0.20
0.008
ccc
0.12
0.005
A
MIN
A
bbb C
A1
Symbol
Dimension in inch
A2
//
Dimension in mm
–C–
SOLDER BALL
ccc
SEATING PLANE
C
BALL LAND
BALL OPENING
Note: 1. Ball land : 0.5mm
2. Ball opening : 0.4mm
3. PCB Ball land suggested ≤ 0.4mm
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 62 -
W988D6FB / W988D2FB
12.2 LPSDR x32
Package Outline VFBGA 90 Balls (8x13 mm2, Ball pitch:0.8mm, Ø =0.42mm)
–A–
D1
aaa
D
PIN #1
e
–B–
R
P
N
M
L
K
E
E1
J
H
G
F
E
D
C
Φb
B
A
1
2
3
4
5
6
7
8
aaa
9
Note: Dimensions apply to Solder Balls Post-Reflow.
The Pre-Reflow diameter is 0.42 on a 0.4 SMD Ball Pad.
CAVITY
MIN
NOM
MAX
MIN
NOM
MAX
A
---
---
1.025
---
---
0.040
A1
0.275
0.300
0.325
0.011
0.012
0.013
A2
0.61
0.66
0.71
0.024
0.026
0.028
D
7.90
8.00
8.10
0.311
0.315
0.319
E
12.90
13.00
13.10
0.508
0.512
0.516
D1
---
6.40
---
---
0.252
---
E1
---
11.20
---
---
0.441
---
e
---
0.80
---
---
0.031
---
b
0.40
0.45
0.50
0.016
0.018
0.020
aaa
0.15
0.006
bbb
0.20
0.008
ccc
0.12
0.005
bbb C
A
Dimension in inch
A1
Dimension in mm
A2
//
Symbol
–C–
SOLDER BALL
SEATING PLANE
ccc C
BALL LAND
BALL OPENING
Note: 1. Ball land : 0.5mm
2. Ball opening : 0.4mm
3. PCB Ball land suggested ≤ 0.4mm
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 63 -
W988D6FB / W988D2FB
13. REVISION HISTORY
VERSION
DATE
PAGE
A01-001
Apr. 28, 2011
All
A01-002
May 18, 2011
9~11
Mar. 12, 2012
57
59
66
A01-004
Aug. 15, 2013
All
9
12
14
15, 26, 30
A01-005
Mar. 20, 2014
All
30
Refine format
Revise note 9.b of section 9.6.2 typo: 200μA --> 200μS
A01-006
Sep. 22, 2014
16
Refine Refresh operation description of section 7.1.16
A01-003
DESCRIPTION
Product datasheet for customer
Update IDD4 value & Add Normal power grade
Update DPD Mode Exit figure
Update Auto precharge write cycle figure
Add Part #
Update table of contents
Update VDD;VDDQ;VIN/VOUT value of section 7.1
Remove note of section 7.4
Update table of 7.6.2
Update text typo
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Publication Release Date: Sep. 22, 2014
Revision: A01-006
- 64 -