WM2613 Byte-wide Parallel Input, 12-bit Voltage Output DAC Production Data, June 1999, Rev 1.0 FEATURES • • • • • • DESCRIPTION Dual 12-bit voltage output DAC Dual supply 2.7V to 5.5V operation DNL ± 0.4 LSB, INL ± 1.5 LSB Programmable settling time 1µ µ s or 3µ µ s typical 8-bit micro controller compatible interface Power down mode (10nA) The WM2613 is a 12-bit voltage output, resistor string, digital-toanalogue converter. The DAC can be powered down under software or hardware control, reducing power consumption to 10nA. The device has an 8-bit microcontroller compatible parallel interface. The eight data LSBs, the four data MSBs, and the three control bits are written using three different addresses. APPLICATIONS • • • • • • • Excellent performance is delivered with a typical DNL of 0.4 LSBs. The output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a Class A output stage (slow mode, class AB). The settling time of the DAC is software programmable to allow the designer to optimize speed versus power dissipation. Battery powered test instruments Digital offset and gain adjustment Battery operated/remote industrial controls Machine and motion control devices Wireless telephone and communication systems Speech synthesis Arbitrary waveform generation The device is available in a 20-pin TSSOP package. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported. ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE WM2613CDT 0° to 70°C 20-pin TSSOP WM2613IDT -40° to 85°C 20-pin TSSOP BLOCK DIAGRAM TYPICAL PERFORMANCE DVDD (10) AVDD (11) 1 AVDD = DVDD = 5V, VREF = 2.048V, Speed = Fast mode, Load = 10k/100pF 0.8 REFIN(12) POWERDOWN/ SPEED CONTROL NPD (15) 3-BIT CONTROL LATCH A[0-1] (8,7) NCS (18) NWE (17) PARALLEL INTERFACE AND CONTROL LOGIC 0.6 X1 0.4 DNL - LSB SPD (9) REFERENCE INPUT BUFFER DAC OUTPUT BUFFER 4-BIT DAC MSW HOLDING LATCH 12-BIT DAC LATCH X2 (13) OUT 0.2 0 -0.2 -0.4 8-BIT DAC LSW HOLDING LATCH -0.6 -0.8 -1 D[0-7] (19,20, 1-6) 0 POWER-ON RESET WM2613 (14) GND 512 1024 1536 2048 2559 3071 3583 4095 DIGITAL CODE (16) NLDAC WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ Terms and conditions. Master rev 1.0.doc June 17, 1999 14:12 1999 Wolfson Microelectronics Ltd. WM2613 Production Data Rev 1.0 PIN CONFIGURATION D2 1 20 D1 D3 2 19 D0 D4 3 18 NCS D5 4 17 NWE D6 5 16 NLDAC D7 6 15 NPD A1 7 14 GND A0 8 13 OUT SPD 9 12 REFIN DVDD 10 11 AVDD PIN DESCRIPTION PIN NO NAME TYPE 1 D2 Digital input Data input. 2 D3 Digital input Data input. 3 D4 Digital input Data input. 4 D5 Digital input Data input. 5 D6 Digital input Data input. 6 D7 Digital input Data input. 7 A1 Digital input Address input. 8 A0 Digital input Address input. 9 SPD Digital input Speed select. Digital input. 10 DVDD Supply 11 AVDD Supply 12 REFIN Analogue input Voltage reference input. 13 OUT Analogue output DAC analogue voltage output. 14 GND Supply 15 NPD Digital input Power down. Active low digital input which powers down all analogue circuits. 16 NLDAC Digital input Load DAC. Digital input active low. NLDAC must be taken low to update the DAC latch from the holding latches. 17 NWE Digital input Write enable. Digital input active low. 18 NCS Digital input Chip select. Digital input active low. 19 D0 Digital input Data input. 20 D1 Digital input Data input. WOLFSON MICROELECTRONICS LTD DESCRIPTION Digital positive power supply. Analogue positive power supply. Ground. Production Data Rev 1.0 June 1999 2 WM2613 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION MIN MAX Supply voltage differences, AVDD to DVDD -2.8V 2.8V Reference input voltage -0.3V DVDD + 0.3V Supply voltages, AVDD or DVDD to GND 7V Digital input voltage range to GND Operating temperature range, TA -0.3V AVDD + 0.3V WM2613C 0°C 70°C WM2613I -40°C 85°C -65°C 150°C Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds 260°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL Supply voltage AVDD, DVDD TEST CONDITIONS MIN 2.7 TYP MAX UNIT 5.5 V High-level digital input voltage VIH DVDD = 2.7V to 5.5V Low-level digital input voltage VIL DVDD = 2.7V to 5.5V 0.8 V Reference voltage to REFIN VREF See Note AVDD - 1.5 V Load resistance RL Load capacitance CL Operating free-air temperature TA 2 V 2 kΩ 100 pF WM2613CDT 0 70 °C WM2613IDT -40 85 °C Note: Reference voltages greater than AVDD/2 will cause saturation for large DAC codes. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 3 WM2613 Production Data Rev 1.0 ELECTRICAL CHARACTERISTICS Test Conditions: RL = 10kΩ, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications Resolution 12 bits Integral non-linearity INL See Note 1 ± 1.5 ±4 LSB Differential non-linearity DNL See Note 2 ± 0.4 ±1 LSB Zero code error ZCE See Note 3 3 ± 20 mV GE See Note 4 ± 0.25 ± 0.5 % FSR d.c. PSRR See Note 5 0.5 mV/V Zero code error temperature coefficient See Note 6 3 ppm/°C Gain error temperature coefficient See Note 6 1 ppm/°C Gain error D.c power supply rejection ratio DAC Output Specifications Output voltage range 0 Output load regulation AVDD - 0.4 V 0.1 0.3 % Slow 0.5 1.3 mA Fast 1.6 3.0 mA Slow 0.4 1.1 mA Fast 1.4 2.7 mA No load, all digital inputs 0V or DVDD. See Note 9 0.01 10 µA 2kΩ to 10kΩ load. See Note 7 Power Supplies Active supply current IDD No load, VIH = DVDD, VIL = 0V AVDD = DVDD = 5V, VREF = 2.048V See Note 8 AVDD = DVDD = 3V, VREF = 1.024V Power down supply current Dynamic DAC Specifications Slew rate DAC code 128 to 4095, 10%-90% See Note 10 Settling time Glitch energy Signal to noise ratio Signal to noise and distortion ratio Total harmonic distortion Spurious free dynamic range WOLFSON MICROELECTRONICS LTD Slow 1.5 V/µs Fast 8 V/µs DAC code 128 to 4095 Slow 3.5 µs Fast 1.0 µs 1 nV-s Code 2047 to code 2048 SNR fS = 480ksps, fOUT = 1kHz BW = 20kHz, TA = 25°C See Note 12 65 78 dB SNRD fS = 480ksps, fOUT = 1kHz BW = 20kHz, TA = 25°C See Note 12 58 69 dB THD fS = 480ksps, fOUT = 1kHz BW = 20kHz, TA = 25°C See Note 12 SPFDR fS = 480ksps, fOUT = 1kHz BW = 20kHz, TA = 25°C See Note 12 -68 60 72 -60 dB dB Production Data Rev 1.0 June 1999 4 WM2613 Production Data Test Conditions: RL = 10kΩ, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Reference Reference input resistance RREFIN 10 MΩ Reference input capacitance CREFIN 5 pF -60 dB Slow 1 MHz Fast 1.6 MHz Reference feedthrough VREF = 1VPP at 1kHz + 1.024V d.c., DAC code 0 Reference input bandwidth VREF = 0.2VPP + 1.024V d.c. DAC code 2048 Digital Inputs High level input current IIH Input voltage = DVDD Low level input current IIL Input voltage = 0V Input capacitance CI 1 µA -1 µA 8 pF Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load. 8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current will increase. 9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test. 10. Slew rate results are for the lower value of the rising and falling edge slew rates. 11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested 12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fS. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 5 WM2613 Production Data Rev 1.0 SERIAL INTERFACE tSUD X D[0-7] tHD Data tSUA A[0-1] X X tHA Address X tSUCSWE NCS tWWE NWE tSUWELD tWLD NLDAC Figure 1 Timing Diagram SYMBOL tSUCSWE tSUDWE TEST CONDITIONS MIN Setup time NCS low before positive NWE edge Data ready before positive NWE edge TYP 13 MAX UNIT ns 9 ns tHD Data hold after positive NWE edge 0 ns tSUA Setup time for address bits A0, A1 17 ns tHA Address hold after positive NWE edge 0 tSUWELD Positive NWE edge before NLDAC low 0 ns tWWE High pulse width of NWE 10 ns tWLD Low pulse width of NLDAC 10 ns WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 6 WM2613 Production Data TYPICAL PERFORMANCE GRAPHS 3 A V D D = D V D D = 5 V , V REF = 2 . 0 4 8 V , S p e e d = F a s t m o d e , L o a d = 1 0 k / 1 0 0 p F 2 INL - LSB 1 0 -1 -2 -3 0 512 1024 1536 2048 2559 3071 3583 4095 DIGITAL CODE Figure 2 Integral Non-Linearity 3 5 AVDD = DVDD = 5V, VREF = 2V, Input Code = 0 AVDD = DVDD =3V, VREF = 1V, Input Code = 0 4.5 2.5 4 3.5 OUTPUT VOLTAGE - V OUTPUT VOLTAGE - V 2 1.5 3 2.5 2 1 1.5 1 0.5 0.5 0 0 0 1 2 3 4 5 6 7 8 9 ISINK - mA Slow 0 10 1 Figure 3 Sink Current AVDD = DVDD = 3V 3 4 5 6 7 8 9 Slow ISINK - mA 10 Fast Figure 4 Sink Current AVDD = DVDD = 5V 4.105 2.065 AVDD = DVDD = 5V, VREF = 2V, Input Code = 4095 AVDD = DVDD = 3V, VREF = 1V, Input Code = 4095 2.06 4.1 2.055 4.095 OUTPUT VOLTAGE - V OUTPUT VOLTAGE - V 2 Fast 2.05 2.045 2.04 4.09 4.085 4.08 2.035 4.075 2.03 4.07 2.025 4.065 0 1 2 3 4 5 6 7 ISOURCE - mA 8 9 Slow Figure 5 Source Current AVDD = DVDD = 3V WOLFSON MICROELECTRONICS LTD 10 Fast 0 1 2 3 4 5 6 7 8 ISOURCE - mA 9 Slow 10 Fast Figure 6 Source Current AVDD = DVDD = 5V Production Data Rev 1.0 June 1999 7 WM2613 Production Data Rev 1.0 DEVICE DESCRIPTION GENERAL FUNCTION The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: Output voltage = 2(VREF ) CODE 4096 INPUT 1111 1111 OUTPUT 1111 2(VREF ) : 4095 4096 : 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 : 2(VREF ) 2(VREF ) 2049 4096 2048 = VREf 4096 2(VREF ) 2047 4096 : 2(VREF ) 1 4096 0V Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2 POWER ON RESET An internal power-on-reset circuit resets the DAC register to all 0s on power-up. BUFFER AMPLIFIER The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ load with a 100pF load capacitance. EXTERNAL REFERENCE The reference voltage input is buffered which makes the DAC input resistance independent of code. The REFIN pin has an input resistance of 10MΩ and an input capacitance of typically 5pF. The reference voltage determines the DAC full-scale output. HARDWARE CONFIGURATION OPTIONS The device has three configuration options that are controlled by device pins. DEVICE POWER DOWN The device can be powered-down by pulling pin NPD (pin 15) low. This powers down the DAC. This will reduce power consumption significantly. The NPD pin overrides the software control bit PWR. When the power down function is released the device reverts to the DAC code set prior to power down. SETTLING TIME The settling time of the device can be controlled by pin SPD (pin 9). A ONE on pin SPD will ensure a FAST settling time; a ZERO will ensure a SLOW settling time. The SPD pin high overrides the software control bit SPD. SIMULTANEOUS DAC UPDATE The NLDAC pin (Pin 16) can be held high to prevent word writes from updating the DAC latch. By writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded into the DAC latch. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 8 WM2613 Production Data PARALLEL INTERFACE The device latches data on the positive edge of NWE. It must be enabled with NCS low. Whether the data is written to one of the DAC holding latches (MSW, LSW) or the control register, depends on the address bits A1 and A0. NLDAC low updates the DAC with the value in the holding latch, see Figure 7. NLDAC is an asynchronous input and can be held low, if a synchronous update is not necessary. Alternatively, the RLDAC bit of the control register can be used to synchonously update the DAC latch via software control, see Figure 8. X D[0-7] MSW 0 A[0-1] X X LSW X 1 X NCS NWE NLDAC Figure 7 Example of a Complete Write Cycle Using NLDAC to Update the DAC X D[0-7] A[0-1] X MSW 0 X X LSW 1 X X Control 3 X X NCS NWE NLDAC Figure 8 Example of a Complete Write Cycle Using the Control Word to Update the DAC. If NLDAC is held low as shown in Figure 8, latch will be transparent. This assumes that the RLDAC control register bit is low at the start and is written high on the final write. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 9 WM2613 Production Data Rev 1.0 SOFTWARE CONFIGURATION OPTIONS DATA FORMAT The WM2613 writes data either to one of the DAC holding latches or to the control register depending on the address bits A1 and A0. A1 A0 REGISTER 0 0 DAC LSW holding 0 1 DAC MSW holding 1 0 Reserved 1 1 Control D7 D6 D5 D4 D3 D2 D1 D0 X X X X X RLDAC PWR SPD Table 2 Register Map PROGRAMMABLE SETTLING TIME Settling time is a software selectable 3.5µs or 1µs, typical to within ±0.5LSB of final value. This is controlled by the value of SPD – Bit D12. A ONE defines a settling time of 1µs, a ZERO defines a settling time of 3.5µs. PIN BIT SPD SPD 0 0 Slow 0 1 Fast 1 0 Fast 1 1 Fast MODE Table 3 Programmable Settling Time PROGRAMMABLE POWER DOWN The power down function can be controlled by PWR. A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts to the DAC code set prior to power down. PIN BIT NPD PWR 0 0 0 1 Down 1 0 Normal 1 1 Down POWER Down Table 4 Programmable Power Down LOAD DAC LATCH Bit RLDAC controls the function of the DAC latch. A ONE configures the DAC latch as transparent. A ZERO configures the DAC latch to be controlled by pin NLDAC. PIN BIT NLDAC RLDAC LATCH 0 0 Transparent 0 1 Transparent 1 0 Hold 1 1 Transparent Table 5 Load DAC Latch WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 10 WM2613 Production Data PACKAGE DIMENSIONS DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm) b DM008.C e 20 11 E1 E GAUGE PLANE 1 θ 10 D 0.25 c A A2 L A1 -C0.05 C Symbols A A1 A2 b c D e E E1 L θ REF: MIN ----0.05 0.80 0.19 0.09 6.40 4.30 0.45 0o Dimensions (mm) NOM --------1.00 --------6.50 0.65 BSC 6.4 BSC 4.40 0.60 ----- SEATING PLANE MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 0.75 8o JEDEC.95, MO-153 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 11