X68C64 68XX Microcontroller Family Compatible X68C64 64K 8192 x 8 Bit E2 Micro-Peripheral FEATURES DESCRIPTION • The X68C64 is an 8K x 8 E2PROM fabricated with advanced CMOS Textured Poly Floating Gate Technology. The X68C64 features a Multiplexed Address and Data bus allowing a direct interface to a variety of popular single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface circuitry. • • • • • • • CONCURRENT READ WRITE™ —Dual Plane Architecture —Isolates Read/Write Functions Between Planes —Allows Continuous Execution of Code From One Plane While Writing in the Other Plane Multiplexed Address/Data Bus —Direct Interface to Popular 8-bit Microcontrollers, e.g., Motorola M6801/03, M68HC11 Family High Performance CMOS —Fast Access Time, 120ns —Low Power —60mA Maximum Active —500µA Maximum Standby Software Data Protection Block Protect Register —Individually Set Write Lock Out in 1K Blocks Toggle Bit Polling —Early End of Write Detection Page Mode Write —Allows up to 32 Bytes to be Written in One Write Cycle High Reliability —Endurance: 100,000 Write Cycles —Data Retention: 100 Years The X68C64 is internally configured as two independent 4K x 8 memory arrays. This feature provides the ability to perform nonvolatile memory updates in one array and continue operation out of code stored in the other array; effectively eliminating the need for an auxiliary memory device for code storage. To write to the X68C64, a three-byte command sequence must precede the byte(s) being written. The X68C64 also provides a second generation software data protection scheme called Block Protect. Block Protect can provide write lockout of the entire device or selected 1K blocks. There are eight 1K x 8 blocks that can be write protected individually in any combination required by the user. Block Protect, in addition to Write Control input, allows the different segments of the memory to have varying degrees of alterability in normal system operation. FUNCTIONAL DIAGRAM WC CE A12 R/W E SEL A8–A11 AS CONTROL LOGIC L A T C H E S X D E C O D E SOFTWARE DATA PROTECT A12 1K BYTES 1K BYTES 1K BYTES 1K BYTES A12 M U X 1K BYTES 1K BYTES 1K BYTES 1K BYTES Y DECODE I/O & ADDRESS LATCHES AND BUFFERS A/D0–A/D7 3868 FHD F02 CONCURRENT READ WRITE™ is a trademark of Xicor, Inc. © Xicor, Inc. 1991, 1995, 1996 Patents Pending 3868-2.6 9/16/96 T0/C0/D2 SH 1 Characteristics subject to change without notice X68C64 PIN DESCRIPTIONS PIN CONFIGURATION Address/Data (A/D0–A/D7) DIP/SOIC Multiplexed low-order addresses and data. The addresses flow into the device while AS is HIGH. After AS transitions from a HIGH to LOW the addresses are latched. Once the addresses are latched these pins input data or output data depending on E, R/W, and CE. NC 1 24 A12 2 23 VCC R/W NC 3 22 AS NC 4 21 A8 Addresses (A8–A12) WC 5 20 A9 High order addresses flow into the device when AS is HIGH and are latched when AS goes LOW. SEL 6 19 A11 Chip Enable (CE) The Chip Enable input must be HIGH to enable all read/ write operations. When CE is LOW and AS is LOW, the X68C64 is placed in the low power standby mode. X68C64 A/D0 7 18 E A/D1 8 17 A10 A/D2 9 16 CE A/D3 10 15 A/D7 A/D4 11 14 A/D6 VSS 12 13 A/D5 Enable (E) 3868 FHD F01.1 When used with a MC6801 or MC6803, the E input is tied directly to the E output of the microcontroller. PIN NAMES Read/Write (R/W) When used with a MC6801 or MC6803, the R/W input is tied directly to the R/W output of the microcontroller. Symbol AS A/D0–A/D7 A8–A12 E R/W CE WC SEL VSS VCC NC Address Strobe (AS) Addresses flow through the latches to address decoders when AS is HIGH and are latched when AS transitions from a HIGH to LOW. Device Select (SEL) Must be connected to VSS. Write Control (WC) The Write Control allows external circuitry to abort a page load cycle once it has been initiated. This input is useful in applications in which a power failure or processor RESET could interrupt a page load cycle. In this case, the microcontroller might drive all signals HIGH, causing bad data to be latched into the E2PROM. If the Write Control input is driven HIGH (before tTBLC Max) after Read/Write (R/W) goes HIGH, the write cycle will be aborted. Description Address Strobe Address Inputs/Data I/O Address Inputs Enable Input Read/Write Input Chip Enable Write Control Device Select—Connect to VSS Ground Supply Voltage No Connect 3868 PGM T01.1 When WC is LOW (tied to VSS) the X68C64 will be enabled to perform write operations. When WC is HIGH normal read operations may be performed, but all attempts to write to the device will be disabled. 2 X68C64 PRINCIPLES OF OPERATION DEVICE OPERATION The X68C64 is a highly integrated peripheral device for a wide variety of single-chip microcontrollers. The X68C64 provides 8K bytes of E2PROM which can be used either for Program Storage, Data Storage, or a combination of both in systems based upon Von Neumann (68XX) architectures. The X68C64 incorporates the interface circuitry normally needed to decode the control signals and demultiplex the Address/Data bus to provide a “Seamless” interface. Motorola 68XX operation requires the microcontroller’s AS, E, and R/W outputs tied to the X68C64 AS, E, and R/W inputs respectively. The falling edge of AS will latch the addresses for both a read and write operation. The state of R/W output determines the operation to be performed, with the E signal acting as a data strobe. If R/W is HIGH and CE HIGH (read operation), data will be output on A/D0–A/D7 after E transitions HIGH. If R/W is LOW and CE is HIGH (write operation), data presented at A/D0–A/D7 will be strobed into the X68C64 on the HIGH to LOW transition of E. The interface inputs on the X68C64 are configured such that it is possible to directly connect them to the proper interface signals of the appropriate single-chip microcontroller. Typical Application The X68C64 is internally organized as two independent planes of 4K bytes of memory with the A12 input selecting which of the two planes of memory are to be accessed. While the processor is executing code out of one plane, write operations can take place in the other plane, allowing the processor to continue execution of code out of the X68C64 during a byte or page write to the device. 30 The X68C64 also features an advanced implementation of the Software Data Protection scheme, called Block Protect, which allows the device to be broken into 8 independent sections of 1K bytes. Each of these sections can be independently enabled for write operations; thereby allowing certain sections of the device to be secured so that updates can only occur in a controlled environment (e.g. in an automotive application, only at an authorized service center). The desired set-up configuration is stored in a nonvolatile register, ensuring the configuration data will be maintained after the device is powered down. 8 MHz OSC. 29 8 XTAL EXTAL VCC VCC 25 24 The X68C64 also features a Write Control input (WC), which serves as an external control over the completion of a previously initiated page load cycle. MODA MODB PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 PB4 PB7 26 AS 27 E 28 R/W 68HC11A8 The X68C64 also features the industry standard E2PROM characteristics such a byte or page mode write and Toggle Bit Polling. 31 32 33 34 35 36 37 38 16 15 14 13 12 9 7 8 9 10 11 13 14 15 21 20 17 19 2 16 5 22 18 23 6 24 A/D0 VCC A/D1 A/D2 A/D3 A/D4 A/D5 A/D6 A/D7 A8 A9 A10 A11 A12 CE WC AS E R/W SEL VSS X68C64 12 3868 ILL F03.2 3 X68C64 MODE SELECTION CE E R/W Mode VSS LOW HIGH HIGH X X HIGH X X HIGH LOW Standby Standby Read Write I/O Power High Z High Z DOUT DIN Standby (CMOS) Standby (TTL) Active Active 3868 PGM T02.1 PAGE WRITE OPERATION Regardless of the microcontroller employed, the X68C64 supports page mode write operations. This allows the microcontroller to write from one to thirty-two bytes of data to the X68C64. Each individual write within a page write operation must conform to the byte write timing requirements. The rising edge of E starts a timer delaying the internal programming cycle 100µs. Therefore, each successive write operation must begin within 100µs of the last byte written. The following waveforms illustrate the sequence and timing requirements. Page Write Timing Sequence for E Controlled Operation OPERATION BYTE 1 BYTE 0 BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR NEXT WRITE OPERATION CE AS A/D0–A/D7 A8–A12 AIN AIN DIN A12=n DIN A12=n AIN AIN DIN A12=n DIN A12=n AIN AIN DIN ADDR A12=x AIN Next Address E R/W tBLC tWC 3868 FHD F07 Notes: (1) For each successive write within a page write cycle A5–A12 must be the same. (2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page write operation. Two responses are possible. a. Reading from the same plane being written (A12 of Read = A12 of Write) is effectively a Toggle Bit Polling operation. b. Reading from the opposite plane being written (A12 of Read ≠ A12 of Write) true data will be returned, facilitating the use of a single memory component as both program and data storage. 4 X68C64 Toggle Bit Polling cycle is complete, the toggling will cease and the device will be accessible for additional read or write operations. Due to the dual plane architecture, reads for polling must occur in the plane that is being written; that is, the state of A12 during a write must match the state of A12 during Toggle Bit Polling. Because the X68C64 typical nonvolatile write cycle time is less than the specified 5ms, Toggle Bit Polling has been provided to determine the early completion of write. During the internal programming cycle, I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal Toggle Bit Polling E Control OPERATION LAST BYTE WRITTEN I/O6=X I/O6=X I/O6=X I/O6=X AIN AIN AIN AIN X68C64 READY FOR NEXT OPERATION CE AS A/D0–A/D7 A8–A12 AIN DIN A12=n DOUT A12=n DOUT A12=n DOUT A12=n AIN DOUT ADDR A12=n E R/W 3868 FHD F08 SYMBOL TABLE WAVEFORM 5 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X68C64 DATA PROTECTION Setting write lockout is accomplished by writing a fivebyte command sequence, opening access to the Block Protect Register (BPR). After the fifth byte is written, the user writes to the BPR, selecting which blocks to protect or unprotect. All write operations, both the command sequence and writing the data to the BPR, must conform to the page write timing requirements. The X68C64 provides two levels of data protection through software control. There is a global software data protection feature similar to the industry standard for E2PROMs and a new Block Protect write lockout protection providing a secondary level of data security. Writing with SDP WRITE AA TO X555 WRITE 55 TO XAAA Block Protect Register Format MSB PERFORM BYTE OR PAGE WRITE OPERATIONS 7 LSB 6 5 4 3 2 1 0 BLOCK ADDRESS 0000–03FF 0400–07FF 0800–0BFF 0C00–0FFF 1000–13FF 1400–17FF 1800–1BFF 1C00–1FFF WAIT tWC WRITE A0 TO X555 EXIT ROUTINE 1 = Protect, 0 = Unprotect Block Specified 3868 FHD F11 X = A12: Setting BPR Command Sequence A12 = 1 IF DATA TO BE WRITTEN IS WITHIN ADDRESS 1000 TO 1FFF. A12 = 0 IF DATA TO BE WRITTEN IS WITHIN ADDRESS 0000 TO 0FFF. 3868 FHD F09 WRITE AA TO X555 WRITE C0 TO XAAA Software Data Protection Software Data Protection (SDP) is employed to protect the entire array against inadvertent writes. To write to the X68C64, a three-byte command sequence must precede the byte(s) being written. WRITE 55 TO XAAA All write operations, both the command sequence and any data write operations, must conform to the page write timing requirements. WRITE BPR MASK VALUE TO ANY ADDRESS WRITE A0 TO X555 WAIT tWC Block Protect Write Lockout The X68C64 provides a secondary level of data security referred to as Block Protect write lockout. This is accessed through an extension of the SDP command sequence. Block Protect allows the user to lockout writes to any 1K x 8 blocks of memory. Unlike SDP which prevents inadvertent writes, but still allows easy system access to writing the memory, Block Protect will lockout all attempts unless it is specifically disabled by the host. This could be used to set a higher level of protection in a system where a portion of the memory is used for Program Storage and another portion is used as Data Storage. WRITE AA TO X555 EXIT ROUTINE X = A12: A12 = 1 IF PROGRAM BEING EXECUTED IS WITHIN 0000 TO 0FFF. A12 = 0 IF PROGRAM BEING EXECUTED RESIDES WITHIN 1000 TO 1FFF. 3868 FHD F12 6 X68C64 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS .................................. –1V to +7V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial Industrial Military 0°C –40°C –55°C +70°C +85°C +125°C X68C64 5V ±10% 3868 PGM T04.1 3868 PGM T03.1 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions CE = VIL, All I/O’s = Open, Other Inputs = VCC, AS = VIH CE = VSS, All I/O’s = Open,Other Inputs = VCC – 0.3V, AS = VSS CE = VIH, All I/O’s = Open, Other Inputs = VIH, AS = VIL VIN = VSS to VCC VOUT = VSS to VCC, E = VIL ICC VCC Current (Active) 60 mA ISB1(CMOS) VCC Current (Standby) 500 µA ISB2(TTL) VCC Current (Standby) 6 mA ILI ILO VlL(1) VIH(1) VOL VOH Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage 10 10 0.8 VCC + 0.5 0.4 µA µA V V V V –1 2 2.4 IOL = 2.1mA IOH = –400µA 3868 PGM T05.1 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol CI/O(2) CIN(2) Test Max. Units Conditions Input/Output Capacitance Input Capacitance 10 6 pF pF VI/O = 0V VIN = 0V 3868 PGM T06 POWER-UP TIMING Symbol Parameter Max. Units tPUR(2) tPUW(2) Power-Up to Read Power-Up to Write 1 5 ms ms 3868 PGM T07 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 7 X68C64 A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels TEST CIRCUIT 0V to 3V 5V 10ns 1.92KΩ 1.5V OUTPUT 3868 PGM T08.1 1.37KΩ 100pF 3868 FHD F04.2 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) E Controlled Read Cycle Symbol Parameter Min. PWASH tASL tAHL tACC tDHR tCSL PWEH tES tEH tRWS tHZ(3) tLZ(3) Address Strobe Pulse Width Address Setup Time Address Hold Time Data Access Time Data Hold Time CE Setup Time E Pulse Width Enable Setup Time E Hold Time R/W Setup Time E LOW to High Z Output E HIGH to Low Z Output 80 20 30 Max. 120 0 7 150 30 20 20 50 0 CE PWASH tCSL tEH tEH tES AS tASL tAHL AIN DOUT tACC A8–A12 tDHR A8–A12 tHZ R/W tRWS tEH E PWEH 3868 FHD F05.1 Note: ns ns ns ns ns ns ns ns ns ns ns ns 3868 PGM T09.1 E Controlled Read Cycle A/D0–A/D7 Units (3) This parameter is periodically sampled and not 100% tested. 8 X68C64 E Controlled Write Cycle Symbol Parameter Min. PWASH tASL tAHL tDSW tDHW tCSL PWEH tWC tES tRWS tEH tBLC Address Strobe Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE Setup Time E Pulse Width Write Cycle Time Enable Setup Time R/W Setup Time E Hold Time Byte Load Time (Page Write) 80 20 30 50 30 7 120 Max. 5 30 20 20 0.5 100 Units ns ns ns ns ns ns ns ms ns ns ns µs 3868 PGM T10 E Controlled Write Cycle CE PWASH tCSL tEH tEH tES AS tASL A/D0–A/D7 tAHL AIN DIN tDSW A8–A12 tDHW A8–A12 tEH R/W tRWS E PWEH 3868 FHD F06.1 3868 FHD F06 Note: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 9 X68C64 PACKAGING INFORMATION 24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.265 (32.13) 1.230 (31.24) 0.557 (14.15) 0.530 (13.46) PIN 1 INDEX PIN 1 0.080 (2.03) 0.065 (1.65) 1.100 (27.94) REF. 0.162 (4.11) 0.140 (3.56) SEATING PLANE 0.030 (0.76) 0.015 (0.38) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.065 (1.65) 0.040 (1.02) 0.022 (0.56) 0.014 (0.36) 0.625 (15.87) 0.600 (15.24) 0° 15° TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F03 10 X68C64 PACKAGING INFORMATION 24-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) PIN 1 INDEX PIN 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7° 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.050" TYPICAL 0.010 (0.25) X 45° 0.020 (0.50) 0.050" TYPICAL 0° – 8° 0.009 (0.22) 0.013 (0.33) 0.420" 0.015 (0.40) 0.050 (1.27) FOOTPRINT 0.030" TYPICAL 24 PLACES NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F24 11 X68C64 ORDERING INFORMATION X68C64 X X X VCC Limits Blank = 5V ±10% Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +128°C Package P = 24-Lead Plastic DIP S = 24-Lead Plastic SOIC LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 12