DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 1.8V to 5.5V, 80µA, 14- and 16-Bit, Low-Power, Single-Channel, DIGITAL-TO-ANALOG CONVERTERS in SC70 Package FEATURES DESCRIPTION 1 • Relative Accuracy: – 1 LSB INL (DAC8311: 14-bit) – 4 LSB INL (DAC8411: 16-bit) • microPower Operation: 80µA at 1.8V • Power-Down: 0.5µA at 5V, 0.1µA at 1.8V • Wide Power Supply: +1.8V to +5.5V • Power-On Reset to Zero Scale • Straight Binary Data Format • Low Power Serial Interface with Schmitt-Triggered Inputs: Up to 50MHz • On-Chip Output Buffer Amplifier, Rail-to-Rail Operation • SYNC Interrupt Facility • Extended Temperature Range –40°C to +125°C • Pin-Compatible Family in a Tiny, 6-Pin SC70 Package 234 APPLICATIONS • • • • Portable, Battery-Powered instruments Process Control Digital Gain and Offset Adjustment Programmable Voltage and Current Sources RELATED DEVICES Pin and Function Compatible 16-BIT 14-BIT 12-BIT 10-BIT 8-BIT DAC8411 DAC8311 DAC7311 DAC6311 DAC5311 The DAC8311 (14-bit) and DAC8411 (16-bit) are low-power, single-channel, voltage output digital-to-analog converters (DAC). They provide excellent linearity and minimize undesired code-to-code transient voltages while offering an easy upgrade path within a pin-compatible family. All devices use a versatile, 3-wire serial interface that operates at clock rates of up to 50MHz and is compatible with standard SPI™, QSPI™, MICROWIRE™, and digital signal processor (DSP) interfaces. All devices use an external power supply as a reference voltage to set the output range. The devices incorporate a power-on reset (POR) circuit that ensures the DAC output powers up at 0V and remains there until a valid write to the device occurs. The DAC8311 and DAC8411 contain a power-down feature, accessed over the serial interface, that reduces current consumption of the device to 0.1µA at 1.8V in power down mode. The low power consumption of this part in normal operation makes it ideally suited for portable, battery-operated equipment. The power consumption is 0.55mW at 5V, reducing to 2.5µW in power-down mode. These devices are pin-compatible with the DAC5311, DAC6311, and DAC7311, offering an easy upgrade path from 8-, 10-, and 12-bit resolution to 14- and 16-bit. All devices are available in a small, 6-pin, SC70 package. This package offers a flexible, pin-compatible, and functionally-compatible drop-in solution within the family over an extended temperature range of –40°C to +125°C. AVDD GND Power-On Reset REF(+) DAC Register 14-/16-Bit DAC Input Control Logic SYNC SCLK Output Buffer Power-Down Control Logic VOUT Resistor Network DIN 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT MAXIMUM RELATIVE ACCURACY (LSB) MAXIMUM DIFFERENTIAL NONLINEARITY (LSB) PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING DAC8411 ±8 ±2 SC70-6 DCK –40°C to 125°C D84 DAC8311 ±4 ±1 SC70-6 DCK –40°C to 125°C D83 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) PARAMETER VALUE UNIT AVDD to GND –0.3 to +6 V Digital input voltage to GND –0.3 to +AVDD +0.3 V AVOUT to GND –0.3 to +AVDD +0.3 V Operating temperature range –40 to +125 °C Storage temperature range –65 to +150 °C +150 °C Junction temperature (TJ max) Power dissipation (TJ max – TA)/θJA θJA thermal impedance (1) 2 250 °C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 ELECTRICAL CHARACTERISTICS At AVDD = +1.8V to +5.5V, RL = 2kΩ to GND, and CL = 200 pF to GND, unless otherwise noted. DAC8411, DAC8311 PARAMETER TEST CONDITIONS MIN TYP MAX ±4 ±8 ±4 ±12 ±0.5 ±2 UNIT STATIC PERFORMANCE (1) Resolution DAC8411 Relative accuracy 16 3.6V to 5V Measured by the line passing through codes 485 and 64714 1.8V to 3.6V Differential nonlinearity Resolution DAC8311 Relative accuracy Measured by the line passing through two codes (2) Offset error drift LSB Bits ±1 ±4 LSB ±0.125 ±1 LSB ±0.05 ±4 mV µV/°C 3 Zero code error All zeros loaded to the DAC register Full-scale error All ones loaded to DAC register 0.2 Gain error Gain temperature coefficient LSB 14 Measured by the line passing through codes 120 and 16200 Differential nonlinearity Offset error Bits mV 0.04 0.2 % of FSR 0.05 ±0.15 % of FSR AVDD = +5V ±0.5 AVDD = +1.8V ±1.5 ppm of FSR/°C OUTPUT CHARACTERISTICS (3) Output voltage range Output voltage settling time 0 RL = 2kΩ, CL = 200 pF, AVDD = 5V, 1/4 scale to 3/4 scale RL = 2MΩ, CL = 470pF Slew rate Capacitive load stability Code change glitch impulse RL = ∞ RL = 2kΩ 1LSB change around major carry Digital feedthrough Power-on glitch impulse RL = 2kΩ, CL = 200pF, AVDD = 5V Power-up time AVDD V 10 µs 12 µs 0.7 V/µs 470 pF 1000 pF 0.5 nV-s 0.5 nV-s 17 mV 0.5 Ω AVDD = +5V 50 mA AVDD = +3V 20 mA Coming out of power-down mode 50 µs DC output impedance Short-circuit current 6 AC PERFORMANCE SNR THD SFDR TA= +25°C, BW = 20kHz, 16-bit level, AVDD = 5V, fOUT = 1kHz, 1st 19 harmonics removed for SNR calculation SINAD DAC output noise density (4) DAC output noise (5) (1) (2) (3) (4) (5) 88 dB –66 dB 66 dB 66 dB TA= +25°C, at zero-scale input, fOUT = 1kHz, AVDD = 5V 17 nV/√Hz TA= +25°C, at mid-code input, fOUT = 1kHz, AVDD = 5V 110 nV/√Hz TA= +25°C, at mid-code input, 0.1Hz to 10Hz, AVDD = 5V 3 µVpp Linearity calculated using a reduced code range of 485 to 64714 for 16-bit, and 120 to 16200 for 14-bit, output unloaded. Straight line passing through codes 485 and 64714 for 16-bit, and 120 and 16200 for 14-bit, output unloaded. Specified by design and characterization, not production tested. For more details, see Figure 31. For more details, see Figure 32. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 3 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) At AVDD = +1.8V to +5.5V, RL = 2kΩ to GND, and CL = 200 pF to GND, unless otherwise noted. DAC8411, DAC8311 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUTS (6) ±1 µA AVDD = +5V 0.8 V AVDD = +1.8V 0.5 V Input current VINL, input low voltage VINH, input high voltage AVDD = +5V 1.8 AVDD = +1.8V 1.1 Pin capacitance V V 1.5 3 pF 5.5 V AVDD = 3.6V to 5.5V 110 160 AVDD = 2.7V to 3.6V 95 150 AVDD = 1.8V to 2.7V 80 140 AVDD = 3.6V to 5.5V 0.5 3.5 AVDD = 2.7V to 3.6V 0.4 3.0 POWER REQUIREMENTS AVDD 1.8 Normal mode VINH = AVDD and VINL = GND, at mid-scale code (7) IDD All power-down mode Normal mode VINH = AVDD and VINL = GND, at mid-scale code VINH = AVDD and VINL = GND, at mid-scale code Power dissipation All power-down mode VINH = AVDD and VINL = GND, at mid-scale code AVDD = 1.8V to 2.7V 0.1 2.0 AVDD = 3.6V to 5.5V 0.55 0.88 AVDD = 2.7V to 3.6V 0.25 0.54 AVDD = 1.8V to 2.7V 0.14 0.38 AVDD = 3.6V to 5.5V 2.50 19.2 AVDD = 2.7V to 3.6V 1.08 10.8 AVDD = 1.8V to 2.7V 0.72 8.1 µA µA mW µW TEMPERATURE RANGE Specified performance (6) (7) 4 –40 +125 °C Specified by design and characterization, not production tested. For more details, see Figure 12, Figure 53, and Figure 83. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 PIN CONFIGURATION DCK PACKAGE SC70-6 (TOP VIEW) SYNC 1 6 VOUT SCLK 2 5 GND DIN 3 4 AVDD/VREF Table 1. PIN DESCRIPTION PIN NAME DESCRIPTION 1 SYNC Level-triggered control input (active low). This is the frame sychronization signal for the input data. When SYNC goes low, it enables the input shift register and data are transferred in on the falling edges of the following clocks. The DAC is updated following the 24th (DAC8411) or 16th (DAC8311) clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8x11. Refer to the DAC8311 and DAC8411 SYNC Interrupt sections for more details. 2 SCLK Serial Clock Input. Data can be transferred at rates up to 50MHz. 3 DIN 4 AVDD/VREF 5 GND Ground reference point for all circuitry on the part. 6 VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation. Serial Data Input. Data is clocked into the 24-bit (DAC8411) or 16-bit (DAC8311) input shift register on the falling edge of the serial clock input. Power Supply Input, +1.8V to 5.5V. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 5 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com SERIAL WRITE OPERATION: 14-Bit (DAC8311) t9 t1 SCLK 1 16 t8 t3 t4 t2 t7 SYNC t10 t6 t5 DB15 DIN DB15 DB0 TIMING REQUIREMENTS (1) (2) All specifications at –40°C to +125°C, and AVDD = +1.8V to +5.5V, unless otherwise noted. PARAMETER t1 (3) SCLK cycle time t2 SCLK high time t3 SCLK low time t4 SYNC to SCLK rising edge setup time t5 Data setup time t6 Data hold time t7 SCLK falling edge to SYNC rising edge t8 Minimum SYNC high time t9 16th SCLK falling edge to SYNC falling edge t10 SYNC rising edge to 16th SCLK falling edge (for successful SYNC interrupt) (1) (2) (3) 6 TEST CONDITIONS MIN AVDD = 1.8V to 3.6V 50 AVDD = 3.6V to 5.5V 20 AVDD = 1.8V to 3.6V 25 AVDD = 3.6V to 5.5V 10 AVDD = 1.8V to 3.6V 25 AVDD = 3.6V to 5.5V 10 AVDD = 1.8V to 3.6V 0 AVDD = 3.6V to 5.5V 0 AVDD = 1.8V to 3.6V 5 AVDD = 3.6V to 5.5V 5 AVDD = 1.8V to 3.6V 4.5 AVDD = 3.6V to 5.5V 4.5 AVDD = 1.8V to 3.6V 0 AVDD = 3.6V to 5.5V 0 AVDD = 1.8V to 3.6V 50 AVDD = 3.6V to 5.5V 20 AVDD = 1.8V to 3.6V 100 AVDD = 3.6V to 5.5V 100 AVDD = 1.8V to 3.6V 15 AVDD = 3.6V to 5.5V 15 TYP MAX UNIT ns ns ns ns ns ns ns ns ns ns All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2. See 14-Bit Serial Write Operation timing diagram. Maximum SCLK frequency is 50MHz at AVDD = 3.6V to 5.5V and 20MHz at AVDD = 1.8V to 3.6V. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 SERIAL WRITE OPERATION: 16-Bit (DAC8411) t9 t1 SCLK 1 24 t8 t3 t4 t2 t7 SYNC t10 t6 t5 DIN DB23 DB23 DB0 TIMING REQUIREMENTS (1) (2) All specifications at –40°C to +125°C, and AVDD = +1.8V to +5.5V, unless otherwise noted. PARAMETER t1 (3) SCLK cycle time t2 SCLK high time t3 SCLK low time t4 SYNC to SCLK rising edge setup time t5 Data setup time t6 Data hold time t7 SCLK falling edge to SYNC rising edge t8 Minimum SYNC high time t9 24th SCLK falling edge to SYNC falling edge t10 SYNC rising edge to 24th SCLK falling edge (for successful SYNC interrupt) (1) (2) (3) TEST CONDITIONS MIN AVDD = 1.8V to 3.6V 50 AVDD = 3.6V to 5.5V 20 AVDD = 1.8V to 3.6V 25 AVDD = 3.6V to 5.5V 10 AVDD = 1.8V to 3.6V 25 AVDD = 3.6V to 5.5V 10 AVDD = 1.8V to 3.6V 0 AVDD = 3.6V to 5.5V 0 AVDD = 1.8V to 3.6V 5 AVDD = 3.6V to 5.5V 5 AVDD = 1.8V to 3.6V 4.5 AVDD = 3.6V to 5.5V 4.5 AVDD = 1.8V to 3.6V 0 AVDD = 3.6V to 5.5V 0 AVDD = 1.8V to 3.6V 50 AVDD = 3.6V to 5.5V 20 AVDD = 1.8V to 3.6V 100 AVDD = 3.6V to 5.5V 100 AVDD = 1.8V to 3.6V 15 AVDD = 3.6V to 5.5V 15 TYP MAX UNIT ns ns ns ns ns ns ns ns ns ns All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2. See 16-Bit Serial Write Operation timing diagram. Maximum SCLK frequency is 50MHz at AVDD = 3.6V to 5.5V and 20MHz at AVDD = 1.8V to 3.6V. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 7 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: AVDD = +5V At TA = +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted. 6 4 2 0 -2 -4 -6 DAC8311 14-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 2 AVDD = 5V LE (LSB) LE (LSB) DAC8411 16-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) -2 0.2 DLE (LSB) DLE (LSB) 0.5 0 -0.5 8192 16384 24576 32768 40960 49152 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 1. Figure 2. DAC8411 16-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) DAC8311 14-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) 6 4 2 0 -2 -4 -6 2 AVDD = 5V AVDD = 5V 1 0 -1 -2 0.2 DLE (LSB) 1.0 DLE (LSB) 0 -0.1 57344 65536 LE (LSB) LE (LSB) 0 0.5 0 -0.5 0.1 0 -0.1 -0.2 -1.0 0 8192 16384 24576 32768 40960 49152 0 57344 65536 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 3. Figure 4. DAC8411 16-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C) DAC8311 14-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C) 6 4 2 0 -2 -4 -6 2 AVDD = 5V LE (LSB) LE (LSB) 0.1 -0.2 -1.0 AVDD = 5V 1 0 -1 -2 0.2 DLE (LSB) 1.0 DLE (LSB) 0 -1 1.0 0.5 0 -0.5 0.1 0 -0.1 -0.2 -1.0 0 8 AVDD = 5V 1 8192 16384 24576 32768 40960 49152 57344 65536 0 2048 4096 6144 8192 10240 12288 Digital Input Code Digital Input Code Figure 5. Figure 6. Submit Documentation Feedback 14336 16384 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted. ZERO-CODE ERROR vs TEMPERATURE SOURCE CURRENT AT POSITIVE RAIL 0.4 5.5 Analog Output Voltage (V) Zero-Code Error (mV) AVDD = 5V 0.3 0.2 0.1 0 -40 -25 -10 5.0 4.5 4.0 3.5 3.0 AVDD = 5V DAC Loaded with FFFFh 2.5 5 20 35 50 65 80 95 110 125 0 6 Figure 7. Figure 8. OFFSET ERROR vs TEMPERATURE SINK CURRENT AT NEGATIVE RAIL 8 10 8 10 0.6 AVDD = 5V DAC Loaded with 0000h AVDD = 5V Analog Output Voltage (V) 0.4 Offset Error (mV) 4 ISOURCE (mA) 0.6 0.2 0 -0.2 -0.4 -0.6 -40 -25 -10 0.4 0.2 0 5 20 35 50 65 80 95 110 125 0 2 4 6 Temperature (°C) ISINK (mA) Figure 9. Figure 10. FULL-SCALE ERROR vs TEMPERATURE POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 120 0.06 AVDD = 5.5V AVDD = 5V Power-Supply Current (mA) 0.04 Full-Scale Error (mV) 2 Temperature (°C) 0.02 0 -0.02 -0.04 -0.06 -40 -25 -10 100 80 60 5 20 35 50 65 80 95 110 125 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Temperature (°C) Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 9 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted. POWER-SUPPLY CURRENT vs TEMPERATURE POWER-DOWN CURRENT vs TEMPERATURE 140 1.6 AVDD = 5V Quiescent Current (mA) Power-Supply Current (mA) AVDD = 5V 130 120 110 100 -40 -25 -10 5 20 35 50 65 80 95 0.8 0.4 0 -40 -25 -10 110 125 5 20 35 50 65 80 Temperature (°C) Temperature (°C) Figure 13. Figure 14. POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE POWER-SUPPLY CURRENT HISTOGRAM 50 2000 SYNC Input (all other digital inputs = GND) 95 110 125 AVDD = 5.5V 45 40 1500 35 Sweep from 0V to 5.5V Occurrences Power-Supply Current (mA) 1.2 1000 Sweep from 5.5V to 0V 30 25 20 15 500 10 5 VLOGIC (V) -40 136 140 128 132 IDD (mA) Figure 15. Figure 16. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 94 AVDD = 5V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz -50 120 5.0 124 4.5 112 4.0 116 3.5 104 3.0 108 2.5 96 2.0 100 1.5 88 1.0 92 0.5 80 0 84 0 0 AVDD = 5V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz THD 92 SNR (dB) THD (dB) -60 2nd Harmonic -70 90 88 -80 3rd Harmonic 86 -90 84 -100 0 10 1 2 3 4 5 0 1 2 3 fOUT (kHz) fOUT (kHz) Figure 17. Figure 18. Submit Documentation Feedback 4 5 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted. CLOCK FEEDTHROUGH 5V, 2MHz, MIDSCALE POWER SPECTRAL DENSITY 0 AVDD = 5V, fOUT = 1kHz, fS = 225kSPS, Measurement Bandwidth = 20kHz VOUT (500mV/div) 20 Gain (dB) -40 -60 -80 -100 AVDD = 5V Clock Feedthrough Impulse ~0.5nV-s -120 -140 0 5 10 15 Time (500ns/div) 20 Frequency (kHz) Figure 19. Figure 20. GLITCH ENERGY 5V, 16-BIT, 1LSB STEP, RISING EDGE GLITCH ENERGY 5V, 16-BIT, 1LSB STEP, FALLING EDGE Clock Feedthrough ~0.5nV-s AVDD = 5V From Code: 8000h To Code: 7FFFh VOUT (100mV/div) VOUT (100mV/div) AVDD = 5V From Code: 7FFFh To Code: 8000h Clock Feedthrough ~0.5nV-s Glitch Impulse < 0.5nV-s Glitch Impulse < 0.5nV-s Time (5ms/div) Time (5ms/div) GLITCH ENERGY 5V, 14-BIT, 1LSB STEP, RISING EDGE GLITCH ENERGY 5V, 14-BIT, 1LSB STEP, FALLING EDGE Glitch Impulse < 0.5nV-s Clock Feedthrough ~0.5nV-s AVDD = 5V From Code: 2000h To Code: 2001h VOUT (100mV/div) Figure 22. VOUT (100mV/div) Figure 21. AVDD = 5V From Code: 2001h To Code: 2000h Clock Feedthrough ~0.5nV-s Time (5ms/div) Glitch Impulse < 0.5nV-s Time (5ms/div) Figure 23. Figure 24. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 11 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted. FULL-SCALE SETTLING TIME 5V RISING EDGE FULL-SCALE SETTLING TIME 5V FALLING EDGE AVDD = 5V From Code: 0000h To Code: FFFFh AVDD = 5V From Code: FFFFh To Code: 0000h Rising Edge 1V/div Zoomed Rising Edge 100mV/div Falling Edge 1V/div Zoomed Falling Edge 100mV/div Trigger Pulse 5V/div Trigger Pulse 5V/div Time (2ms/div) Time (2ms/div) Figure 25. Figure 26. HALF-SCALE SETTLING TIME 5V RISING EDGE HALF-SCALE SETTLING TIME 5V FALLING EDGE AVDD = 5V From Code: C000h To Code: 4000h Falling Edge 1V/div Rising Edge 1V/div Zoomed Falling Edge 100mV/div Zoomed Rising Edge 100mV/div AVDD = 5V From Code: 4000h To Code: C000h Trigger Pulse 5V/div Trigger Pulse 5V/div Time (2ms/div) POWER-ON RESET TO 0V POWER-ON GLITCH POWER-OFF GLITCH 17mV AVDD = 5V DAC = Zero Scale Load = 200pF || 10kW VOUT (20mV/div) AVDD = 5V DAC = Zero Scale Load = 200pF || 10kW AVDD (2V/div) Figure 28. AVDD (2V/div) VOUT (20mV/div) 12 Time (2ms/div) Figure 27. Time (5ms/div) Time (10ms/div) Figure 29. Figure 30. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +5V (continued) At TA = +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted. DAC OUTPUT NOISE DENSITY vs FREQUENCY DAC OUTPUT NOISE 0.1Hz TO 10Hz BANDWIDTH 300 AVDD = 5V, DAC = Midscale, No Load AVDD = 5V VNOISE (1mV/div) Noise (nV/ÖHz) 250 200 150 Midscale 100 3mVPP Zero Scale Full Scale 50 0 10 100 1k 10k Time (2s/div) 100k Frequency (Hz) Figure 31. Figure 32. POWER-SUPPLY CURRENT vs POWER-SUPPLY VOLTAGE POWER-DOWN CURRENT vs POWER-SUPPLY VOLTAGE 120 0.4 AVDD = 1.8V to 5.5V 110 Quiescent Current (mA) Power-Supply Current (mA) AVDD = 1.8V to 5.5V 100 90 80 70 1.800 2.725 3.650 4.575 5.500 0.3 0.2 0.1 0 1.800 2.725 3.650 AVDD (V) AVDD (V) Figure 33. Figure 34. 4.575 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 5.500 13 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: AVDD = +3.6V At TA = 25°C, and AVDD = +3.6V, unless otherwise noted. POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs TEMPERATURE 100 140 AVDD = 3.6V Power-Supply Current (mA) Power-Supply Current (mA) AVDD = 3.6V 90 80 70 60 50 0 130 120 110 100 90 80 -40 -25 -10 8192 16384 24576 32768 40960 49152 57344 65536 50 65 80 Figure 36. POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE POWER-DOWN CURRENT vs TEMPERATURE 95 110 125 95 110 125 1.2 AVDD = 3.6V Quiescent Current (mA) Power-Supply Current (mA) 35 Figure 35. SYNC Input (all other digital inputs = GND) 900 Sweep from 0V to 3.6V 600 300 0.8 0.4 Sweep from 3.6V to 0V 0 -40 -25 -10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 5 20 35 50 65 80 Temperature (°C) VLOGIC (V) Figure 37. Figure 38. SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 3.7 0.6 AVDD = 3.6V DAC Loaded with 0000h 3.5 Analog Output Voltage (V) Analog Output Voltage (V) 20 Temperature (°C) 1200 3.3 3.1 2.9 2.7 AVDD = 3.6V DAC Loaded with FFFFh 2.5 0 14 5 Digital Input Code 2 4 0.4 0.2 0 6 8 10 0 2 4 6 ISOURCE (mA) ISINK (mA) Figure 39. Figure 40. Submit Documentation Feedback 8 10 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +3.6V (continued) At TA = 25°C, and AVDD = +3.6V, unless otherwise noted. POWER-SUPPLY CURRENT HISTOGRAM 50 45 AVDD = 3.6V 40 Occurrences 35 30 25 20 15 10 5 126 130 118 122 110 114 102 106 94 98 86 90 78 82 70 74 0 IDD (mA) Figure 41. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 15 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: AVDD = +2.7V At TA = 25°C, and AVDD = +2.7V, unless otherwise noted. 6 4 2 0 -2 -4 -6 DAC8311 14-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 2 AVDD = 2.7V LE (LSB) LE (LSB) DAC8411 16-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) -2 0.2 DLE (LSB) DLE (LSB) 0.5 0 -0.5 8192 16384 24576 32768 40960 49152 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 42. Figure 43. DAC8411 16-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) DAC8311 14-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) 6 4 2 0 -2 -4 -6 2 AVDD = 2.7V AVDD = 2.7V 1 0 -1 -2 0.2 DLE (LSB) 1.0 DLE (LSB) 0 -0.1 57344 65536 LE (LSB) LE (LSB) 0 0.5 0 -0.5 0.1 0 -0.1 -0.2 -1.0 0 8192 16384 24576 32768 40960 49152 0 57344 65536 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 44. Figure 45. DAC8411 16-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C) DAC8311 14-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C) 6 4 2 0 -2 -4 -6 2 AVDD = 2.7V LE (LSB) LE (LSB) 0.1 -0.2 -1.0 AVDD = 2.7V 1 0 -1 -2 0.2 DLE (LSB) 1.0 DLE (LSB) 0 -1 1.0 0.5 0 -0.5 0.1 0 -0.1 -0.2 -1.0 0 16 AVDD = 2.7V 1 8192 16384 24576 32768 40960 49152 57344 65536 0 2048 4096 6144 8192 10240 12288 Digital Input Code Digital Input Code Figure 46. Figure 47. Submit Documentation Feedback 14336 16384 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued) At TA = 25°C, and AVDD = +2.7V, unless otherwise noted. ZERO-CODE ERROR vs TEMPERATURE SOURCE CURRENT AT POSITIVE RAIL 0.4 2.8 Analog Output Voltage (V) Zero-Code Error (mV) AVDD = 2.7V 0.3 0.2 0.1 0 -40 -25 -10 2.6 2.4 2.2 AVDD = 2.7V DAC Loaded with FFFFh 2.0 5 20 35 50 65 80 95 110 125 0 6 Figure 48. Figure 49. OFFSET ERROR vs TEMPERATURE SINK CURRENT AT NEGATIVE RAIL 8 10 8 10 0.6 AVDD = 2.7V DAC Loaded with 0000h AVDD = 2.7V Analog Output Voltage (V) 0.4 Offset Error (mV) 4 ISOURCE (mA) 0.6 0.2 0 -0.2 -0.4 -0.6 -40 -25 -10 0.4 0.2 0 5 20 35 50 65 80 95 110 125 0 2 4 6 Temperature (°C) ISINK (mA) Figure 50. Figure 51. FULL-SCALE ERROR vs TEMPERATURE POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 100 0.06 AVDD = 2.7V AVDD = 2.7V Power-Supply Current (mA) 0.04 Full-Scale Error (mV) 2 Temperature (°C) 0.02 0 -0.02 -0.04 -0.06 -40 -25 -10 90 80 70 60 50 5 20 35 50 65 80 95 110 125 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Temperature (°C) Figure 52. Figure 53. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 17 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued) At TA = 25°C, and AVDD = +2.7V, unless otherwise noted. POWER-SUPPLY CURRENT vs TEMPERATURE POWER-DOWN CURRENT vs TEMPERATURE 120 1.0 AVDD = 2.7V 110 Quiescent Current (mA) Power-Supply Current (mA) AVDD = 2.7V 100 90 80 70 -40 -25 -10 5 20 35 50 65 80 95 0.6 0.4 0.2 0 -40 -25 -10 110 125 5 20 35 50 65 80 Temperature (°C) Temperature (°C) Figure 54. Figure 55. POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE POWER-SUPPLY CURRENT HISTOGRAM 50 800 SYNC Input (all other digital inputs = GND) 95 110 125 AVDD = 2.7V 45 40 600 35 Occurrences Power-Supply Current (mA) 0.8 Sweep from 0V to 2.7V 400 Sweep from 2.7V to 0V 30 25 20 15 200 10 5 VLOGIC (V) IDD (mA) Figure 56. Figure 57. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 104 100 96 92 88 80 3.0 88 -20 AVDD = 2.7V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz AVDD = 2.7V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz 86 THD SNR (dB) -40 THD (dB) 2.5 84 2.0 76 1.5 72 1.0 68 0.5 60 0 64 0 0 -60 84 2nd Harmonic 82 -80 3rd Harmonic 80 -100 0 18 1 2 3 4 5 0 1 2 3 fOUT (kHz) fOUT (kHz) Figure 58. Figure 59. Submit Documentation Feedback 4 5 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued) At TA = 25°C, and AVDD = +2.7V, unless otherwise noted. CLOCK FEEDTHROUGH 2.7V, 20MHz, MIDSCALE POWER SPECTRAL DENSITY 0 AVDD = 2.7V, fOUT = 1kHz, fS = 225kSPS, Measurement Bandwidth = 20kHz VOUT (500mV/div) 20 Gain (dB) -40 -60 -80 -100 AVDD = 2.7V Clock Feedthrough Impulse ~0.4nV-s -120 -140 0 5 10 15 Time (5ms/div) 20 Frequency (kHz) Figure 60. Figure 61. GLITCH ENERGY 2.7V, 16-BIT, 1LSB STEP, RISING EDGE GLITCH ENERGY 2.7V, 16-BIT, 1LSB STEP, FALLING EDGE AVDD = 2.7V From Code: 8000h To Code: 7FFFh Glitch Impulse < 0.3nV-s Clock Feedthrough ~0.4nV-s VOUT (100mV/div) VOUT (100mV/div) AVDD = 2.7V From Code: 7FFFh To Code: 8000h Glitch Impulse < 0.3nV-s Clock Feedthrough ~0.4nV-s Time (5ms/div) Time (5ms/div) Figure 62. Figure 63. GLITCH ENERGY 2.7V, 14-BIT, 1LSB STEP, RISING EDGE GLITCH ENERGY 2.7V, 14-BIT, 1LSB STEP, FALLING EDGE AVDD = 2.7V From Code: 2001h To Code: 2000h Glitch Impulse < 0.3nV-s Clock Feedthrough ~0.4nV-s VOUT (100mV/div) VOUT (100mV/div) AVDD = 2.7V From Code: 2000h To Code: 2001h Clock Feedthrough ~0.4nV-s Time (5ms/div) Glitch Impulse < 0.3nV-s Time (5ms/div) Figure 64. Figure 65. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 19 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued) At TA = 25°C, and AVDD = +2.7V, unless otherwise noted. FULL-SCALE SETTLING TIME 2.7V RISING EDGE FULL-SCALE SETTLING TIME 2.7V FALLING EDGE AVDD = 2.7V From Code: 0000h To Code: FFFFh AVDD = 2.7V From Code: FFFFh To Code: 0000h Falling Edge 1V/div Rising Edge 1V/div Zoomed Rising Edge 100mV/div Zoomed Falling Edge 100mV/div Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div Time (2ms/div) Time (2ms/div) Figure 66. Figure 67. HALF-SCALE SETTLING TIME 2.7V RISING EDGE HALF-SCALE SETTLING TIME 2.7V FALLING EDGE AVDD = 2.7V From Code: 4000h To Code: C000h AVDD = 2.7V From Code: C000h To Code: 4000h Falling Edge 1V/div Rising Edge 1V/div Zoomed Rising Edge 100mV/div Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div Time (2ms/div) Time (2ms/div) Figure 69. POWER-ON RESET TO 0V POWER-ON GLITCH POWER-OFF GLITCH 17mV AVDD = 2.7V DAC = Zero Scale Load = 200pF || 10kW VOUT (20mV/div) AVDD = 2.7V DAC = Zero Scale Load = 200pF || 10kW AVDD (1V/div) Figure 68. AVDD (1V/div) VOUT (20mV/div) 20 Zoomed Falling Edge 100mV/div Time (5ms/div) Time (10ms/div) Figure 70. Figure 71. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +1.8V At TA = 25°C, and AVDD = +1.8V, unless otherwise noted. 6 4 2 0 -2 -4 -6 DAC8311 14-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 2 AVDD = 1.8V LE (LSB) LE (LSB) DAC8411 16-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) -2 0.2 DLE (LSB) DLE (LSB) 0.5 0 -0.5 8192 16384 24576 32768 40960 49152 0 -0.1 0 57344 65536 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 72. Figure 73. DAC8411 16-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) DAC8311 14-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) 6 4 2 0 -2 -4 -6 2 AVDD = 1.8V LE (LSB) LE (LSB) 0 AVDD = 1.8V 1 0 -1 -2 0.2 DLE (LSB) 1.0 DLE (LSB) 0.1 -0.2 -1.0 0.5 0 -0.5 0.1 0 -0.1 -0.2 -1.0 0 8192 16384 24576 32768 40960 49152 0 57344 65536 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 74. Figure 75. DAC8411 16-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C) DAC8311 14-BIT LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C) 6 4 2 0 -2 -4 -6 2 AVDD = 1.8V LE (LSB) LE (LSB) 0 -1 1.0 AVDD = 1.8V 1 0 -1 -2 0.2 DLE (LSB) 1.0 DLE (LSB) AVDD = 1.8V 1 0.5 0 -0.5 0.1 0 -0.1 -0.2 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 2048 4096 6144 8192 10240 12288 Digital Input Code Digital Input Code Figure 76. Figure 77. 14336 16384 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 21 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: AVDD = +1.8V (continued) At TA = 25°C, and AVDD = +1.8V, unless otherwise noted. ZERO-CODE ERROR vsTEMPERATURE SOURCE CURRENT AT POSITIVE RAIL 1.2 2.0 AVDD = 1.8V 1.8 Analog Output Voltage (V) Zero-Code Error (mV) 1.0 0.8 0.6 0.4 0.2 1.6 1.4 1.2 1.0 0.8 0 -40 -25 -10 AVDD = 1.8V DAC Loaded with FFFFh 0.6 5 20 35 50 65 80 95 110 125 0 2 Temperature (°C) Figure 78. Figure 79. OFFSET ERROR vs TEMPERATURE SINK CURRENT AT NEGATIVE RAIL 0.6 Analog Output Voltage (V) Offset Error (mV) 8 6 8 AVDD = 1.8V DAC Loaded with 0000h 0.4 0.2 0 -0.2 -0.4 -0.6 -40 -25 -10 0.4 0.2 0 5 20 35 50 65 80 95 110 125 0 2 Temperature (°C) 4 ISINK (mA) Figure 80. Figure 81. FULL-SCALE ERROR vs TEMPERATURE POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 100 0.06 AVDD = 1.8V AVDD = 1.8V Power-Supply Current (mA) 0.04 Full-Scale Error (mV) 6 0.6 AVDD = 1.8V 0.02 0 -0.02 -0.04 -0.06 -40 -25 -10 90 80 70 60 50 5 20 35 50 65 80 95 110 125 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Temperature (°C) Figure 82. 22 4 ISOURCE (mA) Figure 83. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +1.8V (continued) At TA = 25°C, and AVDD = +1.8V, unless otherwise noted. POWER-SUPPLY CURRENT vs TEMPERATURE POWER-DOWN CURRENT vs TEMPERATURE 110 0.8 AVDD = 1.8V 100 Quiescent Current (mA) 90 80 70 60 -40 -25 -10 5 20 35 50 65 80 95 0.2 5 20 35 50 65 80 95 Temperature (°C) Temperature (°C) Figure 84. Figure 85. POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE POWER-SUPPLY CURRENT HISTOGRAM 50 SYNC Input (all other digital inputs = GND) 110 125 AVDD = 1.8V 45 40 150 35 Occurrences Sweep from 0V to 1.8V 100 30 25 20 15 50 10 Sweep from 1.8V to 0V 5 VLOGIC (V) IDD (mA) Figure 86. Figure 87. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 116 120 108 112 100 104 92 96 84 2.0 88 1.5 76 1.0 80 0.5 60 0 68 0 0 72 Power-Supply Current (mA) 0.4 0 -40 -25 -10 110 125 200 86 -20 AVDD = 1.8V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz AVDD = 1.8V, fS = 225kSPS, -1dB FSR Digital Input, Measurement Bandwidth = 20kHz THD 84 SNR (dB) -40 THD (dB) 0.6 64 Power-Supply Current (mA) AVDD = 1.8V -60 -80 82 80 2nd Harmonic 78 -100 3rd Harmonic 76 -120 0 1 2 3 4 5 0 1 2 3 fOUT (kHz) fOUT (kHz) Figure 88. Figure 89. 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 5 23 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: AVDD = +1.8V (continued) At TA = 25°C, and AVDD = +1.8V, unless otherwise noted. CLOCK FEEDTHROUGH 1.8V, 20MHz, MIDSCALE POWER SPECTRAL DENSITY 0 AVDD = 1.8V, fOUT = 1kHz, fS = 225kSPS, Measurement Bandwidth = 20kHz VOUT (500mV/div) 20 Gain (dB) -40 -60 -80 -100 AVDD = 1.8V Clock Feedthrough Impulse ~0.34nV-s -120 -140 0 5 10 15 Time (5ms/div) 20 Frequency (kHz) Figure 90. Figure 91. GLITCH ENERGY 1.8V, 16-BIT, 1LSB STEP, RISING EDGE GLITCH ENERGY 1.8V, 16-BIT, 1LSB STEP, FALLING EDGE AVDD = 1.8V From Code: 8000h To Code: 7FFFh Glitch Impulse < 0.2nV-s Clock Feedthrough ~0.3nV-s VOUT (100mV/div) VOUT (100mV/div) AVDD = 1.8V From Code: 7FFFh To Code: 8000h Clock Feedthrough ~0.3nV-s Time (5ms/div) Time (5ms/div) Figure 92. Figure 93. GLITCH ENERGY 1.8V, 14-BIT, 1LSB STEP, RISING EDGE GLITCH ENERGY 1.8V, 14-BIT, 1LSB STEP, FALLING EDGE AVDD = 1.8V From Code: 2000h To Code: 2001h AVDD = 1.8V From Code: 2001h To Code: 2000h VOUT (100mV/div) VOUT (100mV/div) Glitch Impulse < 0.2nV-s Clock Feedthrough ~0.3nV-s Clock Feedthrough ~0.3nV-s Time (5ms/div) Glitch Impulse < 0.2nV-s Time (5ms/div) Figure 94. 24 Glitch Impulse < 0.2nV-s Figure 95. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 TYPICAL CHARACTERISTICS: AVDD = +1.8V (continued) At TA = 25°C, and AVDD = +1.8V, unless otherwise noted. FULL-SCALE SETTLING TIME 1.8V RISING EDGE FULL-SCALE SETTLING TIME 1.8V FALLING EDGE AVDD = 1.8V From Code: 0000h To Code: FFFFh AVDD = 1.8V From Code: FFFFh To Code: 0000h Falling Edge 1V/div Zoomed Rising Edge 100mV/div Rising Edge 1V/div Zoomed Falling Edge 100mV/div Trigger Pulse 1.8V/div Trigger Pulse 1.8V/div Time (2ms/div) Time (2ms/div) Figure 96. Figure 97. HALF-SCALE SETTLING TIME 1.8V RISING EDGE HALF-SCALE SETTLING TIME 1.8V FALLING EDGE AVDD = 1.8V From Code: 4000h To Code: C000h AVDD = 1.8V From Code: C000h To Code: 4000h Falling Edge 1V/div Rising Edge 1V/div Zoomed Rising Edge 100mV/div Zoomed Falling Edge 100mV/div Trigger Pulse 1.8V/div Trigger Pulse 1.8V/div Time (2ms/div) POWER-ON RESET TO 0V POWER-ON GLITCH POWER-OFF GLITCH 4mV AVDD = 1.8V DAC = Zero Scale Load = 200pF || 10kW VOUT (20mV/div) AVDD = 1.8V DAC = Zero Scale Load = 200pF || 10kW AVDD (1V/div) Figure 99. AVDD (1V/div) VOUT (20mV/div) Time (2ms/div) Figure 98. Time (10ms/div) Time (5ms/div) Figure 100. Figure 101. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 25 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com THEORY OF OPERATION DAC SECTION VREF The DAC8311 and DAC8411 are fabricated using TI's proprietary HPA07 process technology. The architecture consists of a string DAC followed by an output buffer amplifier. Because there is no reference input pin, the power supply (AVDD) acts as the reference. Figure 102 shows a block diagram of the DAC architecture. RDIVIDER VREF 2 R AVDD To Output Amplifier R REF (+) DAC Register VOUT Resistor String Output Amplifier GND Figure 102. DAC8x11 Architecture R The input coding to the DAC8311 and DAC8411 is straight binary, so the ideal output voltage is given by: D V OUT + AVDD 2n Where: n = resolution in bits; either 14 (DAC8311) or 16 (DAC8411). D = decimal equivalent of the binary code that is loaded to the DAC register; it ranges from 0 to 16,383 for the 14-bit DAC8311, or 0 to 65,535 for the 16-bit DAC8411. RESISTOR STRING The resistor string section is shown in Figure 103. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is tested monotonic because it is a string of resistors. 26 R Figure 103. Resistor String OUTPUT AMPLIFIER The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0V to AVDD. It is capable of driving a load of 2kΩ in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the Typical Characteristics section for each device. The slew rate is 0.7V/µs with a half-scale settling time of typically 6µs with the output unloaded. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 SERIAL INTERFACE (for 14-Bit DAC8311) The DAC8311 has a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the 14-bit Serial Write Operation timing diagram for an example of a typical write sequence. At this point, the SYNC line may be kept low or brought high. In either case, it must be brought high for a minimum of 20ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. As previously mentioned, it must be brought high again before the next write sequence. DAC8311 Input Shift Register DAC8311 SYNC Interrupt The input shift register is 16 bits wide, as shown in Table 2. The first two bits (PD0 and PD1) are reserved control bits that set the desired mode of operation (normal mode or any one of three power-down modes) as indicated in Table 4. In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th falling edge. However, bringing SYNC high before the 16th falling edge acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating mode occurs, as shown in Figure 104. The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 16-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 50MHz, making the DAC8311 compatible with high-speed DSPs. On the 16th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed. Table 2. DAC8311 Data Input Register DB15 DB14 PD1 PD0 DB0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK SYNC DIN DB15 DB0 Invalid Write Sequence: SYNC HIGH before 16th Falling Edge DB15 DB0 Valid Write Sequence: Output Updates on 16th Falling Edge Figure 104. DAC8311 SYNC Interrupt Facility Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 27 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com SERIAL INTERFACE (for 16-Bit DAC8411) The DAC8411 has a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the 16-bit Serial Write Operation timing diagram for an example of a typical write sequence. At this point, the SYNC line may be kept low or brought high. In either case, it must be brought high for a minimum of 20ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. As previously mentioned, it must be brought high again before the next write sequence. DAC8411 Input Shift Register The SYNC line may be brought high after the 18th bit is clocked in because the last six bits are don't care. The input shift register is 24 bits wide, as shown in Table 3. The first two bits are reserved control bits (PD0 and PD1) that set the desired mode of operation (normal mode or any one of three power-down modes) as indicated in Table 4. The last six bits are don't care. DAC8411 SYNC Interrupt In a normal write sequence, the SYNC line is kept low for 24 falling edges of SCLK and the DAC is updated on the 18th falling edge, ignoring the last six don't care bits. However, bringing SYNC high before the 18th falling edge acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating mode occurs, as shown in Figure 105. The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 50MHz, making the DAC8411 compatible with high-speed DSPs. On the 18th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed. The last six bits are don't care. Table 3. DAC8411 Data Input Register DB23 PD1 DB7 DB6 DB5 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 18th Falling Edge CLK 18 X DB0 X X X X X 18th/24th Falling Edge 24 18 24 SYNC DIN DB23 DB6 DB5 DB0 DB23 Invalid/Interrupted Write Sequence: Output/Mode Does Not Update on the 18th Falling Edge DB6 DB5 DB0 Valid Write Sequence: Output/Mode Updates on the 18th or 24th Falling Edge Figure 105. DAC8411 SYNC Interrupt Facility 28 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 POWER-ON RESET TO ZERO-SCALE The DAC8x11 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the DAC register is filled with zeros and the output voltage is 0V. The DAC register remains that way until a valid write sequence is made to the DAC. This design is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. power-down mode. There are three different options. The output is connected internally to GND either through a 1kΩ resistor or a 100kΩ resistor, or is left open-circuited (High-Z). See Figure 106 for the output stage. Amplifier Resistor String DAC The occuring power-on glitch impulse is only a few mV (typically, 17mV; see Figure 29, Figure 70, or Figure 100). VOUT Power-down Circuitry Resistor Network POWER-DOWN MODES The DAC8x11 contains four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register. Table 4 shows how the state of the bits corresponds to the mode of operation of the device. Table 4. Modes of Operation for the DAC8x11 OPERATING MODE Figure 106. Output Stage During Power-Down All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 50µs for AVDD = 5V and AVDD = 3V. See the Typical Characteristics section for each device for more information. PD1 PD0 0 0 0 1 Output 1kΩ to GND DAC NOISE PERFORMANCE 1 0 Output 100kΩ to GND 1 1 High-Z Typical noise performance for the DAC8x11 is shown in Figure 31 and Figure 32. Output noise spectral density at the VOUT pin versus frequency is depicted in Figure 31 for full-scale, midscale, and zero-scale input codes. The typical noise density for midscale code is 110nV/√Hz at 1kHz and at 1MHz. Normal Operation Power-Down Modes When both bits are set to 0, the device works normally with a standard power consumption of typically 80µA at 1.8V. However, for the three power-down modes, the typical supply current falls to 0.5µA at 5V, 0.4µA at 3V, and 0.1µA at 1.8V. Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. The advantage of this architecture is that the output impedance of the part is known while the part is in Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 29 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com APPLICATION INFORMATION USING THE REF5050 AS A POWER SUPPLY FOR THE DAC8x11 As a result of the extremely low supply current required by the DAC8x11, an alternative option is to use a REF5050 +5V precision voltage reference to supply the required voltage to the part, as shown in Figure 107. This option is especially useful if the power supply is too noisy or if the system supply voltages are at some value other than 5V. The REF5050 outputs a steady supply voltage for the DAC8x11. If the REF5050 is used, the current needed to supply DAC8x11 is typically 110µA at 5V, with no load on the output of the DAC. When the DAC output is loaded, the REF5050 also needs to supply the current to the load. The total current required (with a 5kΩ load on the DAC output) is: 110µA + (5V/5kΩ) = 1.11mA The load regulation of the REF5050 is typically 0.002%/mA, resulting in an error of 90µV for the 1.11mA current drawn from it. This value corresponds to a 1.1LSB error at 16bit (DAC8411). The DAC8x11 has been designed for single-supply operation but a bipolar output range is also possible using the circuit in Figure 108. The circuit shown gives an output voltage range of ±5V. Rail-to-rail operation at the amplifier output is achievable using an OPA211, OPA340, or OPA703 as the output amplifier. For a full list of available operational amplifiers from TI, see TI web site at www.ti.com The output voltage for any input code can be calculated as follows: VO + ƪ AVDD ǒ R1 ) R 2 ǒ2DnǓ R1 Ǔ * AV DD ǒ Ǔƫ R2 R1 (1) Where: n = resolution in bits; either 14 (DAC8311) or 16 (DAC8411). D = the input code in decimal; either 0 to 16,383 (DAC8311) or 0 to 65,535 (DAC8411). With AVDD = 5V, R1 = R2 = 10kΩ: +5.5V ǒ REF5050 1m F (2) This is an output voltage range of ±5V with 0000h (16-bit level) corresponding to a –5V output and FFFFh (16-bit level) corresponding to a +5V output. 110mA SYNC SCLK Ǔ V O + 10 n D *5V 2 +5V Three-Wire Serial Interface BIPOLAR OPERATION USING THE DAC8x11 VOUT = 0V to 5V R2 10kW +5V DAC8x11 DIN +5.5V R1 10kW OPA211 VOUT Figure 107. REF5050 as Power Supply to DAC8x11 For other power-supply voltages, alternative references such as the REF3030 (3V), REF3033 (3.3V), or REF3220 (2.048V) are recommended. For a full list of available voltage references from TI, see TI web site at www.ti.com. 30 AVDD 10mF ±5V DAC8x11 - 5.5V 0.1mF Three-Wire Serial Interface Figure 108. Bipolar Operation with the DAC8x11 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 MICROPROCESSOR INTERFACING DAC8x11(1) Microwire DAC8x11 to 8051 Interface CS SYNC Figure 109 shows a serial interface between the DAC8x11 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8x11, while RXD drives the serial data line of the part. The SYNC signal is derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data are to be transmitted to the DAC8x11, P3.3 is taken low. The 8051 transmits data only in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 remains low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 8051 outputs the serial data in a format which has the LSB first. The DAC8x11 requires its data with the MSB as the first bit received. Therefore, the 8051 transmit routine must take this requirement into account, and mirror the data as needed. SK SCLK SO DIN 80C51/80L51 (1) DAC8x11 P3.3 SYNC TXD SCLK RXD DIN (1) NOTE: (1) Additional pins omitted for clarity. Figure 110. DAC8x11 to Microwire Interface DAC8x11 to 68HC11 Interface Figure 111 shows a serial interface between the DAC8x11 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8x11, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to what was done for the 8051. DAC8x11(1) 68HC11(1) PC7 SYNC SCK SCLK MOSI DIN NOTE: (1) Additional pins omitted for clarity. Figure 111. DAC8x11 to 68HC11 Interface NOTE: (1) Additional pins omitted for clarity. Figure 109. DAC8x11 to 80C51/80L51 Interfaces DAC8x11 to Microwire Interface Figure 110 shows an interface between the DAC8x11 and any Microwire-compatible device. Serial data are shifted out on the falling edge of the serial clock and are clocked into the DAC8x11 on the rising edge of the SK signal. The 68HC11 should be configured so that its CPOL bit is a '0' and its CPHA bit is a '1'. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to the DAC, the SYNC line is taken low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data are transmitted MSB first. In order to load data to the DAC8x11, PC7 is held low after the first eight bits are transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 31 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8x11 offers single-supply operation; it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good performance from the converter. Because of the single ground pin of the DAC8x11, all return currents, including digital and analog return currents, must flow through the GND pin. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system. 32 The power applied to AVDD should be well-regulated and low-noise. Switching power supplies and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as the internal logic switches state. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. This condition is particularly true for the DAC8x11, as the power supply is also the reference voltage for the DAC. As with the GND connection, AVDD should be connected to a +5V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 1µF to 10µF and 0.1µF bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the +5V supply, removing the high-frequency noise. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 PARAMETER DEFINITIONS With the increased complexity of many different specifications listed in product data sheets, this section summarizes selected specifications related to digital-to-analog converters. STATIC PERFORMANCE Static performance parameters are specifications such as differential nonlinearity (DNL) or integral nonlinearity (INL). These are dc specifications and provide information on the accuracy of the DAC. They are most important in applications where the signal changes slowly and accuracy is required. Resolution Generally, the DAC resolution can be expressed in different forms. Specifications such as IEC 60748-4 recognize the numerical, analog, and relative resolution. The numerical resolution is defined as the number of digits in the chosen numbering system necessary to express the total number of steps of the transfer characteristic, where a step represents both a digital input code and the corresponding discrete analogue output value. The most commonly-used definition of resolution provided in data sheets is the numerical resolution expressed in bits. Least Significant Bit (LSB) The least significant bit (LSB) is defined as the smallest value in a binary coded system. The value of the LSB can be calculated by dividing the full-scale output voltage by 2n, where n is the resolution of the converter. Most Significant Bit (MSB) The most significant bit (MSB) is defined as the largest value in a binary coded system. The value of the MSB can be calculated by dividing the full-scale output voltage by 2. Its value is one-half of full-scale. Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy or integral nonlinearity (INL) is defined as the maximum deviation between the real transfer function and a straight line passing through the endpoints of the ideal DAC transfer function. INL is measured in LSBs. Full-Scale Error Full-scale error is defined as the deviation of the real full-scale output voltage from the ideal output voltage while the DAC register is loaded with the full-scale code (0xFFFF). Ideally, the output should be VDD – 1 LSB. The full-scale error is expressed in percent of full-scale range (%FSR). Offset Error Offset error is defined as the difference between actual output voltage and the ideal output voltage in the linear region of the transfer function. This difference is calculated by using a straight line defined by two codes (for example, for 16-bit resolution, codes 485 and 64714). Since the offset error is defined by a straight line, it can have a negative or positve value. Offset error is measured in mV. Zero-Code Error Zero-code error is defined as the DAC output voltage, when all '0's are loaded into the DAC register. Zero-scale error is a measure of the difference between actual output voltage and ideal output voltage (0V). It is expressed in mV. It is primarily caused by offsets in the output amplifier. Gain Error Gain error is defined as the deviation in the slope of the real DAC transfer characteristic from the ideal transfer function. Gain error is expressed as a percentage of full-scale range (%FSR). Full-Scale Error Drift Full-scale error drift is defined as the change in full-scale error with a change in temperature. Full-scale error drift is expressed in units of %FSR/°C. Offset Error Drift Offset error drift is defined as the change in offset error with a change in temperature. Offset error drift is expressed in µV/°C. Zero-Code Error Drift Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is defined as the maximum deviation of the real LSB step from the ideal 1LSB step. Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. If the DNL is within ±1LSB, the DAC is said to be monotonic. Zero-code error drift is defined as the change in zero-code error with a change in temperature. Zero-code error drift is expressed in µV/°C. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 33 DAC8311 DAC8411 SBAS439 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com Gain Temperature Coefficient Digital Feedthrough The gain temperature coefficient is defined as the change in gain error with changes in temperature. The gain temperature coefficient is expressed in ppm of FSR/°C. Digital feedthrough is defined as impulse seen at the output of the DAC from the digital inputs of the DAC. It is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus; that is, from all '0's to all '1's and vice versa. Power-Supply Rejection Ratio (PSRR) Power-supply rejection ratio (PSRR) is defined as the ratio of change in output voltage to a change in supply voltage for a full-scale output of the DAC. The PSRR of a device indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is measured in decibels (dB). Monotonicity Monotonicity is defined as a slope whose sign does not change. If a DAC is monotonic, the output changes in the same direction or remains at least constant for each step increase (or decrease) in the input code. Channel-to-Channel DC Crosstalk Channel-to-channel dc crosstalk is defined as the dc change in the output level of one DAC channel in response to a change in the output of another DAC channel. It is measured with a full-scale output change on one DAC channel while monitoring another DAC channel remains at midscale. It is expressed in LSB. Channel-to-Channel AC Crosstalk Dynamic performance parameters are specifications such as settling time or slew rate, which are important in applications where the signal rapidly changes and/or high frequency signals are present. AC crosstalk in a multi-channel DAC is defined as the amount of ac interference experienced on the output of a channel at a frequency (f) (and its harmonics), when the output of an adjacent channel changes its value at the rate of frequency (f). It is measured with one channel output oscillating with a sine wave of 1kHz frequency, while monitoring the amplitude of 1kHz harmonics on an adjacent DAC channel output (kept at zero scale). It is expressed in dB. Slew Rate Signal-to-Noise Ratio (SNR) The output slew rate (SR) of an amplifier or other electronic circuit is defined as the maximum rate of change of the output voltage for all possible input signals. Signal-to-noise ratio (SNR) is defined as the ratio of the root mean-squared (RMS) value of the output signal divided by the RMS values of the sum of all other spectral components below one-half the output frequency, not including harmonics or dc. SNR is measured in dB. DYNAMIC PERFORMANCE SR = max DVOUT(t) Dt (3) Where ΔVOUT(t) is the output produced by the amplifier as a function of time t. Output Voltage Settling Time Settling time is the total time (including slew time) for the DAC output to settle within an error band around its final value after a change in input. Settling times are specified to within ±0.003% (or whatever value is specified) of full-scale range (FSR). Code Change/Digital-to-Analog Glitch Energy Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nanovolts-second (nV-s), and is measured when the digital input code is changed by 1LSB at the major carry transition. 34 Total Harmonic Distortion (THD) Total harmonic distortion + noise is defined as the ratio of the RMS values of the harmonics and noise to the value of the fundamental frequency. It is expressed in a percentage of the fundamental frequency amplitude at sampling rate fS. Spurious-Free Dynamic Range (SFDR) Spurious-free dynamic range (SFDR) is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of the difference in amplitude between the fundamental and the largest harmonically or non-harmonically related spur from dc to the full Nyquist bandwidth (half the DAC sampling rate, or fS/2). A spur is any frequency bin on a spectrum analyzer, or from a Fourier transform, of the analog output of the DAC. SFDR is specified in decibels relative to the carrier (dBc). Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 Signal-to-Noise plus Distortion (SINAD) DAC Output Noise SINAD includes all the harmonic and outstanding spurious components in the definition of output noise power in addition to quantizing any internal random noise power. SINAD is expressed in dB at a specified input frequency and sampling rate, fS. DAC output noise is defined as any voltage deviation of DAC output from the desired value (within a particular frequency band). It is measured with a DAC channel kept at midscale while filtering the output voltage within a band of 0.1Hz to 10Hz and measuring its amplitude peaks. It is expressed in terms of peak-to-peak voltage (Vpp). DAC Output Noise Density Output noise density is defined as internally-generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. Full-Scale Range (FSR) Full-scale range (FSR) is the difference between the maximum and minimum analog output values that the DAC is specified to provide; typically, the maximum and minimum values are also specified. For an n-bit DAC, these values are usually given as the values matching with code 0 and 2n – 1. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC8311 DAC8411 35 PACKAGE OPTION ADDENDUM www.ti.com 1-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DAC8311IDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DAC8311IDCKT ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DAC8411IDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DAC8411IDCKT ACTIVE SC70 DCK 6 250 CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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