BB DAC8550IBDGKR

 DAC8550
SLAS476C – MARCH 2006 – REVISED MARCH 2006
16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
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DESCRIPTION
Relative Accuracy: 8 LSB (Max)
Glitch Energy: 0.1 nV-s
Settling Time: 10 µs to ±0.003% FSR
Power Supply: +2.7 V to +5.5 V
16-Bit Monotonic Over Temperature
MicroPower Operation: 200 µA at 5 V
Rail-to-Rail Output Amplifier
Power-On Reset to Midscale
Power-Down Capability
Schmitt-Triggered Digital Inputs
SYNC Interrupt Facility
2's Complement Input and Reset to Midscale
Operating Temperature Range: -40°C to 105°C
Available Packages:
– 3 mm × 5 mm MSOP-8
APPLICATIONS
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Process Control
Data Acquisition Systems
Closed-Loop Servo-Control
PC Peripherals
Portable Instrumentation
Programmable Attenuation
The DAC8550 is a small, low-power, voltage output,
16-bit digital-to-analog converter (DAC). It is
monotonic, provides good linearity, and minimizes
undesired code to code transient voltages. The
DAC8550 uses a versatile 3-wire serial interface that
operates at clock rates of up to 30 MHz and is
compatible
with
standard
SPI™,
QSPI™,
Microwire™, and digital signal processor (DSP)
interfaces.
The DAC8550 requires an external reference voltage
to set its output range. The DAC8550 incorporates a
power-on reset circuit that ensures that the DAC
output powers up at midscale and remain there until a
valid write takes place to the device. The DAC8550
contains a power-down feature, accessed over the
serial interface, that reduces the current consumption
of the device to 200 nA at 5 V.
The low-power consumption of this device in normal
operation makes it ideal for portable battery-operated
equipment. Power consumption is 1 mW at 5 V,
reducing to 1 µW in power-down mode.
The DAC8550 is available in a MSOP-8 package.
Also see the DAC8551 binary coded counterpart of
the DAC8550.
FUNCTIONAL BLOCK DIAGRAM
V DD
V FB
V REF
Ref (+)
V OUT
16−Bit DAC
16
DAC Register
16
SYNC
SCLK
D IN
Shift Register
Resistor
Networ k
PWB Control
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola.
Microwire is a trademark of National Semiconductor.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
DAC8550
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SLAS476C – MARCH 2006 – REVISED MARCH 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
PRODUCT
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
PACKAGE
LEAD
PACKAGE
DESIGNATOR (1)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
MARKING
DAC8550
±12
±1
MSOP-8
DGK
–40°C TO 105°C
D80
DAC8550B
(1)
±8
±1
MSOP-8
DGK
–40°C TO 105°C
TRANSPORT
MEDIA,
QUANTITY
ORDERING
NUMBER
DAC8550IDGKT
Tape and Reel, 250
DAC8550IDGKR
Tape and Reel, 2500
DAC8550IBDGKT
Tape and Reel, 250
DAC8550IBDGKR
Tape and Reel, 2500
D80
For the most current package and ordering information, see the Package Option Addendum at the end of this document or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
UNIT
Supply voltage, VDD to GND
–0.3 V to 6 V
Digital input voltage range, VI to GND
–0.3 V to +VDD + 0.3 V
Output voltage, VOUT to GND
–0.3 V to +VDD + 0.3 V
Operating free-air temperature range, TA
–40°C to 105°C
Storage temperature range, TSTG
–65°C to 150°C
Junction temperature range, TJ(max)
150°C
Power dissipation (DGK package)
(TJmax – TA)/θJA
Thermal impedance, θJA
206°C/W
Thermal impedance, θJC
44°C/W
(1)
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V,– 40°C to 105°C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC8550
±5
±12
LSB
DAC8550B
±3
±8
LSB
±1
LSB
STATIC PERFORMANCE (1)
Resolution
16
Bits
EL
Relative accuracy
Measured by line passing
through codes -32283 and
32063
ED
Differential nonlinearity
16-bit Monotonic
±0.25
EO
Zero-code error
±2
±12
mV
EFS
Full-scale error
Measured by line passing through codes -32283
and 32063.
±0.05
±0.5
% of FSR
EG
Gain error
±0.02
±0.2
% of FSR
Zero-code error drift
±5
µV/°C
Gain temperature coefficient
±1
ppm of
FSR/°C
PSRR
Power supply rejection ratio
OUTPUT
CHARACTERISTICS (2)
VO
Output voltage range
(1)
(2)
2
RL = 2 kΩ, CL = 200 pF
0.75
0
Linearity calculated using a reduced code range of -32283 to 32063; output unloaded.
Specified by design and characterization, not production tested.
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mV/V
VREF
V
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SLAS476C – MARCH 2006 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V,– 40°C to 105°C range (unless otherwise noted)
tsd
PARAMETER
TEST CONDITIONS
Output voltage settling time
To ±0.003% FSR, 1200H to 8D00H, RL = 2 kΩ, 0
pF < CL < 200 pF
MIN
RL = 2 kΩ, CL = 500 pF
SR
Slew rate
Capacitive load stability
zo
RL = ∞
RL = 2 kΩ
TYP
MAX
8
10
µs
1.8
V/µs
470
pF
1000
pF
1 LSB change around major carry
0.1
Digital feedthrough
SCLK toggling, FSYNC high
0.1
DC output impedance
At mid-code input
Short-circuit current
ton
Power-up time
µs
12
Code change glitch impulse
IOS
UNIT
nV-s
Ω
1
VDD = 5 V
50
VDD = 3 V
20
Coming out of power-down mode VDD = 5 V
2.5
Coming out of power-down mode VDD = 3 V
5
mA
µs
AC PERFORMANCE
SNR
Signal-to-noise ratio (1st 19
harmonics removed)
95
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range
87
SINAD
Signal-to-noise and distortion
84
85
BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
dB
REFERENCE INPUT
Vref
Reference voltage
II(ref)
Reference current input range
zI(ref)
Reference input impedance
LOGIC INPUTS
VDD
V
VREF = VDD = 5 V
0
50
75
µA
VREF = VDD = 3.6 V
30
45
µA
125
kΩ
(3)
Input current
VIL
Low-level input voltage
VIH
High-level input voltage
±1
µA
VDD = 5 V
0.8
VDD = 3 V
0.6
VDD = 5 V
2.4
VDD = 3 V
2.1
V
V
Pin capacitance
3
pF
5.5
V
POWER REQUIREMENTS
VDD
2.7
IDD (normal mode)
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
Input code equals mid-scale, reference current
included, no load
VIH = VDD and VIL = GND
200
250
180
240
0.2
2
0.05
2
µA
IDD (all power-down modes)
VDD = 3.6 V to 5.5 V
VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V
µA
POWER EFFICIENCY
IOUT/IDD
ILOAD = 2 mA, VDD = 5 V
89%
TEMPERATURE RANGE
Specified performance
(3)
–40
105
°C
Specified by design and characterization, not production tested.
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PIN CONFIGURATION
MSOP-8
(Top View)
VDD
1
VREF
2
VFB
3
VOUT
4
8
GND
7
DIN
6
SCLK
5
SYNC
DAC8550
PIN DESCRIPTIONS
4
PIN
NAME
1
VDD
Power supply input, 2.7 V to 5.5 V.
DESCRIPTION
2
VREF
Reference voltage input.
3
VFB
Feedback connection for the output amplifier.
4
VOUT
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
5
SYNC
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is
updated following the 24th clock (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts
as an interrupt and the write sequence is ignored by the DAC8550).
6
SCLK
Serial clock input. Data can be transferred at rates up to 30 MHz.
7
DIN
8
GND
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input.
Ground reference point for all circuitry on the part.
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TIMING REQUIREMENTS
(1) (2)
VDD = 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t c (3)
SCLK cycle time
t1
SCLK HIGH time
t2
SCLK LOW time
t su1
SYNC to SCLK rising edge setup time
t su2
Data setup time
th
Data hold time
tf
SCLK falling edge to SYNC rising edge
t3
Minimum SYNC HIGH time
(1)
(2)
(3)
MIN
VDD = 2.7 V to 3.6 V
20
VDD = 3.6 V to 5.5 V
20
VDD = 2.7 V to 3.6 V
13
VDD = 3.6 V to 5.5 V
13
VDD = 2.7 V to 3.6 V
22.5
VDD = 3.6 V to 5.5 V
13
VDD = 2.7 V to 3.6 V
0
VDD = 3.6 V to 5.5 V
0
VDD = 2.7 V to 3.6 V
5
VDD = 3.6 V to 5.5 V
5
VDD = 2.7 V to 3.6 V
4.5
VDD = 3.6 V to 5.5 V
4.5
VDD = 2.7 V to 3.6 V
0
VDD = 3.6 V to 5.5 V
0
VDD = 2.7 V to 3.6 V
50
VDD = 3.6 V to 5.5 V
33
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 3 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Serial Write Operation timing diagram.
Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
SERIAL WRITE OPERATION
tc
SCLK
t3
t su1
t1
t2
tf
SYNC
th
t su2
D IN
DB23
DB0
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TYPICAL CHARACTERISTICS: VDD = 5 V
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
(-40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
(25°C)
6
4
2
0
−2
−4
−6
6
4
2
0
−2
VDD = 5 V, VREF = 4.99 V
LE − (LSB)
LE − (LSB)
At TA = 25°C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
−4
−6
1
DLE − (LSB)
1
DLE − (LSB)
VDD = 5 V, VREF = 4.99 V
0.5
0
−0.5
0.5
0
−0.5
−1
−1
0
8192
16384
24576
32768 40960 49152
57344 65536
0
8192
16384 24576 32768
LE − (LSB)
Figure 1.
Figure 2.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
(105°C)
ZERO-SCALE ERROR
vs
TEMPERATURE
6
4
2
0
−2
10
VDD = 5 V, VREF = 4.99 V
VDD = 5 V, VREF = 4.99 V
5
Error (mV)
−4
−6
1
DLE − (LSB)
40960 49152 57344 65536
Digital Input Code
Digital Input Code
0.5
0
0
−0.5
−5
−1
0
8192
16384 24576
32768
40960 49152 57344 65536
−40
0
Digital Input Code
40
80
120
Temperature − C
Figure 3.
Figure 4.
FULL-SCALE ERROR
vs
TEMPERATURE
IDD HISTOGRAM
0
1000
VDD = 5 V, VREF = 4.99 V
VDD = VREF = 5.5 V,
Reference Current Included
f − Frequency − Hz
Error (mV)
800
−5
600
400
200
−10
0
−40
0
40
80
120
120
160
180
200
220
240
IDD − Supply Current − A
Temperature − C
Figure 5.
6
140
Figure 6.
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260
280
300
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SLAS476C – MARCH 2006 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
SOURCE AND SINK CURRENT CAPABILITY
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
300
6
VDD = 5.5 V
VDD = VREF = 5.5 V
DAC Loaded With FFFFH
I DD − Supply Current − µ A
V OUT − Output Voltage − V
5
4
3
VREF = VDD −10 mV
2
1
250
200
Reference Current Included
150
100
50
DAC Loaded With 0000H
0
0
0
3
5
8
0
10
8192
16384 24576
I(SOURCE/SINK) − mA
Digital Input Code
Figure 7.
Figure 8.
POWER-SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
250
300
VDD = VREF = 5.5 V
I DD − Supply Current − µ A
200
Quiescent Current −µ A
32768 40960 49152 57344 65536
150
Reference Current Included
100
50
280
VREF = VDD
260
Reference Current Include, No Load
240
220
200
180
160
140
120
0
−40
−10
20
50
80
100
2.7
110
3.1
3.4
Temperature − C
3.8
4.1
4.5
4.8
5.2
5.5
VDD − Supply Voltage − V
Figure 9.
Figure 10.
POWER-DOWN CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
1
I DD − Supply Current − µ A
− Supply Current −µ A
0.5
0.3
I
DD
0.8
0
2.7
TA = 25°C, SCL Input (All Other Inputs = GND)
VDD = VREF = 5.5 V
1700
VREF = VDD
1300
900
500
100
3.1
3.4
3.8
4.1
4.5
4.8
5.2
5.5
0
1
2
3
4
5
V(LOGIC) − V
VDD − Supply Voltage − V
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
FULL-SCALE SETTLING TIME: 5-V RISING EDGE
FULL-SCALE SETTLING TIME: 5-V FALLING EDGE
Trigger Pulse
5 V/div
Trigger Pulse
5 V/div
VDD = 5 V,
VREF = 4.096 V,
From Code: 0000
To Code: FFFF
Rising Edge
1 V/div
VDD = 5 V,
VREF = 4.096 V,
From Code: FFFF
To Code: 0000
Falling
Edge
1 V/div
Zoomed Rising Edge
1 mV/div
Zoomed Falling Edge
1 mV/div
Time (2 µs/div)
Time (2 µs/div)
Figure 13.
Figure 14.
HALF-SCALE SETTLING TIME: 5-V RISING EDGE
HALF-SCALE SETTLING TIME: 5-V FALLING EDGE
Trigger Pulse
5 V/div
Trigger Pulse
5 V/div
VDD = 5 V,
VREF = 4.096 V,
From Code: CFFF
To Code: 4000
VDD = 5 V,
VREF = 4.096 V,
From Code: 4000
To Code: CFFF
Rising
Edge
1 V/div
Falling
Edge
1 V/div
Zoomed Rising Edge
1 mV/div
Time (2 µs/div)
Time (2 µs/div)
GLITCH ENERGY: 5-V, 1-LSB STEP, RISING EDGE
GLITCH ENERGY: 5-V, 1-LSB STEP, FALLING EDGE
VDD = 5 V,
VREF = 4.096 V
From Code: 7FFF
To Code: 8000
Glitch: 0.08 nV-s
VOUT(500 V/div)
Figure 16.
VOUT (500 V/div)
Figure 15.
VDD = 5 V,
VREF = 4.096 V
From Code: 8000
To Code: 7FFF
Glitch: 0.16 nV-s
Measured Worst Case
Time 400 ns/div
Time 400 ns/div
Figure 17.
8
Zoomed Falling Edge
1 mV/div
Figure 18.
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TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
GLITCH ENERGY: 5-V, 16-LSB STEP, FALLING EDGE
VDD = 5 V,
VREF = 4.096 V
From Code: 8010
To Code: 8000
Glitch: 0.08 nV-s
VOUT (500 V/div)
VOUT(500 V/div)
GLITCH ENERGY: 5-V, 16-LSB STEP, RISING EDGE
VDD = 5 V,
VREF = 4.096 V
From Code: 8000
To Code: 8010
Glitch: 0.04 nV-s
Time 400 ns/div
Time 400 ns/div
Figure 19.
Figure 20.
GLITCH ENERGY: 5-V, 256-LSB STEP, RISING EDGE
GLITCH ENERGY: 5-V, 256-LSB STEP, FALLING EDGE
Time 400 ns/div
Time 400 ns/div
Figure 21.
Figure 22.
TOTAL HARMONIC DISTORTION
vs
OUTPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs
OUTPUT FREQUENCY
98
VDD = 5 V, VREF = 4.9 V
−50
SNR − Signal-to-Noise Ratio − dB
THD − Total Harmonic Distortion − dB
−40
−1dB FSR Digital Input, Fs = 1 MSPS
Measurement Bandwidth = 20 kHz
−60
−70
THD
2nd Harmonic
−80
3rd Harmonic
−90
−100
VDD = 5 V,
VREF= 4.096 V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
VOUT(5 mV/div)
VOUT(5 mV/div)
VDD = 5 V,
VREF = 4.096 V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
VDD = VREF = 5 V
96
−1 dB FSR Digital Input, Fs = 1 MSPS
Measurement Bandwidth = 20 kHz
94
92
90
88
86
84
0
1
2
3
4
5
0
Output Tone − kHz
Figure 23.
0.5
1
1.5
2
2.5
3
3.5
f − Output Frequency − kHz
4
4.5
5
Figure 24.
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TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
POWER SPECTRAL DENSITY
OUTPUT NOISE DENSITY
350
VDD = 5 V
VREF = 4.096
Code = 7FFF
No Load
−10
V n − Voltage Noise − nV/
Gain − dB
−30
Hz
VDD = 5.0 V, VREF = 4.096 V
fOUT = 1 kHz
fCLK = 1 MSPS
−50
−70
−90
−110
−130
0
5000
10000
15000
20000
300
250
200
150
100
100
Figure 25.
10
1000
10000
f − Frequency − Hz
f − Frequency − Hz
Figure 26.
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TYPICAL CHARACTERISTICS: VDD = 2.7 V
At TA = 25°C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL
INPUT CODE
(-40°C)
6
4
2
0
−2
1
1
0.5
0.5
0
−0.5
−4
−6
0
−0.5
−1
−1
0
8192
49152 57344 65536
0
8192
16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 27.
Figure 28.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
(105°C)
ZERO-SCALE ERROR
vs
TEMPERATURE
6
4
LE − (LSB)
16384 24576 32768 40960
Digital Input Code
10
VDD = 2.7 V, VREF = 2.69 V
VDD = 2.7 V, VREF = 2.69 V
2
0
−2
5
Error (mV)
−4
−6
1
DLE − (LSB)
VDD = 2.7 V, VREF = 2.69 V
LE − (LSB)
VDD = 2.7 V, VREF = 2.69 V
DLE − (LSB)
DLE − (LSB)
LE − (LSB)
6
4
2
0
−2
−4
−6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL
INPUT CODE
(25°C)
0.5
0
0
−0.5
−1
0
8192
16384
−5
−40
24576 32768 40960 49152 57344 65536
0
40
80
120
Digital Input Code
Temperature − C
Figure 29.
Figure 30.
FULL-SCALE ERROR
vs
TEMPERATURE
IDD HISTOGRAM
5
1500
VDD = VREF = 2.7 V
Reference Current Included
VDD = 2.7 V, VREF = 2.69 V
f − Frequency − Hz
1200
Error (mV)
0
−5
900
600
300
−10
−40
0
0
40
80
120
120
140
160
180
200
220
240
260
280
300
IDD − Supply Current − A
Temperature − C
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = 25°C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
SOURCE AND SINK CURRENT CAPABILITY
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
3
180
VDD = 2.7 V
2
1.5
VREF = VDD − 10 mV
1
0.5
140
120
Reference Current Included
100
0
3
80
60
40
20
DAC Loaded With 0000H
0
VDD = VREF = 2.7 V
160
DAC Loaded With FFFFH
I DD − Supply Current − µ A
V OUT − Output Voltage − V
2.5
5
8
0
10
0
8192
16384
I(SOURCE/SINK) − mA
24576 32768
40960
49152
57344 65536
Digital Input Code
Figure 33.
Figure 34.
POWER-SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
250
TA = 25°C, SCL Input (All Other Inputs = GND)
I DD − Supply Current − µ A
VDD = VREF = 2.7 V
Quiescent Current −µ A
200
150
Reference Current Included
100
50
0
−40
−10
20
50
80
110
700
VDD = VREF = 2.7 V
500
300
100
0
0.5
1
1.5
2.5
Temperature − C
Figure 35.
Figure 36.
FULL-SCALE SETTLING TIME: 2.7-V RISING EDGE
FULL-SCALE SETTLING TIME: 2.7-V FALLING EDGE
Trigger Pulse
2.7 V/div
Trigger Pulse
2.7 V/div
VDD = 2.7 V,
VREF = 2.5 V,
From Code: FFFF
To Code: 0000
VDD = 2.7 V,
VREF = 2.5 V,
From Code: 0000
To Code: FFFF
Rising
Edge
0.5 V/div
Zoomed Rising Edge
1 mV/div
Falling
Edge
0.5 V/div
Time (2 µs/div)
Zoomed Falling Edge
1 mV/div
Time (2 µs/div)
Figure 37.
12
2
V(LOGIC) − V
Figure 38.
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TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = 25°C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
HALF-SCALE SETTLING TIME: 2.7-V RISING EDGE
HALF-SCALE SETTLING TIME: 2.7-V FALLING EDGE
Trigger Pulse
2.7 V/div
Trigger Pulse
2.7 V/div
VDD = 2.7 V,
VREF = 2.5 V,
From Code: CFFF
To Code: 4000
VDD = 2.7 V
VREF = 2.5 V
From code; 4000
To code: CFFF
Rising
Edge
0.5 V/div
Falling
Edge
0.5 V/div
Zoomed Rising Edge
1 mV / div
Zoomed Falling Edge
1 mV/div
Time (2 µs/div)
Time − 2 s/div
GLITCH ENERGY: 2.7-V, 1-LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7-V, 1-LSB STEP, FALLING EDGE
VDD = 2.7 V,
VREF = 2.5 V
From Code: 7FFF
To Code: 8000
Glitch: 0.08 nV-s
VOUT(200 V/div)
Figure 40.
VOUT(200 V/div)
Figure 39.
VDD = 2.7 V,
VREF = 2.5 V
From Code: 8000
To Code: 7FFF
Glitch: 0.16 nV-s
Measured Worst Case
Time 400 ns/div
Time 400 ns/div
GLITCH ENERGY: 2.7-V, 16-LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7-V, 16-LSB STEP, FALLING EDGE
VDD = 2.7 V,
VREF = 2.5 V
From Code: 8000
To Code: 8010
Glitch: 0.04 nV-s
VDD = 2.7 V,
VREF = 2.5 V
From Code: 8010
To Code: 8000
Glitch: 0.12 nV-s
V/div)
VOUT (200 uV/div)
Figure 42.
VOUT(200 uV/div)
Figure 41.
Time 400 ns/div
Time 400 ns/div
Figure 43.
Figure 44.
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TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = 25°C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
AVDD = 2.7 V,
Vref = 2.5 V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
GLITCH ENERGY: 2.7-V, 256-LSB STEP, FALLING EDGE
VOUT (5 mV/div)
VOUT(5 mV/div)
GLITCH ENERGY: 2.7-V, 256-LSB STEP, RISING EDGE
Time 400 ns/div
Time 400 ns/div
Figure 45.
14
VDD = 2.7 V,
VREF = 2.5 V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
Figure 46.
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THEORY OF OPERATION
DAC SECTION
R
The architecture consists of a string DAC followed by
an output buffer amplifier. Figure 47 shows the block
diagram of the DAC architecture.
Ω
Ω
R
VFB
62 Ω
To Output
Amplifier
R
GND
Figure 47. DAC8550 Architecture
The input coding to the DAC8550 is 2's complement,
so the ideal output voltage is given by:
V
V
D
V
REF REF
OUT
2
65536
(1)
R
where D = decimal equivalent of the 2's complement
code that is loaded to the DAC register; D ranges
from -32768 to +32767 where D = 0 is centered at
VREF/2.
R
RESISTOR STRING
The resistor string section is shown in Figure 48. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier.
Monotonicity is ensured due to the string resistor
architecture.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail output voltages with a range of 0 V to VDD.
It is capable of driving a load of 2 Ωk in parallel with
1000 pF to GND. The source and sink capabilities of
the output amplifier can be seen in the typical curves.
The slewrate is 1.8 V/µs with a full-scale setting time
of 8 µs with the output unloaded.
The inverting input of the output amplifier is brought
out to the VFB pin. This allows for better accuracy in
critical applications by tying the VFB point and the
amplifier output together directly at the load. Other
signal conditioning circuitry may also be connected
between these points for specific applications.
Figure 48. Resistor String
SERIAL INTERFACE
The DAC8550 has a 3-wire serial interface ( SYNC,
SCLK, and DIN), which is compatible with SPI™,
QSPI™, and Microwire™ interface standards, as well
as most DSP interfaces. See the Serial Write
Operation timing diagram for an example of a typical
write sequence.
The write sequence begins by bringing the SYNC line
LOW. Data from the DIN line is clocked into the 24-bit
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 30 MHz, making
the DAC8550 compatible with high-speed DSPs. On
the 24th falling edge of the serial clock, the last data
bit is clocked in and the programmed function is
excuted (i.e., a change in DAC register contents
and/or a change in the mode of operation).
At this point, the SYNC line may be kept LOW or
brought HIGH. In either case, it must be brought
HIGH for a minimum of 33 ns before the next write
sequence so that a falling edge of SYNC can initiate
the next write sequence. Since the SYNC buffer
draws more current when the SYNC signal is HIGH
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than it does when it is LOW, SYNC should be idled
LOW between write sequences for lowest power
operation of the part. As mentioned above, it must be
brought HIGH again just before the next write
sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide, as shown in
Figure 49. The first six bits are don't care bits. The
next two bits (PD1 andPD0) are control bits that
control which mode of operation the part is in (normal
mode or any one of three power-down modes). For a
more complete description of the various modes see
the Power-Down Modes section. The next 16 bits are
the data bits. These are transferred to the DAC
register on the 24th falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
DAC is updated on the 24th falling edge. However, if
SYNC is brought HIGH before the 24th falling edge, it
acts as an interrupt to the write sequence. The shift
register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register
contents nor a change in the operating mode occurs,
as shown in Figure 50.
POWER-ON RESET
The DAC8550 contains a power-on reset circuit that
controls the output voltage during power-up. On
power-up, the output voltages are set to midscale; it
remains there until a valid write sequence is made to
the DAC. This is useful in applications where it is
important to know the state of the output of the DAC
while it is in the process of powering up.
DB23
X
DB0
X
X
X
X
X
PD1
PD0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 49. DAC8550 Data Input Register Format
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB80
DB23
DB80
Valid Write Sequence: Output Updates
on the 24th Falling Edge
Figure 50. SYNC Interrupt Facility
POWER-DOWN MODES
The DAC8550 supports four seperate modes of
operation. These modes are programmable by setting
two bits (PD1 and PD0) in control register. Table 1
shows how the state of the bits corresponds to the
mode of operation of the device.
Table 1. Modes of Operation for the DAC8550
PD1
(DB17)
PD0
(DB16)
OPERATING MODE
0
0
Normal operation
--
--
Power-down modes
0
1
Output typically 1 kΩ to GND
1
0
Output typically 100 kΩ to GND
1
1
High-Z
at 5 V. However, for the three power-down modes,
the supply current falls to 200 nA at 5 V (50 nA at 3
V). Not only does the supply current fall, but the
output stage is also internally switched from the
output of the amplifier to a resistor network of known
values. The advantage with this is that the output
impedance of the device is known while in
power-down mode. There are three different options.
The output is connected internally to GND through a
1-kΩ resistor, a 100-kΩ resistor, or it is left
open-circuited (High-Z). The output stage is illustrated
in Figure 51.
All analog circuitry is shut down when the
power-down mode is activated. However, the
contents of the DAC register are unaffected when in
power-down. The time to exit power-down is typically
2.5 µs for VDD = 5 V, and 5 µs for VDD = 3 V. See the
Typical Characteristics for more information.
When both bits are set to 0, the device works
normally with a typical current consumption of 200 µA
16
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DAC8550 to Microwire Interface
VFB
VOUT
Amplifier
Resistor
String DAC
Power−Down
Circuitry
Resistor
Network
Figure 53 shows an interface between the DAC8550
and any Microwire compatible device. Serial data is
shifted out on the falling edge of the serial clock and
is clocked into the DAC8550 on the rising edge of the
SK signal.
MicrowireTM
Figure 51. Output Stage During Power-Down
DAC8550(1)
CS
SYNC
SK
SCLK
SO
DIN
NOTE: (1) Additional pins omitted for clarity.
MICROPROCESSOR INTERFACING
Figure 53. DAC8550 to Microwire Interface
DAC8550 TO 8051 Interface
See Figure 52 for a serial interface between the
DAC8550 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8550, while RXD drives
the serial data line of the device. The SYNC signal is
derived from a bit-programmable pin on the port of
the 8051. In this case, port line P3.3 is used. When
data is to be transmitted to the DAC8550, P3.3 is
taken LOW. The 8051 transmits data in 8-bit bytes;
thus only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
LOW after the first eight bits are transmitted, then a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken HIGH following the
completion of the third write cycle. The 8051 outputs
the serial data in a format which has the LSB first.
The DAC8550 requires its data with the MSB as the
first bit received. The 8051 transmit routine must
therefore take this into account, and mirror the data
as needed.
80C51/80L51(1)
DAC8550 (1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 52. DAC8550 to 80C51/80L51 Interface
DAC8550 to 68HC11 Interface
Figure 54 shows a serial interface between the
DAC8550 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8550, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
68HC11(1)
DAC8550 (1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 54. DAC8550 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is 0 and its CPHA bit is 1. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data is being
transmitted to the DAC, the SYNC line is held LOW
(PC7). Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted
MSB first.) In order to load data to the DAC8550,
PC7 is left LOW after the first eight bits are
transferred, then a second and third serial write
operation is performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
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APPLICATION INFORMATION
V
REF V
D
REF 65536
2
R1 R2 V REF R2
R1
R1
USING THE REF02 AS A POWER SUPPLY
FOR THE DAC8550
V
Due to the extremely low supply current required by
the DAC8550, an alternative option is to use a REF02
+5 V precision voltage reference to supply the
required voltage to the device, as shown in Figure 55.
where D represents the input code in 2's complement
(-32768 to +32767).
+15
O
With VREF = 5 V, R1 = R2 = 10 kΩ.
V 10 D
O
65536
(4)
This is an output voltage range of ±5 V with 8000H
corresponding to a –5 V output and 8FFFH
corresponding to a 5 V output. Similarly, using VREF =
2.5 V a ±2.5 V output voltage range can be achieved.
+5V
REF02
285 mA
LAYOUT
SYNC
Three-Wire
Serial
Interface
VOUT = 0 V to 5 V
SCLK
DAC8550
DIN
Figure 55. REF02 as a Power Supply to the
DAC8550
This is especially useful if the power supply is quite
noisy or if the system supply voltages are at some
value other than 5 V. The REF02 outputs a steady
supply voltage for the DAC8550. If the REF02 is
used, the current it needs to supply to the DAC8550
is 250 µA. This is with no load on the output of the
DAC. When a DAC output is loaded, the REF02 also
needs to supply the current to the load. The total
typical current required (with a 5 kΩ load on the DAC
output) is:
200 A 5 V 1.2 mA
5 k
(2)
The load regulation of the REF02 is typically
0.005%/mA, which results in an error of 299 µV for
the 1.2 mA current drawn from it. This corresponds to
a 8.9 LSB error.
BIPOLAR OPERATION USING THE DAC8550
The DAC8550 has been designed for single-supply
operation, but a bipolar output range is also possible
using the circuit in Figure 56. The circuit shown gives
an output voltage range of ±VREF. Rail-to-rail
operation at the amplifier output is achievable using
an OPA703 as the output amplifier.
The output voltage for any input code can be
calculated as follows:
18
A precision analog component requires careful layout,
adequate bypassing, and clean, well-regulated power
supplies.
The DAC8550 offers single-supply operation and is
used often in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed the more
difficult it is to keep digital noise from appearing at
the output.
Due to the single ground pin of the DAC8550 all
return currents, including digital and analog return
currents for the DAC, must flow through a single
point. Ideally, GND would be connected directly to an
analog ground plane. This plane would be separate
from the ground connection for the digital
components until they were connected at the
power-entry point of the system.
The power applied to VDD should be well regulated
and have low noise. Switching power supplies and
DC/DC converters often has high-frequency glitches
or spikes riding on the output voltage. In addition,
digital components can create similar high-frequency
spikes as their internal logic switches states. This
noise can easily couple into the DAC output voltage
through various paths between the power
connections and analog output.
As with the GND connection, VDD should be
connected to a 5 V power-supply plane or trace that
is separate from the connection for digital logic until
they are connected at the power-entry point. In
addition, a 1 µF to 10 µF capacitor and 0.1 µF bypass
capacitor are strongly recommended. In some
situations, additional bypassing may be required,
such as a 100 µF electrolytic capacitor or even a Pi
filter made up of inductors and capacitors, all
designed to essentially low-pass filter the 5 V supply,
removing the high-frequency noise.
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R2
10 kW
VREF
+5 V
R1
10 kW
OPA703
VFB
VREF
10 mF
DAC8550
5V
VOUT
0.1 mF
±5 V
Three-Wire
Serial Interface
Figure 56. Bipolar Output Range
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Apr-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC8550IBDGKR
ACTIVE
MSOP
DGK
8
2500
TBD
Call TI
Call TI
DAC8550IBDGKT
ACTIVE
MSOP
DGK
8
250
TBD
Call TI
Call TI
DAC8550IDGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DAC8550IDGKT
ACTIVE
MSOP
DGK
8
250
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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