SN65LVDS047 www.ti.com SLLS416B – JUNE 2000 – REVISED DECEMBER 2003 LVDS QUAD DIFFERENTIAL LINE DRIVER FEATURES • • • • • • • • • • The SN65LVDS047 is characterized for operation from -40°C to 85°C. >400 Mbps (200 MHz) Signaling Rates Flow-Through Pinout Simplifies PCB Layout 300 ps Maximum Differential Skew Propagation Delay Times 1.8 ns (Typical) 3.3 V Power Supply Design ±350 mV Differential Signaling High Impedance on LVDS Outputs on Power Down Conforms to TIA/EIA-644 LVDS Standard Industrial Operating Temperature Range (-40°C to 85°C) Available in SOIC and TSSOP Packages D OR PW PACKAGE (Marked as LVDS047) (TOP VIEW) EN DIN1 DIN2 VCC GND DIN3 DIN4 EN 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 DOUT1– DOUT1+ DOUT2+ DOUT2– DOUT3– DOUT3+ DOUT4+ DOUT4– functional block diagram DESCRIPTION The SN65LVDS047 is a quad differential linedriver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled. The intended application of this device and signaling technique is for point-to-point and multi-drop baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics. DIN1 D1 DIN2 D2 DIN3 D3 DIN4 D4 DOUT1+ DOUT1– DOUT2+ DOUT2– DOUT3+ DOUT3– DOUT4+ DOUT4– EN EN TRUTH TABLE (1) INPUT DIN L H X (1) ENABLES OUTPUTS EN EN H L or OPEN All other conditions DOUT+ DOUT- L H H L Z Z H = high level, L = low level, X = irrelevant, Z = high impedance (off) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2003, Texas Instruments Incorporated SN65LVDS047 www.ti.com SLLS416B – JUNE 2000 – REVISED DECEMBER 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC 50 Ω DIN or EN Input 50 Ω 10 kΩ Output 7V 300 kΩ 7V ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature (see (2) range (unless otherwise noted) UNIT (VCC) Supply voltage -0.3 V to 4 V VI(DIN) Input voltage range -0.3 V to (VCC +0.3 V) (EN, EN ) Enable input voltage -0.3 V to (VCC +0.3 V) VO(DOUT+,DOUT-) Output voltage -0.5 V to (VCC +0.5 V) (DOUT+,DOUT-) Bus-pin--electrostatic discharge, see (DOUT+,(DOUT-) Short circuit duration (3) >10 kV Continuous Storage temperature range -65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE (1) PACKAGE TA≤ 25°C POWER RATING OPERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING D 950 mW 7.6 mW/°C 494 mW PW 774 mW 6.2 mW/°C 402 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS VCC Supply voltage TA Operating free-air temperature 2 Submit Documentation Feedback MIN NOM MAX 3 3.3 3.6 UNIT V -40 25 85 °C SN65LVDS047 www.ti.com SLLS416B – JUNE 2000 – REVISED DECEMBER 2003 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (see PARAMETER (1) and (2) ) (unless otherwise noted) TEST CONDITIONS MIN TYP (3) MAX UNIT 250 310 450 mV 1 35 |mV| 1.17 1.375 1 25 |mV| 1.33 1.6 V VOD Differential output voltage n|VOD| Change in magnitude of VOD for complementary output states VOC(SS) Steady-state, common-mode output voltage nVOC(SS) Change in steady-state common-mode output voltage between logic states VOH Output high voltage VOL Output low voltage VIH Input high voltage VIL Input low voltage IIH Input high current VIN = VCC or 2.5 V -10 IIL Input low current VIN = GND or 0.4 V -10 VIK Input clamp voltage ICL = -18 mA -1.5 -0.8 IOS Output short circuit current, see Enabled, DIN = VCC, DOUT+ = 0 V or DIN = GND, DOUT- = 0 V IOSD Differential output short circuit current, see (4) Enabled, VOD = 0 V IOFF Power-off leakage VO = 0 V or 3.6 V, VCC = 0 V or Open IOZ Output 3-state current EN = 0.8 V and EN = 2 V, VO = 0 V or VCC ICC No load supply current, drivers enabled DIN = VCC or GND ICCL Loaded supply current, drivers enabled RL = 100 Ω all channels, DIN = VCC or GND (all inputs) 20 26 mA ICC(Z) No load supply current, drivers disabled DIN = VCC or GND, EN = GND, EN = VCC 0.5 1.3 mA (1) (2) (3) (4) 1.125 0.90 (4) V RL = 100 Ω, see Figure 1 1.02 V 2 VCC V GND 0.8 V 3 10 µA 1 10 µA -3.1 V -9 mA -9 mA -1 1 µA -1 1 µA 7 mA Current into device pin is defined as positive. Current out of the device is defined as negative. All voltages are referenced to ground, unless otherwise specified. The SN65LVDS047 is a current mode device and only functions within data sheet specifications when a resistive load is applied to the driver outputs, 90 Ω to 110 Ω typical range. All typical values are given for: VCC = 3.3 V, TA = 25°C. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Submit Documentation Feedback 3 SN65LVDS047 www.ti.com SLLS416B – JUNE 2000 – REVISED DECEMBER 2003 SWITCHING CHARACTERISTICS over recommended operating conditions (see (1) (2) , PARAMETER and (3) )(unless otherwise noted) TEST CONDITIONS tPHL Differential propagation delay, high-to-low tPLH Differential propagation delay, low-to-high tSK(p) Differential pulse skew (tPHLD - tPLHD), see tSK(o) Channel-to-channel skew, see (6) tSK(pp) Differential part-to-part skew, see (7) tSK(lim) Differential part-to-part skew, see (8) tr Rise time tf (5) RL = 100 Ω,, CL = 15 pF, see Figure 2 and Figure 3 MIN TYP ( 4) MAX UNIT 1.4 1.8 2.8 ns 1.4 1.8 2.8 ns 50 300 ps 40 300 ps 1 ns 1.2 ns 0.5 1.5 ns Fall time 0.5 1.5 ns tPHZ Disable time high to Z 5.5 8 ns tPLZ Disable time low to Z 5.5 8 ns tPZH Enable time Z to high 8.5 12 ns tPZL Enable time Z to low 8.5 12 f(MAX) Maximum operating frequency, see (1) (2) (3) (4) (5) (6) (7) (8) (9) 4 RL = 100 Ω,, CL = 15 pF, see Figure 4 and Figure 5 (9) 250 ns MHz Generator waveform for all tests unless otherwise: f = 1 MHz, Zo = 50 Ω, tr < 1 ns, and tf < 1 ns. CL includes probe and jig capacitance. All input voltages are for one channel unless otherwise specified. Other inputs are set to GND. All typical values are given for: VCC = 3.3 V, TA = 25°C. tSK(p)|tPHL-tPLH| is the magnitude difference in differential propagation delay time between the positive going edge andthe negative going edge of the same channel. tSK(o) is the differential channel-to-channel skew of any event on the same device. tSK(pp) is the differential part-to-part skew, and is defined as the difference between the minimum and the maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. tSK(lim) part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSK(lim) is defined as|Min - Max| differential propagation delay. f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to55,VOD > 250 mV, all channels switching Submit Documentation Feedback SN65LVDS047 www.ti.com SLLS416B – JUNE 2000 – REVISED DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION DOUT+ VCC RL/2 DIN GND VOC D S1 VOD RL/2 Driver Enable DOUT– Figure 1. Driver VOD and VOC Test Circuit CL DOUT+ DIN Generator RL D 50 Ω DOUT– Driver Enable CL Figure 2. Driver Propagation Delay and Transition Time Test Circuit 3V 1.5 V DIN 1.5 V 0V tPLH tPHL VOH DOUT– 0 V (Differential) 0V DOUT+ V(DIFF) VOL 20% 80% 0V 80% 0V 20% V(DIFF) = DOUT+ – DOUT– tr tf Figure 3. Driver Propagation Delay and Transition Time Waveforms Submit Documentation Feedback 5 SN65LVDS047 www.ti.com SLLS416B – JUNE 2000 – REVISED DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION (continued) CL DOUT+ 50 Ω VCC DIN D GND DOUT– EN Generator 1.2 V 50 Ω CL EN 50 Ω 1/4 65LVDS047 Figure 4. Driver 3-State Delay Test Circuit 3V 1.5 V EN When EN = GND or Open 1.5 V 0V 3V EN When EN = VCC 1.5 V 1.5 V 0V tPHZ tPZH VOH DOUT+ When DIN = VCC DOUT– When DIN = GND 50% DOUT+ When DIN = GND DOUT– When DIN = VCC 50% 50% 1.2 V 1.2 V 50% VOL tPLZ tPZL Figure 5. Driver 3-State Delay Waveform 6 Submit Documentation Feedback SN65LVDS047 www.ti.com SLLS416B – JUNE 2000 – REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS OUTPUT HIGH VOLTAGE vs POWER SUPPLY VOLTAGE OUTPUT LOW VOLTAGE vs POWER SUPPLY VOLTAGE 1.36 1.061 TA = 25°C Load = 100 Ω 1.35 1.056 VOL − Output Low Voltage − V VOH − Output High Voltage − V TA = 25°C Load = 100 Ω 1.34 1.33 1.32 1.31 1.30 1.046 1.041 1.036 3 3.3 VCC − Power Supply Voltage − V 3.6 3 3.3 VCC − Power Supply Voltage − V Figure 6. Figure 7. OUTPUT SHORT CIRCUIT CURRENT vs POWER SUPPLY VOLTAGE DIFFERENTIAL OUTPUT VOLTAGE vs POWER SUPPLY VOLTAGE −3.30 3.6 350 TA = 25°C VI = VCC or GND, VO = 0 V −3.25 VOD − Differential Output Voltage − mV I OS − Output Short Circuit Current − mA 1.051 −3.20 −3.15 −3.10 −3.05 −3.00 TA = 25°C Load = 100 Ω 330 310 290 270 250 3 3.3 VCC − Power Supply Voltage − V 3.6 3 Figure 8. 3.3 VCC − Power Supply Voltage − V 3.6 Figure 9. Submit Documentation Feedback 7 SN65LVDS047 www.ti.com SLLS416B – JUNE 2000 – REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) COMMON-MODE OUTPUT VOLTAGE vs POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT vs FREQUENCY 60 TA = 25°C Load = 100 Ω I CC − power Supply Current − mA VOC − Common-Mode Output Voltage − V 1.20 1.18 1.16 1.14 1.12 1.10 3 3.3 VCC − Power Supply Voltage − V 3.6 50 TA = 25°C Load = 100 Ω 40 All Switching 30 20 10 0 0.01 Figure 10. 8 0.1 10 1 f − Frequency − MHz Figure 11. Submit Documentation Feedback 100 1000 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVDS047D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS047DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS047DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS047DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS047PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS047PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS047PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS047PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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