SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 FEATURES • • • • • • • • • • • • • • (1) (2) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Designed for TIA/EIA-485, TIA/EIA-422, and ISO 8482 Applications Signaling Rates up to 30 Mbps (2) Propagation Delay Times <11 ns Low Standby Power Consumption 1.5 mA Max Output ESD Protection Exceeds 13 kV Driver Positive- and Negative-Current Limiting Power-Up and Power-Down Glitch Free for Line-Insertion Applications Thermal Shutdown Protection Industry Standard Pinout, Compatible With SN75174, MC3487, DS96174, LTC487, and MAX3042 Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the unit bits per second (bps). 20-PIN DW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 1A 1Y NC 1Z 1,2EN 2Z NC 2Y 2A GND 20 19 18 17 16 15 14 13 12 11 VCC 4A 4Y NC 4Z 3,4EN 3Z NC 3Y 3A logic diagram (positive logic) 1A 1,2EN 2A 3A 3,4EN 4A 1 2 4 5 9 11 8 6 12 14 15 19 18 16 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z DESCRIPTION/ORDERING INFORMATION The SN65LBC174A-EP is a quadruple differential line driver with 3-state outputs, designed for TIA/EIA-485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 applications. This device is optimized for balanced multipoint bus transmission at signaling rates up to 30-million bits per second (Mbps). The transmission media may be printed-circuit-board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. Each driver features current limiting and thermal-shutdown circuitry, making it suitable for high-speed multipoint applications in noisy environments. The device is designed using LinBiCMOS™ technology, facilitating low power consumption and robustness. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 The two enable (EN) inputs provide pair-wise driver enabling, or can be externally tied together to provide enable control of all four drivers with one signal. When disabled or powered off, the driver outputs present a high impedance to the bus for reduced system loading. The SN65LBC174A-EP is characterized for operation over the temperature range of –55°C to 125°C. ORDERING INFORMATION (1) TA PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING –55°C to 125°C 20-pin SOIC – DW SN65LBC174AMDWREP 65LBC174EP Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (1) (each driver) (1) OUTPUTS INPUT A ENABLE G Y Z L H L H H H H L OPEN H H L L OPEN L H H OPEN H L OPEN OPEN H L X L Z Z H = high level, L = low level, X = irrelevant, Z = high impedance (off) EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS Y or Z Output A or EN Input VCC VCC 16 V 20 V 100 kΩ 16 V 1 kΩ Input Output 16 V 9V 17 V 16 V 2 Submit Documentation Feedback SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC VI MIN MAX Supply voltage range (2) –0.3 6 V Voltage range at any bus (dc) –10 15 V Voltage range at any bus (transient pulse through 100 Ω, see Figure 8) –30 30 V Input voltage range at any A or EN terminal –0.5 VCC + 0.5 V Electrostatic discharge Y, Z, and GND Human-Body Model (3) Charged-Device Model (4) Tstg 5 All pins 1 Storage temperature range (5) –65 150 kV °C See Dissipation Rating Table Lead temperature 1,6 mm (1/16 in) from case for 10 s (2) (3) (4) (5) 13 All pins Continuous power dissipation (1) UNIT 260 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to GND. Tested in accordance with JEDEC standard 22, Test Method A114-A. Tested in accordance with JEDEC standard 22, Test Method C101. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. DISSIPATION RATING TABLE PACKAGE 20-pin DW (1) JEDEC BOARD MODEL TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C Low K 1483 mW High K 2753 mW TA = 70°C POWER RATING TA = 125°C POWER RATING 11.86 mW/°C 949 mW 297 mW 22 mW/°C 1762 mW 553 mW This is the inverse of the junction-to-ambient thermal resistance when board mounted with no air flow. Submit Documentation Feedback 3 SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 Recommended Operating Conditions VCC Supply voltage Voltage at any bus terminal Y, Z VIH High-level input voltage A, EN VIL Low-level input voltage A, EN TA MIN NOM MAX UNIT 4.75 5 5.25 V –7 12 V 2 VCC V 0 0.8 V Output current –60 60 mA Operating free-air temperature –55 125 °C Electrical Characteristics over recommended operating conditions PARAMETER MIN –1.5 TYP (1) MAX Input clamp voltage II = –18 mA VO Open-circuit output voltage Y or Z, No load 0 VCC No load (open circuit) 3 VCC |VOD(SS)| Steady-state differential output voltage magnitude (2) ∆VOD(SS) Change in steady-state differential output voltage between logic states See Figure 1 –0.1 VOC(SS) Steady-state common-mode output voltage See Figure 3 2 ∆VOC(SS) Change in steady-state common-mode output voltage between logic states See Figure 3 II Input current A, G, G IOS Short-circuit output current IOZ High-impedance-state output current IO(OFF) Output current with power off ICC Supply current (1) (2) 4 TEST CONDITIONS VIK –0.77 V RL = 54 Ω, See Figure 1 0.8 1.6 2.5 With common-mode loading, See Figure 2 0.8 1.6 2.5 VI = 0 V or VCC, No load V V 0.1 V 2.8 V –0.04 0.04 V -–70 70 µA –200 200 mA EN at 0 V –50 50 VCC = 0 V –10 10 VI = 0 V VTEST = –7 V to 12 V, See Figure 7 UNIT VI = VCC 2.4 All drivers enabled 25 All drivers disabled 1.5 µA mA All typical values are at VCC = 5 V and 25°C. The minimum VOD may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the possibility of lower output signal into account in determining the maximum signal transmission distance. Submit Documentation Feedback SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 Switching Characteristics over recommended operating conditions PARAMETER tPLH Propagation delay time, low- to high-level output tPHL Propagation delay time, high- to low-level output tr Differential output voltage rise time tf Differential output voltage fall time tsk(p) Pulse skew |tPLH – tPHL| tsk(o) Output skew (1) TEST CONDITIONS MIN TA=25°C 4.0 TA= -55°C to 125°C 4.0 TA=25°C 4.0 TA= -55°C to 125°C 4.0 RL = 54 Ω, CL = 50 pF, See Figure 4 TA=25°C 3 TA= -55°C to 125°C 3 TA=25°C 3 TA= -55°C to 125°C 3 Propagation delay time, high impedance to high-level output Propagation delay time, high-level output to high impedance tPZL Propagation delay time, high impedance to low-level output (1) (2) 8 7.5 7.5 11 ns 16 ns 11 ns 16 ns 11 ns 24 ns 11 ns 24 ns ns 0.6 tPHZ tPLZ 8 0.6 tsk(pp) Part-to-part skew (2) tPZH TYP MAX UNIT Propagation delay time, low-level output to high impedance 2 ns 3 ns 25 ns 25 ns 30 ns 20 ns See Figure 5 See Figure 6 Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together. Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback 5 SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 PARAMETER MEASUREMENT INFORMATION IOY Y II A IOZ Z VOD 54 Ω VOY GND VI VOZ Figure 1. Test Circuit, VOD Without Common-Mode Loading 375 Ω Y A Input 60 Ω VOD Z VTEST = −7 V to 12 V 375 Ω VTEST VI Figure 2. Test Circuit, VOD With Common-Mode Loading Y 27 Ω A Z Signal Generator(A) 27 Ω CL = 50 pF(B) 50 Ω A. PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω B. Includes probe and jig capacitance Figure 3. VOC Test Circuit 6 Submit Documentation Feedback VOC SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) Y A RL = 54 Ω CL = 50 pF(B) VOD Z Signal Generator(A) 50 Ω 3V 1.5 V Input 0V tPLH tPHL ≈ 1.5 V 90% 0V 10% Output tr ≈ −1.5 V tf A. PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω B. Includes probe and jig capacitance Figure 4. Output Switching Test Circuit and Waveforms Submit Documentation Feedback 7 SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) Y S1 A 3 V or 0 V(C) Output Z CL = 50 pF(B) RL = 110 Ω Input EN Signal Generator(A) 50 Ω 3V 1.5 V Input 0V tPZH 0.5 V VOH 2.3 V 0V Output tPHZ A. PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω B. Includes probe and jig capacitance C. 3 V if testing Y output, 0 V if testing Z output Figure 5. Enable Timing Test Circuit and Waveforms, tPZH and tPHZ 8 Submit Documentation Feedback SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) 5V RL = 110 Ω Y S1 A 0 V or 3 V(C) Output Z CL = 50 pF(B) Input EN Signal Generator(A) 50 Ω 3V 1.5 V Input 0V tPZL tPLZ 5V Output 2.3 V VOL 0.5 V A. PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω B. Includes probe and jig capacitance C. 3 V if testing Y output, 0 V if testing Z output Figure 6. Enable Timing Test Circuit and Waveforms, tPZL and tPLZ Y IO VI Z VTEST Voltage Source VTEST = −7 V to 12 V Slew Rate ≤1.2 V/µs Figure 7. Test Circuit, Short-Circuit Output Current Submit Documentation Feedback 9 SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) Y Z 100 Ω VTEST 0V Pulse Generator 15-µs Duration, 1% Duty Cycle 15 µs 1.5 ms Figure 8. Test Circuit Waveform, Transient Overvoltage Test 10 Submit Documentation Feedback −VTEST SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 2.5 3.5 VOD − Differential Output Voltage − V VOD − Differential Output Voltage − V 4 3 VCC = 5.25 V 2.5 VCC = 5 V 2 1.5 VCC = 4.75 V 1 0.5 20 40 60 80 IO − Output Current − mA VCC = 5 V 1.5 VCC = 4.75 V 1 0.5 0 −60 0 0 VCC = 5.25 V 2 100 −40 −20 0 20 40 60 TA − Free-Air Temperature − °C Figure 9. SUPPLY CURRENT (FOUR CHANNELS) vs SIGNALING RATE 144 I CC − Supply Current (Four Channels) − mA 8.5 Propagation Delay Time − ns 8 7 VCC = 5.25 V VCC = 4.75 V 6.5 6 5.5 5 −40 100 Figure 10. PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 7.5 80 RL = 54 Ω CL = 50 pF (Each Channel) 142 140 138 136 134 132 130 128 −20 0 20 40 60 TA − Free-Air Temperature − °C 80 1 Figure 11. 10 Signaling Rate − Mbps 100 Figure 12. Submit Documentation Feedback 11 SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL OUTPUT VOLTAGE vs SUPPLY VOLTAGE 3 VOD − Differential Output Voltage − V RL = 54 Ω 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VCC − Supply Voltage − V 5.5 6 Figure 13. RL = 54 Ω CL = 50 pF Figure 14. Eye Pattern, Pseudo-Random Data at 30 Mbps 12 Submit Documentation Feedback SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION TMS320F243 DSP (Controller) SN65LBC174A-EP SN65LBC175A-EP TMS320F241 DSP (Embedded Application) SPISIMO SPISIMO IOPA1 (Enable) IOPA1 SPISTE SPISTE SPICLK SPICLK IOPA2 (Enable) IOPA2 IOPA0 (Handshake /Status) IOPA0 SPISOMI SPISOMI Figure 15. Typical Application Circuit, DSP-to-DSP Link Via Serial Peripheral Interface Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LBC174AMDWREP ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/07611-01XE ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN65LBC174A-EP : • Catalog: SN65LBC174A NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LBC174AMDWREP Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.1 2.65 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LBC174AMDWREP SOIC DW 20 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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