AD AD10226AB

a
Dual-Channel, 12-Bit 125 MSPS
IF Sampling A/D Converter
AD10226
FEATURES
Two Independent 12-Bit, 125 MSPS ADCs
Channel-to-Channel Isolation, > 80 dB
AC-Coupled Signal Conditioning Included
Gain Flatness up to Nyquist, < 0.1 dB
Input VSWR 1.1:1 to Nyquist
80 dB Spurious-Free Dynamic Range
Two’s Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
1.5 W Per Channel
Single-Ended or Differential Input
350 MHz Input Bandwidth
PRODUCT DESCRIPTION
The AD10226 offers two complete ADC channels with on-module
signal conditioning for improved dynamic performance. Each wide
dynamic range ADC has a transformer coupled front end
optimized for direct-IF sampling. The AD10226 has on-chip
track-and-hold circuitry and utilizes an innovative architecture to
achieve 12-bit, 125 MSPS performance. The AD10226 uses
innovative high density circuit design to achieve exceptional
performance, while still maintaining excellent isolation and providing for board area savings.
The AD10226 operates with 5.0 V analog supply and 3.3 V digital
supply. Each channel is completely independent, allowing operation with independent ENCODE and analog inputs. The AD10226
is available in a 35 mm square 385-lead BGA package.
APPLICATIONS
Wireless and Wired Broadband Communications
Base Stations and “Zero-IF” or Direct IF Sampling
Subsystems
Wireless Local Loop (WLL)
Local Multipoint Distribution Service (LMDS)
Radar and Satellite Subsystems
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 125 MSPS
2. Input signal conditioning included with full-power bandwidth
to 350 MHz
3. Industry-leading IF sampling performance
FUNCTIONAL BLOCK DIAGRAM
AIN A1 AIN A2
AIN B1 AIN B2
D0A
(LSB)
D0B
(LSB)
D1B
D1A
T1A
D2A
T1B
D3A
50⍀
50⍀
T/H
T/H
D2B
D3B
D4B
D4A
D5A
D5B
AD10226
D6B
D6A
D7A
ADC
D7B
ADC
D8A
D9A
D10A
D11A
(MSB)
DFS_A
D8B
12
12
12
OUTPUT
RESISTORS
TIMING
12
OUTPUT
RESISTORS
REF
REF
TIMING
D9B
D10B
D11B
(MSB)
DFS_B
SFDR_B
SFDR_A
ENCODEA ENCODEA REF_A_OUT
REF_B_OUT ENCODEB ENCODEB
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD10226–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS1 (V
Parameter
Temp
DD =
3.3 V, VCC = 5.0 V; ENCODE = 125 MSPS, unless otherwise noted.)
Test
Level
Min
RESOLUTION
Full
Full
Full
25°C
25°C
Full
Full
IV
IV
IV
I
I
V
V
ANALOG INPUT
Input Voltage Range
Input Impedance
Input VSWR4
Analog Input Bandwidth, High
Analog Input Bandwidth, Low
25°C
25°C
Full
Full
Full
V
V
V
IV
IV
ANALOG REFERENCE
Output Voltage
Load Current
Tempco
25°C
25°C
Full
V
V
V
SWITCHING PERFORMANCE5
Maximum Conversion Rate
Minimum Conversion Rate
Duty Cycle
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Valid Time (tV)6
Output Propagation Delay (tPD)6
Output Rise Time (tR)
Output Fall Time (tF)
Full
Full
Full
25°C
25°C
Full
Full
25°C
25°C
VI
IV
IV
V
V
IV
IV
V
V
DIGITAL INPUTS
ENCODE Input Common-Mode
Differential Input (ENC, ENC)
Logic “1” Voltage
Logic “0” Voltage
Input Resistance
Input Capacitance
Full
Full
Full
Full
Full
25°C
IV
IV
IV
IV
IV
V
Full
Full
IV
IV
Full
Full
Full
Full
VI
IV
VI
VI
POWER SUPPLY7
Power Dissipation8
Power Supply Rejection Ratio
Total I (DVDD) Current
Total I (AVCC) Current
Max
12
DC ACCURACY
Differential Nonlinearity2
Integral Nonlinearity2
No Missing Codes
Gain Error3
Output Offset
Gain Tempco
Offset Tempco
DIGITAL OUTPUTS
Logic “1” Voltage6
Logic “0” Voltage6
Output Coding
Typ
–0.99
–1.3
–9
–12
300
1
± 0.3
± 0.75
Guaranteed
±1
+2
100
–50
1.84
50
1.1:1
350
Bits
+0.99
+1.3
LSB
LSB
+9
+12
% FS
LSB
ppm/°C
ppm/°C
1.25:1
2.5
5
± 80
3.0
50
2.1
0.25
4.5
4.5
3.5
3.3
10
55
6.0
3.75
500
2.0
0.8
–2–
V p-p
Ω
Ratio
MHz
MHz
V
mA
ppm/°C
125
45
Unit
MSPS
MSPS
%
ns
ps rms
ns
ns
ns
ns
V
mV
V
V
kΩ
pF
3
6
3
3.1
3.3
0
Two’s Complement
0.2
V
V
3040
± 0.5
40
540
3300
± 5.0
60
650
mW
mV/V
mA
mA
REV. 0
AD10226
Parameter
Temp
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)9 (Without Harmonics)
fIN = 10.3 MHz
25°C
fIN = 49 MHz
25°C
25°C
fIN = 71 MHz
fIN = 121 MHz
25°C
fIN = 250 MHz
25°C
Signal-to-Noise Ratio (SINAD)10 (With Harmonics)
25°C
fIN = 10.3 MHz
fIN = 49 MHz
25°C
fIN = 71 MHz
25°C
25°C
fIN = 121 MHz
fIN = 250 MHz
25°C
Spurious-Free Dynamic Range11
fIN = 10 MHz
25°C
25°C
fIN = 41 MHz
fIN = 71 MHz
25°C
fIN = 121 MHz
25°C
25°C
fIN = 250 MHz
Two-Tone Intermodulation
Distortion12 (IMD)
fIN = 29.3 MHz; fIN = 30.3 MHz
25°C
25°C
fIN = 150 MHz; fIN = 151 MHz
Channel-to-Channel Isolation13
fIN = 121 MHz
Full
Test
Level
Min
Typ
I
V
I
V
V
66.5
68.5
67
66
64
60
dBFS
dBFS
dBFS
dBFS
dBFS
I
V
I
V
V
65.5
68
66.5
65
62.5
59.5
dBFS
dBFS
dBFS
dBFS
dBFS
I
V
I
V
V
76.5
82
77
72
71
70
dBFS
dBFS
dBFS
dBFS
dBFS
V
V
78
70
dBc
dBc
IV
85
dB
63
62.5
66
Max
Unit
NOTES
1
All ac specifications tested by driving ENCODE and ENCODE differentially, with the analog input applied to A INX1 and A INX2 tied to ground.
2
SFDR enabled (SFDR = 1) for DNL and INL specifications.
3
Gain error measured at 10.3 MHz.
4
Input VSWR, see TPC 14.
5
See Figure 1, Timing Diagram.
6
tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during
test is not to exceed an ac load of 10 pF or a dc current of ± 40 A.
7
Supply voltages should remain stable within ± 5% for normal operation.
8
Power dissipation measures with encode at rated speed.
9
Analog input signal power at –1 dBFS; signal-to-noise (SNR) is the ratio of signal level to total noise (first six harmonics removed). ENCODE = 125 MSPS,
SFDR mode = 1. SNR is reported in dBFS, related back to converter full-scale.
10
Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. ENCODE = 125 MSPS.
SINAD is reported in dBFS, related back to converter full-scale.
11
Analog input signal equals –1 dBFS; SFDR is ratio of converter full-scale to worst spur.
12
Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.
13
Channel-to-channel isolation tested with A channel/50 Ω terminated (AIN A2) grounded and a full-scale signal applied to B channel (A IN B2).
Specifications subject to change without notice.
REV. 0
–3–
AD10226
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . 5 V p-p (18 dBm)
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature (Ambient) . . . . . . . –55°C to +125°C
Storage Temperature (Ambient) . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Test Level
I
100% production tested
II 100% production tested at 25°C and sample tested at specific
temperatures
III Sample tested only
IV Parameter is guaranteed by design and characterization
testing
V Parameter is a typical value only
VI 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions outside of those indicated in the operation sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table I. Output Coding (VREF = 2.5 V) (Two’s Complement)
THERMAL CHARACTERISTICS
Code
AIN (V)
Digital Output
385-Lead BGA Package:
The typical θJA of the module as determined by an IR scan is
26.25°C/W.
+2047
·
·
0
–1
·
·
–2048
+0.875
·
·
0
–0.000427
·
·
–0.875
0111 1111 1111
·
·
0000 0000 0000
1111 1111 1111
·
·
1000 0000 0000
SAMPLE Nⴚ1
SAMPLE N
SAMPLE Nⴙ10
SAMPLE Nⴙ11
AIN
SAMPLE Nⴙ1
SAMPLE Nⴙ9
1/f S
ENCODE
ENCODE
t PD
tV
D11ⴚD0
DATA Nⴚ11
DATA Nⴚ10
Nⴚ9
Nⴚ2
DATA Nⴚ1
DATA N
DATA N ⴙ 1
Figure 1. Timing Diagram
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD10226AB
AD10226/PCB
–25°C to +85°C (Ambient)
25°C
385-Lead BGA (35 mm 35 mm)
Evaluation Board with AD10226AB
B-385
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10226 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD10226
PIN CONFIGURATION
25
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
35mm SQUARE
BOTTOM VIEW
PIN FUNCTION DESCRIPTIONS
Mnemonic
Function
AGNDA
REF_A_OUT
NC
AIN A1
AIN A2
AVCCA
DGNDA
D11A–D0A
ENCODEA
ENCODEA
DVCCA
DGNDB
D11B–D0B
AGNDB
DVCCB
ENCODEB
ENCODEB
REF_B_OUT
AIN B1
AIN B2
AVCCB
DFS
SFDR Mode
A Channel Analog Ground. A and B grounds should be connected as close to the device as possible.
A Channel Internal Voltage Reference
No connection
Analog Input for A side ADC (– input)
Analog Input for A side ADC (+ input)
Analog Positive Supply Voltage (nominally 5.0 V)
A Channel Digital Ground
Digital Outputs for ADC A. D0 (LSB)
Complement of ENCODE
Data conversion initiated on the rising edge of ENCODE input.
Digital Positive Supply Voltage (nominally 3.3 V)
B Channel Digital Ground
Digital Outputs for ADC B. D0 (LSB)
B Channel Analog Ground. A and B grounds should be connected as close to the device as possible.
Digital Positive Supply Voltage (nominally 3.3 V)
Complement of ENCODE
Data conversion initiated on rising edge of ENCODE input.
B Channel Internal Voltage Reference
Analog Input for B side ADC (– input)
Analog Input for B side ADC (+ input)
Analog Positive Supply Voltage (nominally 5.0 V)
Data format select. Low = Two’s Complement, High = Binary.
CMOS control pin that enables (SFDR MODE = 1) a proprietary circuit that may improve the spurious free dynamic
range (SFDR) performance. It is useful in applications where the dynamic range of the system is limited by discrete spurious
frequency content caused by nonlinearities in the ADC transfer function. SFDR Mode = 0 for normal operation.
REV. 0
–5–
AD10226
385-LEAD BGA PINOUT
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Ball Signal
No. Name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
DNC
DNC
AGNDA
AVCCA
REF_A_OUT
AGNDA
DNC
AGNDB
AGNDB
AVCCB
AGNDB
AVCCB
DNC
DNC
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
DNC
DNC
AGNDA
AVCCA
REF_A_OUT
AGNDA
DNC
AGNDB
AGNDB
AVCCB
AGNDB
AVCCB
DNC
DNC
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
DNC
DNC
AGNDA
AVCCA
REF_A_OUT
AGNDA
DNC
AGNDB
AGNDB
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
E1
E2
E3
E4
E22
E23
E24
E25
F1
F2
F3
F4
F22
F23
F24
F25
G1
G2
G3
G4
G22
G23
G24
G25
H1
H2
H3
H4
H22
H23
AVCCB
AGNDB
AVCCB
DNC
DNC
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AINA2
AINA1
AGNDA
AVCCA
REF_A_OUT
AGNDA
DNC
AGNDB
AGNDB
AVCCB
AGNDB
AVCCB
AINB2
AINB1
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDA
AGNDA
AGNDA
AGNDA
AGNDB
AGNDB
AGNDB
AGNDB
AGNDA
AGNDA
AGNDA
AGNDA
AGNDB
AGNDB
AGNDB
AGNDB
AGNDA
AGNDA
AGNDA
AGNDA
AGNDB
AGNDB
AGNDB
AGNDB
AGNDA
AGNDA
AGNDA
AGNDA
AGNDB
AGNDB
H24
H25
J1
J2
J3
J4
J22
J23
J24
J25
K1
K2
K3
K4
K10
K11
K12
K13
K14
K15
K16
K22
K23
K24
K25
L1
L2
L3
L4
L10
L11
L12
L13
L14
L15
L16
L22
L23
L24
L25
M1
M2
M3
M4
M10
M11
M12
M13
M14
M15
M16
M22
M23
M24
M25
N1
N2
N3
N4
N10
N11
N12
N13
N14
N15
AGNDB
AGNDB
AVCCA
AVCCA
AVCCA
AVCCA
REF_B_OUT
REF_B_OUT
REF_B_OUT
REF_B_OUT
AGNDA
AGNDA
AGNDA
AGNDA
SFDR_MODE_A
AGNDA
AGNDA
DNC
AGNDB
AGNDB
SFDR_MODE_B
AGNDB
AGNDB
AGNDB
AGNDB
AGNDA
AGNDA
AGNDA
AGNDA
DFS_A
AGNDA
AGNDA
DNC
AGNDB
AGNDB
DFS_B
ENCBB
ENCBB
ENCBB
ENCBB
ENCAB
ENCAB
ENCAB
ENCAB
AGNDA
AGNDA
AGNDA
DNC
AGNDB
AGNDB
AGNDB
ENCB
ENCB
ENCB
ENCB
ENCA
ENCA
ENCA
ENCA
GAIN_A
AGNDA
AGNDA
DNC
AGNDB
AGNDB
N16
N22
N23
N24
N25
P1
P2
P3
P4
P10
P11
P12
P13
P14
P15
P16
P22
P23
P24
P25
P25
R1
R2
R3
R4
R10
R11
R12
R13
R14
R15
R16
R22
R23
R24
R25
T1
T2
T3
T4
T10
T11
T12
T13
T14
T15
T16
T22
T23
T24
T25
U1
U2
U3
U4
U22
U23
U24
U25
V1
V2
V3
V4
V22
V23
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
DNC
AGNDB
AGNDB
AGNDB
DVCCB
DVCCB
DVCCB
DVCCB
DVCCB
DVCCA
DVCCA
DVCCA
DVCCA
AGNDA
AGNDA
AGNDA
DNC
AGNDB
AGNDB
AGNDB
DB0
DB0
DB0
DB0
DA11
DA11
DA11
DA11
AVCCA
AGNDA
AGNDA
DNC
AVCCB
GAIN_B
AGNDB
DB1
DB1
DB1
DB1
DA10
DA10
DA10
DA10
DB2
DB2
DB2
DB2
DA9
DA9
DA9
DA9
DB3
DB3
V24
V25
W1
W2
W3
W4
W22
W23
W24
W25
Y1
Y2
Y3
Y4
Y22
Y23
Y24
Y25
AA1
AA2
AA3
AA4
AA22
AA23
AA24
AA25
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
DB3
DB3
DA8
DA8
DA8
DA8
DB4
DB4
DB4
DB4
DA7
DA7
DA7
DA7
DB5
DB5
DB5
DB5
DGNDA
DGNDA
DGNDA
DGNDA
DGNDB
DGNDB
DGNDB
DGNDB
OVRA
OVRA
OVRA
OVRA
DGNDA
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DGNDA
DGNDB
DB11
DB10
DB9
DB8
DB7
DB6
DGNDB
OVRB
OVRB
OVRB
OVRB
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DA6
DA5
DA4
DA3
DA2
DA1
DA0
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AE1
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
–6–
DGNDA
DGNDB
DB11
DB10
DB9
DB8
DB7
DB6
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DGNDA
DGNDB
DB11
DB10
DB9
DB8
DB7
DB6
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DGNDA
DGNDB
DB11
DB10
DB9
DB8
DB7
DB6
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
REV. 0
AD10226
385-LEAD BGA PINOUT (Top View, PCB Footprint)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA DNC
DNC
AGNDA AVCCA REF_A_OUT AGNDA DNC AGNDB AGNDB AVCCB AGNDB AVCCB DNC
DNC AGNDB AGNDB AGNDB AGNDB AGNDB
B AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA DNC
DNC
AGNDA AVCCA REF_A_OUT AGNDA DNC AGNDB AGNDB AVCCB AGNDB AVCCB DNC
DNC AGNDB AGNDB AGNDB AGNDB AGNDB
C AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA DNC
DNC
AGNDA AVCCA REF_A_OUT AGNDA DNC AGNDB AGNDB AVCCB AGNDB AVCCB DNC
DNC AGNDB AGNDB AGNDB AGNDB AGNDB
D AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA AINA2 AINA1 AGNDA AVCCA REF_A_OUT AGNDA DNC AGNCB AGNCB AVCCB AGNCB AVCCB AINB2 AINB1 AGNDB AGNDB AGNDB AGNDB AGNDB
E AGNDA AGNDA AGNDA AGNDA
AGNDB AGNDB AGNDB AGNDB
F AGNDA AGNDA AGNDA AGNDA
AGNDB AGNDB AGNDB AGNDB
G AGNDA AGNDA AGNDA AGNDA
AGNDB AGNDB AGNDB AGNDB
H AGNDA AGNDA AGNDA AGNDA
AGNDB AGNDB AGNDB AGNDB
J AVCCA AVCCA AVCCA AVCCA
REF_B_OUT REF_B_OUT REF_B_OUT REF_B_OUT
K AGNDA AGNDA AGNDA AGNDA
SFDR
Mode A
AGNDA
SFDR
AGNDA DNC AGNDB AGNDB Mode B
AGNDB AGNDB AGNDB AGNDB
L AGNDA AGNDA AGNDA AGNDA
DFS_A
AGNDA
AGNDA DNC AGNDB AGNDB DFS_B
ENCBB ENCBB ENCBB ENCBB
M ENCAB ENCAB ENCAB ENCAB
AGNDA
AGNDA
AGNDA DNC AGNDB AGNDB AGNDB
N
ENCA ENCA ENCA ENCA
AGNDA
AGNDA
AGNDA DNC AGNDB AGNDB AGNDB
AGNDB AGNDB AGNDB AGNDB
P AGNDA AGNDA AGNDA AGNDA
AGNDA
AGNDA
AGNDA DNC AGNDB AGNDB AGNDB
DVCCB DVCCB DVCCB DVCCB
R DVCCA DVCCA DVCCA DVCCA
AGNDA
AGNDA
AGNDA DNC AGNDB AGNDB AGNDB
DB0
DB0
DB0
DB0
T
DA11 DA11 DA11 DA11
AVCCB
AGNDA
AGNDA DNC
AVCCB AGNDB AGNDB
DB1
DB1
DB1
DB1
U
DA10 DA10 DA10 DA10
DB2
DB2
DB2
DB2
V
DA9
DA9
DA9
DA9
DB3
DB3
DB3
DB3
W
DA8
DA8
DA8
DA8
DB4
DB4
DB4
DB4
Y
DA7
DA7
DA7
DA7
DB5
DB5
DB5
DB5
ENCB
AA DGNDA DGNDA DGNDA DGNDA
ENCB
ENCB
ENCB
DGNDB DGNDB DGNDB DGNDB
OVRA DGNDA
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DGNDA DGNDB DB11 DB10
DB9
DB8
DB7
DB6 DGNDB OVRB
AC DGNDA DGNDA DGNDA DGNDA DGNDA
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DGNDA DGNDB DB11 DB10
DB9
DB8
DB7
DB6 DGNDB DGNDB DGNDB DGNDB DGNDB
AD DGNDA DGNDA DGNDA DGNDA DGNDA
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DGNDA DGNDB DB11 DB10
DB9
DB8
DB7
DB6 DGNDB DGNDB DGNDB DGNDB DGNDB
AE DGNDA DGNDA DGNDA DGNDA DGNDA
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DGNDA DGNDB DB11 DB10
DB9
DB8
DB7
DB6 DGNDB DGNDB DGNDB DGNDB DGNDB
AB
OVRA
OVRA
OVRA
DNC = DO NOT CONNECT
REV. 0
–7–
OVRB
OVRB
OVRB
AD10226 – Typical Performance Characteristics
0
0
ENCODE = 125MSPS
AIN = 10.3MHz (–1dBFS)
SNR = 68.19dBFS
SFDR = 85.13dBFS
ⴚ10
ⴚ20
ⴚ20
ⴚ30
ⴚ40
ⴚ40
ⴚ50
ⴚ50
ⴚ60
ⴚ60
dB
dB
ⴚ30
ENCODE = 125MSPS
AIN = 121MHz (–1dBFS)
SNR = 63.66dBFS
SFDR = 79.28dBFS
ⴚ10
ⴚ70
ⴚ80
ⴚ70
ⴚ80
ⴚ90
ⴚ90
ⴚ100
ⴚ100
ⴚ110
ⴚ110
ⴚ120
ⴚ120
ⴚ130
ⴚ130
0
5
10
15
20
25 30 35 40
FREQUENCY – MHz
45
50
55
60
0
TPC 1. Single Tone @ 10.3 MHz
10
15
20 25 30 35 40
FREQUENCY – MHz
45
50
55
60
TPC 4. Single Tone @ 121 MHz
0
0
ENCODE = 125MSPS
AIN = 49MHz (–1dBFS)
SNR = 67.12dBFS
SFDR = 83.09dBFS
ⴚ10
ⴚ20
ⴚ30
ENCODE = 125MSPS
AIN = 240MHz (–1dBFS)
SNR = 59.06dBFS
SFDR = 74.56dBFS
ⴚ10
ⴚ20
ⴚ30
ⴚ50
ⴚ60
ⴚ60
dB
ⴚ40
ⴚ50
dB
ⴚ40
ⴚ70
ⴚ80
ⴚ70
ⴚ80
ⴚ90
ⴚ90
ⴚ100
ⴚ100
ⴚ110
ⴚ110
ⴚ120
ⴚ120
ⴚ130
ⴚ130
0
5
10
15
20
25 30 35 40
FREQUENCY – MHz
45
50
55
60
0
TPC 2. Single Tone @ 49 MHz
5
10
15
20
25 30 35 40
FREQUENCY – MHz
45
50
55
60
TPC 5. Single Tone @ 240 MHz
0
0
ENCODE = 125MSPS
AIN = 71MHz (–1dBFS)
SNR = 66.2dBFS
SFDR = 82.02dBFS
ⴚ10
ⴚ20
ⴚ30
ENCODE = 125MSPS
AIN = 29.3MHz AND 30.3MHz
SFDR = 79.03dBFS
ⴚ10
ⴚ20
ⴚ30
ⴚ40
ⴚ40
ⴚ50
ⴚ50
ⴚ60
ⴚ60
dB
dB
5
ⴚ70
ⴚ80
ⴚ70
ⴚ80
ⴚ90
ⴚ90
ⴚ100
ⴚ100
ⴚ110
ⴚ110
ⴚ120
ⴚ120
ⴚ130
ⴚ130
0
5
10
15
20
25 30 35 40
FREQUENCY – MHz
45
50
55
60
TPC 3. Single Tone @ 71 MHz
0
5
10
15
20
25 30 35 40
FREQUENCY – MHz
45
50
55
60
TPC 6. Two Tone @ 29/30 MHz
–8–
REV. 0
AD10226
0
3.0
ENCODE = 125MSPS
AIN = 150MHz AND 151MHz
SFDR = 75.38dBFS
ⴚ10
ⴚ20
ENCODE = 125MSPS
INL MIN = 0.610
INL MAX = 0.702
2.0
ⴚ30
ⴚ40
1.0
ⴚ60
LSB
dB
ⴚ50
ⴚ70
ⴚ80
0.0
ⴚ1.0
ⴚ90
ⴚ100
ⴚ2.0
ⴚ110
ⴚ120
ⴚ130
0
5
10
15
20 25 30 35 40
FREQUENCY – MHz
45
ⴚ3.0
50
55
60
0
512
1024
1536
2048
2560
3072
3584
4096
OUTPUT CODES
TPC 7. Two Tone @ 150/151 MHz
TPC 10. Integral Nonlinearity
0
0
ENCODE = 125MSPS
AIN = 240MHz AND 241MHz
SFDR = 67dBFS
ⴚ10
ⴚ20
ⴚ1
ⴚ30
ⴚ40
ⴚ2
GAIN – dB
dB
ⴚ50
ⴚ60
ⴚ70
ⴚ80
ⴚ3
ⴚ4
ⴚ90
ⴚ100
ⴚ5
ⴚ110
ⴚ120
ⴚ130
ⴚ6
0
5
10
15
20 25 30 35 40
FREQUENCY – MHz
45
50
55
60
10
TPC 8. Two Tone @ 240/241 MHz
100
FREQUENCY – MHz
1000
TPC 11. Frequency Response
3.0
0
ENCODE = 125MSPS
DNL MIN = 0.530
DNL MAX = 0.369
2.5
2.0
GAIN – dB
LSB
1.5
1.0
ⴚ1
0.5
0.0
ⴚ0.5
ⴚ2
ⴚ1.0
0
512
1024
1536
2048
2560
3072
3584
10
4096
OUTPUT CODES
TPC 9. Differential Nonlinearity
100
FREQUENCY – MHz
TPC 12. Gain Flatness*
*Gain flatness measurement is performed by
applying a constant voltage at the device input.
REV. 0
–9–
1000
AD10226
10
9
1MHz
10MHz
50MHz
100MHz
140MHz
160MHz
200MHz
8
GAIN – dB
7
= 1.010
= 1.028
= 1.045
= 1.066
= 1.090
= 1.126
= 1.170
6
5
4
3
10MHz
50MHz
100MHz
150MHz
200MHz
250MHz
300MHz
= 52.22 – j0.421
= 50.69 – j2.84
= 47.50 – j3.58
= 44.61 – j0.970
= 43.70 + j3.70
= 46.41 + j9.48
= 53.09 + j14.76
2
1
0
0.1
TPC 13. Input Impedance S11
10
FREQUENCY – MHz
1
100
1000
TPC 14. Voltage Standing Wave Ratio (VSWR)
Equivalent Circuits
VCC
VCC
VCC
8k⍀
8k⍀
Q1
NPN
ENCODE
ENCODE
24k⍀
24k⍀
VREF OUTPUT
Test Circuit 1. Equivalent ENCODE Input
Test Circuit 3. Equivalent Voltage Reference Output
VCC
VCC
3.75k⍀
3.75k⍀
15k⍀
15k⍀
AIN2
100⍀
50⍀
DIGITAL
OUTPUT
AIN1
Test Circuit 4. Equivalent Analog Input
Test Circuit 2. Equivalent Digital Output
DEFINITION OF TERMS
Analog Bandwidth
Differential Nonlinearity
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
ENCODE Pulsewidth/Duty Cycle
The deviation of any code from an ideal 1 LSB step.
Aperture Delay
The delay between the 50% point on the rising edge of the ENCODE
command and the instant at which the analog input is sampled.
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these specs
define an acceptable ENCODE duty cycle.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
–10–
REV. 0
AD10226
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the worst
harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line measured
in fractions of 1 LSB using a “best straight line” determined by
a least square curve fit.
Minimum Conversion Rate
The ENCODE rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The ENCODE rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of ENCODE
command and the time when all output data bits are within valid
logic levels.
Power Supply Rejection Ratio
The ratio of a change in output offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full-scale)
to the rms value of the sum of all other spectral components,
excluding the first six harmonics and dc. [May be reported in dBc
(i.e., degrades as signal levels are lowered) or in dBFS (always
related back to converter full-scale).]
USING THE AD10226
ENCODE Input
Any high speed A/D converter is extremely sensitive to the quality
of the sampling clock provided by the user. A track/hold circuit
is essentially a mixer, and any noise, distortion, or timing jitter
on the clock will be combined with the desired signal at the A/D
output. For that reason, considerable care has been taken in the
design of the ENCODE input of the AD10226, and the user is
advised to give commensurate thought to the clock source.
The monolithic converter has an internal clock duty cycle stabilization circuit that locks to the rising edge of ENCODE (falling edge
of ENCODE if driven differentially), and optimizes timing internally. This allows for a wide range of input duty cycles at the input
without degrading performance. Jitter in the rising edge of the input
is still of paramount concern and is not reduced by the internal
stabilization circuit. This circuit is always on and cannot be disabled by the user.
The ENCODE and ENCODE inputs are internally biased to 3.75 V
(nominal) and support either differential or single-ended signals.
For best dynamic performance, a differential signal is recommended.
Good performance is obtained using an MC10EL16 in the circuit
to directly drive the encode inputs, as illustrated in Figure 2.
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component may
or may not be a harmonic. [May be reported in dBc (i.e., degrades
as signal levels is lowered) or in dBFS (always related back to
converter full-scale).]
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Voltage Standing Wave Ratio (VSWR)
The ratio of the amplitude of the electric field at a voltage maximum
to that at an adjacent voltage minimum.
APPLICATION NOTES
Theory of Operation
The AD10226 is a high-dynamic-range dual 12-bit, 125 MHz
subrange pipeline converter that uses switched capacitor architecture. The analog input section uses AINA2/B2 at 1.84 V p-p
with an input impedance of 50 Ω. The analog input includes an
ac-coupled wideband 1:1 transformer, which provides high dynamic
range and SNR while maintaining VSWR and gain flatness. The
ADC includes a high bandwidth linear track/hold that gives excellent spurious performance up to and beyond the Nyquist rate. The
high bandwidth track/hold has a low jitter of 0.25 ps rms, leading
to excellent SNR and SFDR performance. AC-coupled differential PECL/ECL encode inputs are recommended for optimum
performance.
REV. 0
ENCODE
ENCODE
510⍀
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full-scale)
to the rms value of the sum of all other spectral components,
excluding the first six harmonics and dc. [May be reported in
dBc (i.e., degrades as signal levels are lowered) or in dBFS (always
related back to converter full-scale).]
AD10226
0.1␮F
PECL
GATE
510⍀
0.1␮F
GND
Figure 2. Using PECL to Drive ENCODE Inputs
Often, the cleanest clock source is a crystal oscillator producing
a pure, single-ended sine wave. In this configuration, or with any
roughly symmetrical, single-ended clock source, the signal can
be ac-coupled to the ENCODE input. To minimize jitter, the
signal amplitude should be maximized within the input range
described in the Table II.
Table II. ENCODE Inputs
Description
Differential Signal
Amplitude (VID)
Input Voltage
Range (VHID, VILD, VHIS)
Internal Common-Mode
Voltage (VICM)
External Common-Mode
Bias (VECM)
Min
Nom
Max
200 mV
750 mV
5.5 V
–5 V
VCC + 0.5 V
3.75 V
2.0 V
4.25 V
0.1␮F
AD10226
ENCODE
50⍀
SINE
SOURCE
0.1␮F
ENCODE
50⍀
50⍀
50⍀
Figure 3. Single-Ended 50 Sine Encode Circuit
The 10 kΩ resistors to ground at each of the inputs, in parallel with
the internal bias resistors, set the common-mode voltage to ~ 2.5 V,
–11–
AD10226
allowing the maximum swing at the input. The ENCODE input
should be bypassed with a capacitor to ground to reduce noise.
This ensures that the internal bias voltage is centered on the
encode signal (Figure 3). For best dynamic performance, impedances at ENCODE and ENCODE should match.
Figure 4 shows another preferred method for clocking the AD10226.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD10226 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD9433, and limits the noise
presented to the ENCODE inputs. A crystal clock oscillator can
also be used to drive the RF transformer if an appropriate limiting
resistor (typically 100 Ω) is placed in the series with the primary.
AD10226
0.1␮F
ENCODE
100⍀
CLOCK
SOURCE
Digital Outputs
The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL/CMOScompatible for lower power consumption. The output data format
is selectable through the data format select (DFS) CMOS input.
DFS = 1 selects offset binary coding (Table III); DFS = 0 selects Two’s Complement coding (Table IV).
Table III. Offset Binary Output Coding (DFS = 1, VREF = 2.5 V)
Code
AIN – AIN (V)
Range = 2 V p-p
Digital
Output
4095
•
•
2048
2047
•
•
0
+0.92
•
•
0
–0.00045
•
•
–0.92
1111 1111 1111
•
•
1000 0000 0000
0111 1111 1111
•
•
0000 0000 0000
ENCODE
Figure 4. Double-Ended 50 Sine Encode Circuit
ENCODE Voltage Level Definition
The voltage level definitions for driving ENCODE and ENCODE
in differential mode is shown in Figure 6.
VIHD
ENCODE
VIHS V ILS
ENCODE
VIHS
ENCODE
ENCODE
VID
VILD
VIHS V ILS
0.1␮F
VILS
Figure 5. Differential Input Levels
Analog Input
The analog input is a single-ended ac-coupled high performance
1:1 transformer with an input impedance of 50 Ω to 350 MHz.
The nominal full scale input is 1.87 V p-p.
Special care was taken in the design of the analog input section
of the AD10226 to prevent damage and corruption of data when
the input is overdriven.
SFDR Optimization
The SFDR MODE pin enables (SFDR MODE = 1) a proprietary
circuit that may improve the spurious-free dynamic range (SFDR)
performance of the AD10226. It is useful in applications where the
dynamic range of the system is limited by discrete spurious frequency
content caused by nonlinearities in the ADC transfer function.
Table IV. Two’s Complement Output Coding
(DFS = 0, VREF = 2.5 V)
Code
AIN – AIN (V)
Range = 2 V p-p
Digital
Output
+2047
•
•
0
–1
•
•
–2048
+0.92
•
•
0
–0.00045
•
•
–0.92
0111 1111 1111
•
•
0000 0000 0000
1111 1111 1111
•
•
1000 0000 0000
Voltage Reference
A stable and accurate 2.5 V voltage reference is designed into the
AD10226 (VREFOUT). An external voltage reference is not required.
Timing
The AD10226 provides latched data outputs, with 10 pipeline
delays. Data outputs are available one propagation delay (tPD) after
the rising edge of the ENCODE command (see Figure 1). The
length of the output data lines and loads placed on them should
be minimized to reduce transients within the AD10226; these
transients can detract from the converter’s dynamic performance.
The minimum guaranteed conversion rate of the AD10226 is
10 MSPS. At internal clock rates below 10 MSPS, dynamic performance may degrade. Therefore, input clock rates below 10 MHz
should be avoided.
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high-speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recommended
Enabling this circuit will give the circuit a dynamic transfer function,
to provide optimal grounding and power schemes. The use of
meaning that the voltage threshold between two adjacent output
ground and power planes offers distinct advantages:
codes may change from clock cycle to clock cycle. While improv1. The minimization of the loop area encompassed by a signal
ing spurious frequency content, this dynamic aspect of the transfer
and its return path.
function may be inappropriate for some time domain applications
2. The minimization of the impedance associated with ground
of the converter. Connecting the SFDR Mode pin to ground will
and power paths.
disable this function. The Typical Performance Characteristics
section of the data sheet illustrates the improvement in the linearity
3. The inherent distributed capacitor formed by the powerplane,
of the converter and its effect on spurious-free dynamic range.
PCB insulation, and ground plane.
–12–
REV. 0
AD10226
These characteristics result in both a reduction of electromagnetic
interference (EMI) and an overall improvement in performance.
LAYOUT INFORMATION
It is important to design a layout that prevents noise from coupling
to the input signal. Digital signals should not be run in parallel
with input signal traces and should be routed away from the input
circuitry. The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance path and manage the power and ground currents. The
ground plane should be removed from the area near the input
pins to reduce stray capacitance.
Solder Reflow Profile
The Solder Reflow Profile for the AD10226 is shown in Figure 6.
250
EVALUATION BOARD
200
TEMPERATURE – ⴗC
The schematic of the evaluation board (Figures 7a–7d) represents
a typical implementation of the AD10226. The pinout of the
AD10226 is very straightforward and facilitates ease of use and the
implementation of high-frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors
be used to decouple each supply pin to ground directly at the device.
All capacitors can be standard high quality ceramic chip capacitors.
Care should be taken when placing the digital output runs. Because
the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for
the digital outputs should be kept short and connect directly to
the receiving gate. Internal circuitry buffers the outputs of the
AD9433 ADC through a resistor network to eliminate the need
to externally isolate the device from the receiving gate.
150
100
50
0
0
50
100
150
200
250
TIME – Seconds
300
350
Figure 6. Typical Solder Reflow Profile
400
The AD10226 evaluation board (Figures 7a–7d) is designed to
provide optimal performance for evaluation of the AD10226
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating the
AD10226. The board requires an analog input signal, an ENCODE
clock and power supply inputs. The clock is buffered on-board to
provide clocks for the latches. The digital outputs and out clocks
are available at the standard 40-pin connectors J1 and J2. Power
to the analog supply pins is connected via banana jacks. The analog
supply powers the associated components and analog section of the
AD10226. The digital outputs of the AD10226 are also powered
via banana jacks with 3.3 V. Contact the factory if additional layout
or application assistance is required.
BILL OF MATERIALS LIST FOR AD10226 EVALUATION BOARD
Quantity
Reference Designator
2
U16, U17
1
2
U1
U14, U15
4
8
32
2
2
4
4
R38, R39, R56, R58
R1, R7, R8, R41, R60, R61, R71, R72
R3, R4, R9–R18, R23–R30, R35,
R36, R40, R42–R46, R63–R66
C1, C2, C5–C10, C12, C16–C18,
C20–C26, C28, C33–C35
C13, C27
J1, J2
L1, L2, L3, L4
U2, U3, U9, U11
8
2
E3–E6, E25, E26, E33, E34
U4, U10
10
C3, C4, C11, C14, C15, C19,
C29, C30–C32
J3–J7, J10–J12
23
8
4
4
1
2
6
REV. 0
AD10201/AD10226 Evaluation Board
C36, C37
JP3, JP4, JP6, JP8, JP9, JP12
Value
Description
Part Number
33 kΩ
51 Ω
100 Ω
IC, Low Voltage 16-Bit D-Type Flip-Flop
with 5 V Tolerant Inputs and Outputs
IC, BGA 35 35 385
IC, Precision Low Dropout any CAP
Voltage Regulator
RES 33 kΩ 1/10W 0.1% 0805 SMD
RES 51 Ω 1/10W 5% 0805 SMD
RES 100 Ω 1/10W 1% 0805 SMD
0.1 µF
CAP 0.1 µF 50 V Ceramic Y5V 0805
74LCX16374MTD
(Fairchild)
AD10226AB
ADP3330ART-3.3-RL7
(Analog)
ERA-6YEB333V (Panasonic)
ERJ-6GEYJ510V (Panasonic)
ERJ-6ENF1000V
(Panasonic)
ECJ-2VF1H104Z
(Panasonic)
ECJ-2YF1E474Z (Panasonic)
TSW-120-08G-D (Samtec)
2743019447 (Fair Rite)
MC10EP16D
(Motorola)
108-0740-001 (Johnson Company)
SY100ELT23L
(Micrel-Synergy)
T491C106M016AS
(KEMET)
142-0801-201
(Johnson Components Inc.)
0.47 µF CAP 0.47 µF 25 V Ceramic Y5V 0805
2 20 Male Connector Strip, 100 Centers
47 Ω
SMT Ferrite Bead
IC, 3.3 V/5 V ECL Differential
Receiver/Driver
Power Jack, Banana Plug
3.3 V Dual Differential
LVPECL-to-LVTTL Translator
10 µF
Solid Tantalum Chip Capacitor,
10 µF, 16 V, 20%
SMA PLUG 200Mil STR GOLD
0Ω
Spacer Aluminum, Hex M–F (Standoff)
Nut Hex Stl #4-40 UNC-2B
GS03983 Rev. A (PCB)
CAP 0.047 µF 25 V Ceramic Y5V 0603
RES 0 Ω 1/16 W 5% 0402
–13–
ECJ-1VB1C473K
ER J-2GEOR00
AD10226
R18
100⍀
DUT_3.3VDA
U16
R7
51⍀
LATCHA
MSB D11A
D10A
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
D1A
LSB D0A
25
24
26
27
29
30
32
33
35
36
48
1
37
38
40
41
43
44
46
47
28
34
39
45
CP2
OE2
I15
I14
I13
I12
I11
I10
I9
I8
CP1
OE1
I7
I6
I5
I4
I3
I2
I1
I0
GND
GND
GND
GND
VCC
VCC
VCC
VCC
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
GND
GND
GND
GND
42
31
7
18
23
22
20
19
17
16
14
13
B11A MSB
R17
100⍀
B10A
R16
100⍀
R40
100⍀
B8A
R44
100⍀
B7A
R45
100⍀
B6A
R46
100⍀
12
11
9
8
6
5
3
2
21
15
10
4
J1
MSB B11A
B10A
+ C15
B9A
10␮F
16V
B8A
B7A
DGNDA
B6A
B5A
R71
51⍀ B4A
BUFLATA
B5A
R15
100⍀
R14
100⍀
R13
100⍀
R24
100⍀
B3A
B2A
B1A
LSB B0A
B4A
B3A
B2A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
B1A
R23
100⍀
DGNDA
DGNDA
B0A LSB
74LCX16374MTD
DGNDA
3.3VDA
B9A
DGNDA
R11
100⍀
DUT_3.3VDB
U17
R8
51⍀
LATCHB
MSB D11B
D10B
D9B
D8B
D7B
D6B
D5B
D4B
D3B
D2B
D1B
LSB D0B
25
24
26
27
29
30
32
33
35
36
48
1
37
38
40
41
43
44
46
47
28
34
39
45
CP2
OE2
I15
I14
I13
I12
I11
I10
I9
I8
CP1
OE1
I7
I6
I5
I4
I3
I2
I1
I0
GND
GND
GND
GND
VCC
VCC
VCC
VCC
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
GND
GND
GND
GND
42
31
7
18
23
22
20
19
17
16
14
13
B11B MSB
R10
100⍀
B10B
R30
100⍀
R29
100⍀
B8B
R28
100⍀
B7B
R27
100⍀
B6B
R26
100⍀
12
11
9
8
6
5
3
2
21
15
10
4
J2
MSB B11B
B10B
+ C14
B9B
10␮F
16V
B8B
B7B
DGNDB
B6B
B5B
R72
51⍀ B4B
BUFLATB
B5B
R12
100⍀
R9
100⍀
R25
100⍀
R36
100⍀
B4B
B3B
B2B
B3B
B2B
B1B
LSB B0B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
B1B
R35
100⍀
DGNDB
DGNDB
B0B LSB
74LCX16374MTD
DGNDB
3.3VDB
B9B
DGNDB
Figure 7a. Evaluation Board Schematic
–14–
REV. 0
AD10226
E4
E6
AGNDA
5VAA
L3
1
2
J3
5VAA
AINA1
AINA1
47⍀ @ 100MHz
+ C3
10␮F
16V
C20
0.1␮F
+ C11
10␮F
16V
JP1
STITCHES TO TIE GROUNDS TOGETHER
AGNDA
AGNDA
AGNDA
DGNDA
DGNDA
DGNDA
AGNDA
DGNDB
E3
E5
AGNDB
5VAB
E77
E12
E9
E11
E2
E42
E44
E48
E66
E67
E70
E72
E73
E76
E81
E41
E43
E47
E65
E68
E69
E71
E74
E75
E82
2
AINA2
5VAB
47⍀ @ 100MHz
+ C4
10␮F
16V
AINA2
AGNDA
C21
0.1␮F
AGNDB
+ C19
10␮F
16V
J7
AINB2
AINB2
AGNDB
AGNDB
E34
DGNDA
E25
DGNDA
3.3VDA
L1
1
2
AINB1
AINB1
+ C31
10␮F
16V
C12
0.1␮F
JP2
DGNDB
AGNDB
DGNDA
DGNDA
E33
E26
DGNDB
3.3VDB
L2
1
2
DUT_3.3VDB
47⍀ @ 100MHz
+ C30
10␮F
16V
C16
0.1␮F
DGNDB
5VAA
+ C32
10␮F
16V
DGNDB
C34
0.1␮F
DUT_3.3VDA
C10
0.1␮F
AGNDA
DUT_3.3VDB
C9
0.1␮F
C18
0.1␮F
DGNDA
Figure 7b. Evaluation Board Schematic
REV. 0
–15–
AGNDA
E29
E36
E38
E40
E45
E79
E84
J6
DUT_3.3VDA
47⍀ @ 100MHz
+ C29
10␮F
16V
DGNDB
DGNDB
AGNDA
AGNDB
AGNDB
J4
L4
1
E78
E7
E10
E8
E1
C17
0.1␮F
DGNDB
E30
E35
E37
E39
E46
E80
E83
AGNDB
AD10226
3.3VA
U14
5VAA
2
6
IN
OUT
NR
SD
ERR
1
5
3
GND
4
AGNDA
C1
0.1␮F
J5
C7
0.1␮F
U2
ENCODE
R1
51⍀
AGNDA
R56
33k⍀
3.3VA
1
2
3
4
AGNDA
NC
ENCAB
8
VCC
D
Q
D
Q
VBB
7
6
5
VEE
C13
0.1␮F
25V
MC10EP16D
AGNDA
3.3VDA
1
2
3
4
C2
0.1␮F
J12
NC
AGNDA
7
Q
D
Q
VEE
R41
51⍀
1
5
2
C6
0.1␮F
3
R3
100⍀
R4
100⍀
4
D0
VCC
D0
Q
D1
Q
D1
GND
8
LATCHA
7
E23
6
E19
5
C5
0.1␮F
SY100EPT23L
DGNDA
AGNDA
3.3VDA
U4
6
MC10EP16D
ENCA
ENCA
8
VCC
D
VBB
C8
0.1␮F
R43
100⍀
3.3VDA
U3
R58
33k⍀
R42
100⍀
BUFLATA
DGNDA
AGNDA
DGNDA
3.3VB
U15
5VAB
2
6
IN
OUT
NR
SD
ERR
1
5
3
GND
4
AGNDB
C22
0.1␮F
J10
C24
0.1␮F
U11
ENCODE
R60
51⍀
AGNDB
R38
33k⍀
3.3VB
1
2
3
4
AGNDB
NC
ENCBB
VCC
D
Q
D
Q
VBB
VEE
8
7
6
5
C27
0.47␮F
25V
MC10EP16D
AGNDB
3.3VDB
1
2
3
C23
0.1␮F
J11
4
NC
D
D
VBB
VCC
R61
51⍀
AGNDB
ENCB
AGNDB
Q
Q
VEE
8
7
3.3VDB
U10
6
1
2
5
C25
0.1␮F
MC10EP16D
ENCB
C28
0.1␮F
R64
100⍀
3.3VDB
U9
R39
33k⍀
R63
100⍀
3
R65
100⍀
R66
100⍀
4
D0
VCC
D0
Q
D1
Q
D1
GND
8
E24
6
E22
5
SY100EPT23L
DGNDB
LATCHB
7
C26
0.1␮F
BUFLATB
DGNDB
AGNDB
DGNDB
Figure 7c. Evaluation Board Schematic
–16–
REV. 0
AD10226
C33
0.1␮F
C36
0.047␮F
AGNDA
+5VAA
JP4
AGNDA
+5VAA
DGNDA
AA22
AA23
AA24
AA25
AB14
AB21
AC14
AC21
AC22
AC23
AC24
AC25
AD14
AD21
AD22
AD23
AD24
AD25
AE14
AE21
AE22
AE23
AE24
AE25
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AINA2
ENCAB
ENCA
D11A
D10A
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
D1A
5VAA
5VAA
5VAA
5VAA
5VAA
5VAA
5VAA
5VAA
3.3VDA
3.3VDA
3.3VDA
3.3VDA
SHEILD
SHEILD
SHEILD
SHEILD
SHEILD
SHEILD
SHEILD
SHEILD
SHEILD
SHEILD
SHEILD
3.3VDB
3.3VDB
3.3VDB
3.3VDB
5VAB
5VAB
5VAB
5VAB
5VAB
5VAB
5VAB
5VAB
JP3
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
+5VAA
+5VAA
AD10226
JP6
AGNDA
AGNDA
AGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDA
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
DGNDB
+5VAB
JP8
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
+5VAB
C37
0.047␮F
AGNDB
JP9
AGNDB
+5VAB
JP12
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
AGNDB
J1
J2
J3
J4
A10
B10
C10
D10
+5VAA
R1
R2
R3
R4
DUT_3.3VDA
A13
B13
C13
D13
K13
L13
M13
N13
P13
R13
T13
P22
P23
P24
P25
DUT_3.3VDB
A16
B16
C16
D16
A18
B18
C18
D18
+5VAB
A14
A15
A17
A21
A22
A23
A24
A25
B14
B15
B17
B21
B22
B23
B24
B25
C14
C15
C17
C21
C22
C23
C24
C25
D14
D15
D17
D21
D22
D23
D24
D25
E22
E23
E24
E25
F22
F23
F24
F25
G22
G23
G24
G25
H22
H23
H24
H25
K14
K15
K16
K22
K23
K24
K25
L14
L15
L16
M14
M15
M16
N14
N15
N16
N22
N23
N24
N25
P14
P15
P16
R14
R15
R16
T14
T15
T16
AGNDB
C35
AGNDB 0.1␮F
Figure 7d. Evaluation Board Schematic
REV. 0
–17–
E50
AINB2
AINB1
ENCBB
ENCB
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B
OVRB
AB25
AB24
AB23
AB22
AE15
AD15
AC15
AB15
AE16
AD16
AC16
AB16
AE17
AD17
AC17
AB17
AE18
AD18
AC18
AB18
AE19
AD19
AC19
AB19
AE20
AD20
AC20
AB20
Y25
Y24
Y23
Y22
W25
W24
W23
W22
V25
V24
V23
V22
U25
U24
U23
U22
T25
T24
T23
T22
R25
R24
R23
R22
M25
M24
M23
M22
L25
L24
L23
L22
J25
J24
J23
J22
D20
C20
B20
A20
D19
C19
B19
A19
DGNDB
AA1
AA2
AA3
AA4
AB5
AB13
AC1
AC2
AC3
AC4
AC5
AC13
AD1
AD2
AD3
AD4
AD5
AD13
AE1
AE2
AE3
AE4
AE5
AE13
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
OVRB
OVRB
OVRB
OVRB
D11B (MSBB)
D11B (MSBB)
D11B (MSBB)
D11B (MSBB)
D10B
D10B
D10B
D10B
D9B
D9B
D9B
D9B
D8B
D8B
D8B
D8B
D7B
D7B
D7B
D7B
D6B
D6B
D6B
D6B
D5B
D5B
D5B
D5B
D4B
D4B
D4B
D4B
D3B
D3B
D3B
D3B
D2B
D2B
D2B
D2B
D1B
D1B
D1B
D1B
D0B (LSBB)
D0B (LSBB)
D0B (LSBB)
D0B (LSBB)
ENCB
ENCB
ENCB
ENCB
ENCBB
ENCBB
ENCBB
ENCBB
REF_B
REF_B
REF_B
REF_B
AINB1
AINB1
AINB1
AINB1
AINB2
AINB2
AINB2
AINB2
AGNDA
A1
A2
A3
A4
A5
A6
A9
A12
B1
B2
B3
B4
B5
B6
B9
B12
C1
C2
C3
C4
C5
C6
C9
C12
D1
D2
D3
D4
D5
D6
D9
D12
E1
E2
E3
E4
F1
F2
F3
F4
G1
G2
G3
G4
H1
H2
H3
H4
K1
K2
K3
K4
K10
K11
K12
L1
L2
L3
L4
L10
L11
L12
M10
M11
M12
N10
N11
N12
P1
P2
P3
P4
P10
P11
P12
R10
R11
R12
T10
T11
T12
OVRA
OVRA
OVRA
OVRA
D0A (LSBA)
D0A (LSBA)
D0A (LSBA)
D0A (LSBA)
D1A
D1A
D1A
D1A
D2A
D2A
D2A
D2A
D3A
D3A
D3A
D3A
D4A
D4A
D4A
D4A
D5A
D5A
D5A
D5A
D6A
D6A
D6A
D6A
D7A
D7A
D7A
D7A
D8A
D8A
D8A
D8A
D9A
D9A
D9A
D9A
D10A
D10A
D10A
D10A
D11A (MSBA)
D11A (MSBA)
D11A (MSBA)
D11A (MSBA)
ENCA
ENCA
ENCA
ENCA
ENCAB
ENCAB
ENCAB
ENCAB
AINA2
AINA2
AINA2
AINA2
AINA1
AINA1
AINA1
AINA1
REF_A
REF_A
REF_A
REF_A
AB4
AB3
AB2
AB1
AE12
AD12
AC12
AB12
AE11
AD11
AC11
AB11
AE10
AD10
AC10
AB10
AE9
AD9
AC9
AB9
AE8
AD8
AC8
AB8
AE7
AD7
AC7
AB7
AE6
AD6
AC6
AB6
Y4
Y3
Y2
Y1
W4
W3
W2
W1
V4
V3
V2
V1
U4
U3
U2
U1
T4
T3
T2
T1
N4
N3
N2
N1
M4
M3
M2
M1
D7
C7
B7
A7
D8
C8
B8
A8
D11
C11
B11
A11
D0A
OVRA
AINA1
E49
AGNDA
AGNDB
+5VAB
AD10226
E5 +5VAB
E33 DGNDB
E3 AGNDB
E37
E38
E29
E30
+
C4
C30
+
E1
E2
J2
E26 +3.3VDB
C16
L2
L4
J10
ENCB
E80
ENCB
J11
+
C32
R
R 11
R 10
R 30
R 29
2
R 8
R 27
R 26
12
R R9
2
R 5
R 36
35
C19
+
E36
GNDTIES
E35
E79
E46
E45
E83
E84
E22
BUFLATB
LATCHB
E24
E50
JP2
REF_B
J6
AINB2
E11
E39
GNDTIE
AINB1
J7
GNDTIE
J3
E49
E8
E47
E12
E77
AINA1
GNDTIE
GNDTIE
E78
E7
REF_A
J1
JP1
18
R 17
R 16
R 40
R 44
R 45
R 46
R 15
R 14
R 13
R 24
R 23
R
J4
U1
AINA2
ENCA
ENCA
L3
E82
E81
E65
E66
E9
E10
E41
E42
J12
J5
+ C11
GNDTIES
GS03983 REV: A
AD10201/ AD10206
EVALUATION BOARD
E43
E68
C3
+
+5VAA
E6
AGNDA
E4
E44
BUFLATA
E19
E23
LATCHA
C31
+
L1
C29
+
E67
E74
E73
E71
E72
E69
E70
E75
E76
C12
E34 DGNDA
E25 +3.3VDA
Figure 8a. Mechanical Layout Top View
GNDTIES
+
C14
Figure 8c. Top View
R72
R61
U10
C23
C17 R8
R38
R66
C27
R65
C25
U17
R60
C22
U11
R39
C26
U9
R63
R64
U15
C18 C28 C24
C21
JP12
JP9
C35
GNDTIE
C37
JP8
JP3
+5V
GNDTIE
JP6
U16
JP4
R43
C9
GNDTIE
C33
C8
C10
C7
R42
C15
GNDTIE
C36
C20
C34
U3
R7
U14
R56
R58
U2
C13
R4
R3
C1
R1
C6
U4
R71
R41
C2
GNDTIES
C5
Figure 8b. Mechanical Layout Bottom View
Figure 8d. Layer 2
–18–
REV. 0
AD10226
Figure 8g. Ground View 2
Figure 8e. Layer 3
Figure 8f. Ground View 1
REV. 0
–19–
AD10226
OUTLINE DIMENSIONS
Dimensions shown in millimeters (mm).
385-Lead Ball Grid Array (BGA)
C02927–0–5/02(0)
(B-385)
37.00
35.00 BSC SQ
33.00
24 22 20 18 16 14 12 10 8 6 4 2
25 23 21 19 17 15 13 11 9 7 5 3 1
A
B
C
E D
G F
H
J
K
L
M
N P
R T
U
V
W
Y
AA
AB
AC AD
AE
AD10201AB
XXXX
DETAIL C
30.48 BSC
SQ
DETAIL A
1.27 TYP
DETAIL A
3.20
MAX
1.15
1.02
0.89
0.90
0.75
0.60
0.75
0.60
0.50
DETAIL B
DETAIL C
PRINTED IN U.S.A.
COMPONENT
VOLUME
AD10201AB
XXXX
DETAIL B
–20–
REV. 0