SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES327 – APRIL 2000 D D D D D Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process DOC (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC D D D D Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Ioff Supports Partial-Power-Down Mode Operation ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Packaged in Plastic Fine-Pitch Ball Grid Array Package description A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009. 3.2 TA = 25°C Process = Nominal – Output Voltage – V 2.4 VCC = 3.3 V 2.0 1.6 VCC = 2.5 V 1.2 OH VCC = 1.8 V 0.8 V VOL – Output Voltage – V 2.8 2.8 TA = 25°C Process = Nominal 2.4 2.0 1.6 1.2 0.8 VCC = 3.3 V VCC = 2.5 V 0.4 0.4 0 17 34 51 68 85 102 119 IOL – Output Current – mA 136 153 170 VCC = 1.8 V –160 –144 –128 –112 –96 –80 –64 –48 IOH – Output Current – mA –32 –16 0 Figure 1. Output Voltage vs Output Current This 32-bit transparent D-type latch with is operational from 1.2-V or 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVC32373 can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DOC, EPIC, and Widebus are trademarks of Texas Instruments. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES327 – APRIL 2000 description (continued) OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC32373 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 8-bit latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z GKE PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 1 2 A 1Q2 1Q1 B 1Q4 1Q3 C C 1Q6 1Q5 D D 1Q8 E E 2Q2 F F G A B H 4 5 6 1OE 1LE 1D1 1D2 GND GND 1D3 1D4 1VCC GND 1D5 1D6 1Q7 1VCC GND 1D7 1D8 2Q1 GND GND 2D1 2D2 2Q4 2Q3 2D4 2Q6 2Q5 1VCC GND 2D3 G 1VCC GND 2D5 2D6 H 2Q7 2Q8 2OE 2LE 2D8 2D7 J 3Q2 3Q1 3OE 3LE 3D1 3D2 K 3Q4 3Q3 GND GND 3D3 3D4 L 3Q6 3Q5 3D6 3Q8 3Q7 2VCC GND 3D5 M 2VCC GND 3D7 3D8 N 4Q2 4Q1 GND GND 4D1 4D2 N P 4Q4 4Q3 4Q6 4Q5 2VCC GND 4D4 R 2VCC GND 4D3 P 4D5 4D6 R T 4Q7 4Q8 4OE 4LE 4D8 4D7 J K L M T 2 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES327 – APRIL 2000 logic diagram (positive logic) 1OE 1LE A3 2OE A4 2LE C1 1D1 A5 A2 1D H3 H4 C1 1Q1 2D1 E5 To Seven Other Channels E2 1D 2Q1 To Seven Other Channels NOTE A: 1VCC is associated with these channels. 3OE 3LE J3 4OE J4 4LE C1 3D1 J5 J2 1D T3 T4 C1 3Q1 To Seven Other Channels 4D1 N5 1D N2 4Q1 To Seven Other Channels NOTE B: 2VCC is associated with these channels. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES327 – APRIL 2000 recommended operating conditions (see Note 4) VCC VIH Supply voltage Operating High-level input voltage MIN MAX 1.2 3.6 VCC = 1.2 V VCC = 1.4 V to 1.6 V VCC 0.65 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0.65 × VCC Low-level input voltage Input voltage VO Output voltage IOHS GND 0.35 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V Static high-level high level output current† IOLS Static low-level low level output current† ∆t/∆v Input transition rise or fall rate V 2 V 0.7 VCC = 3 V to 3.6 V VI V 1.7 VCC = 1.2 V VCC = 1.4 V to 1.6 V VIL UNIT 0.8 0 3.6 V Active state 0 3-state 0 VCC 3.6 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V –2 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V –8 –4 mA –12 VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V 2 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 8 12 VCC = 1.4 V to 3.6 V 5 4 mA ns/V TA Operating free-air temperature –40 85 °C † Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009. NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES327 – APRIL 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOHS = –100 µA IOHS = –2 mA, VOH VIH = 0.91 V VIH = 1.07 V IOHS = –4 mA, IOHS = –8 mA, II Ioff Control inputs IOZ ICC IOLS = 2 mA, IOLS = 4 mA, VIL = 0.49 V VIL = 0.57 V IOLS = 8 mA, IOLS = 12 mA, VIL = 0.7 V VIL = 0.8 V VI = VCC or GND VI or VO = 3.6 V IO = 0 Co VI = VCC or GND Outputs Out uts TYP† VO = VCC or GND MAX UNIT VCC–0.2 1.05 1.65 V 1.2 2.3 V 1.75 3V 2.3 V 0.2 1.4 V 0.4 1.65 V 0.45 2.3 V 0.55 V 3V 0.7 3.6 V ±2.5 µA 0 ±10 µA 3.6 V ±10 µA 3.6 V 40 µA 2.5 V VI = VCC or GND Ci Data inputs MIN 1. V to 3.6 V VO = VCC or GND VI = VCC or GND, Control inputs 1.4 V VIH = 1.7 V VIH = 2 V IOHS = –12 mA, IOLS = 100 µA VOL VCC 1.2 V to 3.6 V 3 3.3 V 3 2.5 V 2.5 3.3 V 2.5 2.5 V 6.5 3.3 V 6.5 pF pF F † Typical values are measured at VCC = 2.5 V and 3.3 V, TA = 25°C. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5) VCC = 1.2 V MIN tw tsu Pulse duration, LE high th Hold time, data after LE↓ Setup time, data before LE↓ MAX VCC = 1.5 V ± 0.1 V MIN MAX VCC = 1.8 V ± 0.15 V MIN MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN UNIT MAX 2.2 2 1.8 ns 1.7 1.2 1.1 0.9 0.8 ns 2 1.1 1.1 1.1 1 ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5) PARAMETER tpd d FROM (INPUT) D LE TO (OUTPUT) Q VCC = 1.2 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 5.8 1.2 6.8 1 5.7 0.8 3.3 0.7 2.8 7.2 1.4 8.3 1.1 6.6 0.8 4 0.7 3.2 UNIT ns ten OE Q 7.4 1.6 8.8 1.6 6.7 1.4 4.3 0.7 3.4 ns tdis OE Q 8.4 2.5 9.4 2.3 7.8 1.3 4.2 1.2 3.9 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES327 – APRIL 2000 operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled Power dissipation capacitance Cpd d Outputs disabled CL = 0, 0 VCC = 1.8 V TYP f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 40 43 47 20 22 24 UNIT pF PARAMETER MEASUREMENT INFORMATION VCC = 1.2 V AND 1.5 V ± 0.1 V 2 × VCC S1 2 kΩ From Output Under Test Open GND CL = 15 pF (see Note A) 2 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.1 V VOL tPHZ VCC/2 VOH VOH – 0.1 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES327 – APRIL 2000 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES327 – APRIL 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES327 – APRIL 2000 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V From Output Under Test 2 × VCC S1 500 Ω GND CL = 30 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND Open 500 Ω tw LOAD CIRCUIT VCC VCC Timing Input VCC/2 Input VCC/2 VCC/2 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC Output Control (low-level enabling) VCC/2 0V tPZL VCC Input VCC/2 VCC/2 0V tPLH Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 tPLZ VCC VCC/2 VOL + 0.3 V VOL tPZH tPHL VOH Output VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) tPHZ VCC/2 VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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