AKM AK2571

AKM Confidential
AK2571
= Preliminary =
AK2571
Single-Chip Automatic Power/Temperature Control
for WDM Laser Diodes
Features
Single Chip LSI that integrates APC (Auto Power Control) and ATC (Auto Temperature Control) functions for
WDM Laser Module
A controlling TEC (Thermal Electrical Cooler) stabilizes the temperature of LD module in the range of +/-0.1°C
by PID algorithm.
Parameters controlling Laser Diode are user programmable and stored in EEPROM
Internal Temperature Sensor detects on-chip temperature, enabling compensation internal and external
components that may be affected by changing ambient temperature.
Autonomous operation (internal oscillator and logic).
Pin-selectable wavelength data for tunable laser diodes (four options).
Single 3.3V operation
64-pin LQFP or Bare chip
Description
The AK2571 is a single-chip solution for WDM Laser Diode Module applications. It integrates both ATC (Auto
Temperature Control) and APC (Auto Power Control) functions in a small 64-pin LQFP or bare die package..
The ATC function of the AK2571 detects the LD module temperature via an external thermister and uses the PID
algorithm to control the Thermo-Electric Cooler (TEC). This provides +/- 0.1°C stabilization.. A customer can program the
appropriate PID parameters into the internal EEPROM , thereby providing compensation characteristics for each Laser
Diode. TEC control is handled through either PWM or Analog current control through I-DAC4. These are easily selected
by an EEPROM (Register) setting.
The APC has two functions. The first function is to compensate for Laser Diode power decreases caused by aging. The
other function is to compensate for temperature variations of AK2571 and external components (current amplifier or
driver circuits) which may be affected by ambient temperature within the LDM. The AK2571 does this by controlling
BIAS and modulation current according to the look up table in EEPROM .
The AK2571 has every alarm needed for WDM modules (Loss of power, Over current, Temperature etc.). There is a
dithering function for modulation current that improves the extinction ratio for long distance transmissions.
Also, parameter and compensation data can be stored for four wavelengths. If a customer uses a tunable laser diode, it is
very easy to change the wavelength by pin control.
<Rev. 0.6E Preliminary>
-1-
2001/11
AKM Confidential
AK2571
Block Diagram
AK2571 - Block Diagram RB (12k)
IOUT1
BIAS
I-DAC1
BIAS GEN
EEPROM
Store the
parameter and
look up table
PDMON
Monitor
PD
I-DAC2
IOUT3
Gain Adj
RPD
Driver
+
LD
IOUT2
APC
I-DAC3
PDIN
CPD
STATUS_MON
TIMERALM
REFOUT
Regulator
OPALM(Optical out down)
Alarm Decision
CUALM(Over Current)
TEMPALM(Temperature ALM
Rth
PIDALM(TECControl current ALM)
RL
Gain &
OFFSET
Adj
WLALM(Target Temperature ALM)
Selecter
TEMPIN
ADC
HEATP
T-V
Conv.
PID
WAVE1
OSC
PWM
COOLP
or
Current
direction
COOLN
control
HEATN
TEC
WAVE0
SHUT_APCN
SHUT_ATCN
MODE
STATUS
Digital I/F
Monitor
DAC
IOUT4H
I-DAC4
Curret
Amp/
Bypass
IOUT4C
CSN
SKN
DI
<Rev. 0.6E Preliminary>
DO
READY
REG
EEP
AMON
-2-
2001/11
AKM Confidential
AK2571
Circuit Description
1. Over view
The AK2571 has two primary functions. The first function is APC (Automatic Temperature Control) which supplies
adequate modulation /BIAS current to a Laser diode and the other is ATC (Automatic Temperature control) which
controls the TEC (Thermo Electric Cooler) to stabilize the temperature of the Laser diode.
1. 1 APC
There are three Digital to Analog Converters (I-DAC1, 2, 3) that output the current for modulation, BIAS and EA
(Electrical Absorption) Modulation.
Maximum output currents :
I-DAC1: 120mA (typ.),
I-DAC2 and I-DAC3: 20mA (typ.)
Each DAC has a current limit function whose value is stored in the internal EEPROM. This is especially important for
I-DAC1, which has the modulation function for dithering.
In WDM systems, there is no need for discrete laser diode temperature compensation. However the outer current
amplifier or LD drivers may be affected by ambient temperature changes. In order to compensate for these the AK2571
has a feed-forward APC that can supply adequate current corresponding to the ambient temperature change detected by
the internal T_V converter.
Please refer the part “3. APC” for details.
1.2 ATC
The AK2571 controls TEC to stabilize the input voltage from the temperature sensor of the LD module (Thermistor). The
control algorithm is PID (Proportion Integration Differential) which has user-programmable parameters that are stored in
EEPROM. There are two ways for driving TEC, one is PWM (more energy effective than DC drive), the other is DC
current drive through I-DAC, which has lower noise.
Please refer the part “4. ATC” for details.
1.3 Control Sequence
There are three functional modes in AK2571 below.
1) Self-operation mode: The AK2571 operates ATC and APC independently. When self-operating mode starts, , ATC Lock
(detects when the target temperature is reached), APC Count up (prevents jumps in BIAS and Modulation currents) and
Timer (counts the time from device start to beginning of operation) are available.
2) Register Access Mode: AK2571 permits writing registers through the digital interface. Customers can adjust any
parameters or tables in this mode.
3) EEPROM mode: AK2571 permits EEPROM writes. Customers can store the parameters or table data in EEPROM.
Please refer the part “5. Sequencer” for details.
<Rev. 0.6E Preliminary>
-3-
2001/11
AKM Confidential
AK2571
2. Reference
2.1 Definition
All values are expressed in the order shown below
Tab_(Function Block_)Main name(Function_).Sub name[Bit]
Setting way
Tab
Main name
Sub name
Register
R
REGISTER NAME Sub register name
(Capital letter)
Bits
Example
[x,x]
R_PDGAIN
R_DAC_SET.Dac1
R_DAC_SET[2:0]
EEPROM
E
PIN
P
EEPROM
NAME Sub eeprom name
(Capital letter)
PIN NAME (Capital
letter)
[x,x]
E_PDGAIN
E_DAC_SET.Dac1
P_WAVE0
Register and EEPROM names may include additional tags as described below
Classify
Additional Tag
Contents
Example
Function Block
APC
APC relate
E_APC_FF_SET
DAC
I-DAC relate
E_DAC1_FIX
ATC
ATC relate
E_ATC_OFFSET
ALM
Alarm relate
E_ALM_POL
PID
PID relate
E_PID_P
LK
ATC Lock counter relate
E_LK_CNT_SET
TMPRT
Temperature decode value
R_TMPRT_TRNT
SET
Settled value (ALM or Counter etc.)
E_DAC1_SET
WIN
Hysteresis (ALM or counter etc.)
E_TMPRTALM_WIN
CTRL
Hysteresis (ALM or counter etc.)
E_INI_CTRL_USR
FIX
Fixed data for APC
E_DAC1_FIX
TV
APC compensation data
E_DAC1_TV
CMPNST
LD aging compensation data
R_APC_CMPNST
TRGT
Target value (Temperature or Voltage etc.)
E_APC_TRGT
CRNT
Current value
R_TMPRT_CRNT
BFR
Before value
R_TMPRT_BFR
Function
<Rev. 0.6E Preliminary>
-4-
2001/11
AKM Confidential
AK2571
All circuit blocks and internal nodes are noted as below
Circuit Block
Main name
Example
BLOCK NAME (Capital letter)
I-DAC1
PID
Internal Node
Signal name (Small letter)
vout
2.2 Functional explanation
Some values are stored in both register and EEPROM to simplify user programming. Explanations of these values are in
the register description tables.
For EEPROM details, refer to Section 7. EEPROM
For Register details, refer to Section 8. Registers
3. APC (Automatic Power Control)
APC set
(E__APC_FF_SET)
T-V_
CONV
ADC*
EA_MOD ON/OFF(R_EA_SW)
Frequency(R_EA_FREQ)
Gain(R_EA_GAIN)
I-DAC1～3 ON/
LD Ageing
compensation OFF(R__DAC_SET[2:0])
I-DAC1 Gain set
ON/OFF
(R_DAC1_GAIN)
(E__APC_FB_SET)
EA_MOD
R_DAC1
EEPROM
I-DAC1
ADDER
I-DAC2
PDMON Digital value
(R_PDMOND)
ADC*
R_DAC3
PD_MON Target
(R_PDMON_SET)
PDMON
IOUT1
I-DAC2 Gain set
(R_DAC2_GAIN)
* Time shearing ADC
R_DAC2
+
IOUT2
I-DAC3 Gain set
(R_DAC3_GAIN)
I-DAC3
IOUT3
LD Ageing
compensation current
(R_APC_CMPNST)
PDMON
set
ALM polarity set
(R_ALM_POL)
PD GAIN set
(R_PDGAIN)
Monitor
PD
PD voltage after
PDGAIN
(vpd)
OPALM_
COMP
APC_
COMP
DIGITAL
FILTER
OPALM
PDIN
CPD
PDGAIN
RPD
vapc_ref
APC Target
(R_APC_TRGT)
<Rev. 0.6E Preliminary>
DAC_APC
LD ageing compensation
current limit value
OPALM_
(E_APC_FB_MAX)
GAIN
vopalm_ref
Current ALM set
(E_CUALM_SET)
Optical out down
threshold(R_OPALM_SET)
-5-
ALM polarity
set
(R_ALM_POL)
CUALM_
COMP
CUALM
2001/11
AKM Confidential
AK2571
3.1 Functional description
Block
Function
T_V CONV
ADC
EEPROM
ADDER
I-DAC1
I-DAC2
I-DAC3
EA_MOD
PDGAIN
DACAPC
Note
Internal Temperature Sensor. Outputs a voltage that corresponds to the surface temperature
of the AK2571. This function controls temperature compensation of an external current
amplifier, driver IC, etc. By activating the E_APC_FF_SET (=1), the ADC outputs the digital
data of T_V CONV as the address of EEPROM stores the lookup table of temperature
compensation data for external components every 5.6degree. This data is output through
I-DAC and supplies the Laser Diode modulation and BIAS currents. If this function is not
required set E_APC_FF_SET to a fixed value and set the current value in E_DACx_FIX.
8-bits A-to-D converter for temperature detection. (5-bit MSB is used for temperature
compensation)
E_APC_FF_SET=0 (Default): APC is not activated. Fixed data (E_DACx_FIX, x=1-3) is sent
to I-DACs.
E_APC_FF_SET=1: APC activation. 5-bits MSB of ADC sent to E_DACxTV[A/D], x=1-3
and work the APC sequence.
E_APC__FB_SET.Dacx(x=1-3)=0 (default): Do not add aging compensation current to
I-DACs.
E_APC_FB_SET.Dacx(x=1-3)=1: Add aging compensation (R_APC_CMPNST) current to
I-DACs.
8-bit current output DAC (120mA max.). Output current corresponds to R_DAC1 data.
When R_DAC_SET=1, this outputs is enabled.
8-bit current output DAC (20mA max.). Output current corresponding to R_DAC1 data.
When R_DAC_SET=1, this outputs is enabled.
8 bit current output DAC (20mA max.). Output current corresponding to R_DAC1 data.
When R_DAC_SET=1, this outputs is enabled.
Dithering function. R_EA_SW=0: Non-Active/ 1: Active. R_EA_FREQ: Modulation
frequency selection: 16kHz(000), 32kHz(001), 64kHz(010), 128kHz(011) and 256kHz(100).
R_EA_GAIN: Additional level to I=DAC1 out selection:16%(00), 8%(01), 10.4%(10) and
2%(11).
Amplifies the input signal from the monitoring Photo Diode. (vpd).
Customers can set the gain from 0dB to 21dB(Typ.) by 0.7dB steps, using values stored in the
EEPROM.
Input range: 0.2V - 1.5V
Full-scale output through PDMON can be set from 0.4V to1.1V in 0.1V steps. Internal
attenuator adjusts the full scale per E_PDMON_SET..
Generates the target APC (R_APC_TRGT) voltage (vact_ref) in proportion to PDGAIN.
APC_COMP
Compares the PD monitoring voltage (vpd) with APC target voltage (vapc_ref), if vpd <
vapc_ref, outputs UP signals to digital filter. And if vpd > vapc_ref, outputs DOWN signals to
digital filter. The sampling rate is 512kHz.
DIGITAL
Receives signals from APC_COMP, calculates the value to make vpd and vapc_ref equal. Its
FILTER
value is the LD aging error (R_APC_CMPNST), and is limited by the value of
E_APC_FB_MAX. There is no need to supply negative current for aging error.
CUALM_COMP LD aging error current (R_APC_CMPNST) over Alarm value (E_CUALM_SET), output
CUALM. Its polarity is selected by register R_ALM_POL.
OPALM_GAIN OPALM (light sparkle fail) output level (vopalm_ref) setting by register R_OPALM_SET.
000: 1/2, 001: 1/3, 010: 1/4, 011: 1/5, 100: 1/6, 101:1/8
OPALM_COMP Compares the PD monitoring voltage (vpd) with OPALM voltage (vpalm), if vpd < vpalm,
outputs OPALM (light power down alarm). Its polarity is selected by register R_ALM_POL.
<Rev. 0.6E Preliminary>
-6-
2001/11
AKM Confidential
AK2571
3.2 Feed forward APC Function
The AK2571 compensates for ambient temperature variations caused by the current amplifier or driver chip located
outside of the LD module. If this function is not required, a fixed-current source for the LD can be used instead..
The Feed-forward process is described below:
1) The internal T_V converter (please refer to “3.6 Internal T-V converter”) senses the ambient temperature. The
integrated ADC converts the signal to a digital value.
2) 5-bit MSB data address for the EEPROM stores the temperature compensation data, which is sent to I-DACx.
3) Compensation current is output from I-DACx.
To execute feed forward APC, temperature compensation data must be stored in the internal EEPROM as a look-up table
that is programmed during the customer assembly process.
In Self-operation mode, all compensation operations (sensing T_V converter, access to EEPROM and compensation
current output through I-DACs) are automatically executed.
3.3 LD aging error compensation
Compensation current outputs are available for LD light power deterioration. APC_COMP compares the feedback voltage
from PDIN (vpd) with the output voltage of DACAPC (vapc_ref, R_APC_TRGT). Based on this result a compensation
current (R_APC_CMPNST) is added to the output current of I-DAC set by E_APC_FB_SET after averaging through a
digital filter.
PDMON Digital
(R_PDMOND)
ADC*
*: Time shearing ADC
PD_MON Target
(R_PDMON_SET)
PDMON
PDMON
set
Monitor
PD
PD voltage after
PDGAIN
(vpd)
APC_
COMP
PDIN
CPD
PDGAIN
RPD
PD GAIN set
(R_PDGAIN)
APC Target
(R_APC_TRGT)
3.3.1
LD Ageing compensation
Max value
(E_APC_FB_MAX)
LD Ageing error
compensation current
(R_APC_CMPNST)
DIGITAL
FILTER
vapc_ref
DAC_APC
PDMON / PDGAIN setting
Selects the output range from PDMON pin by R_PDMON_SET in the range from0.4 to 1.1V. Adjust the input signal level
using R_PD_GAIN (E_PD_GAIN) to make the initial input level equal the value of R_PDMON_SET. Table 3-2 indicates
the function of R_PDMON_SET and output voltages, Table 3-3 indicates the function of R_PDGAIN and Gain. After this
adjustment, the internal PD input voltage (vpd) is set at 1.8V(typ) in Self-operation mode.
<Rev. 0.6E Preliminary>
-7-
2001/11
AKM Confidential
AK2571
Table 3-2 R_PDMON_SET setting
R_PDMON_SET (E_PDMON_SET)[2:0]
PDMON Full Scale
111
1.1V
-
0.1V / step
000
0.4V
Table 3-3 R_PDGAIN setting
R_PDGAIN_SET (E_PDGAIN_SET)[4:0]
Gain
11111
21.7dB
-
0.7dB / step
00000
0dB
Make sure the PDMON voltage equals the value of R(E)_PDMON_SET.
Conversion expression: Gain = 20*log (1.8 / PDIN voltage)
3.3.2
DACAPC
Generates the reference voltage for aging compensation. Table 3-4 indicates the function of R(E)_APC_TRGT and vapc_ref
R_APC_TRGT (E_APC_TRGT)[6:0]
Reference voltage for Aging compensation (vapc_ref)
1111111
2.1V
|
4.8mV / step
0000000
1.5V
Refer to “5.3.1 Process - ATC and APC Adjustment Example” for further instructions regarding the adjustment process, .
<Rev. 0.6E Preliminary>
-8-
2001/11
AKM Confidential
AK2571
3.4 Gain setting of I-DAC1,2,3
See the table below for a description on how to set the three I-DACs full-scale voltages. The resolution is set in proportion
with the gain.
I-DAC1 gain setting
R_DAC1_GAIN
(E_DAC1_GAIN)
Gain set value Max
output Setting range of Non missing code Current
current (typ)
output current (typ) warranty range (typ) resolution (typ)
00
1
121.8mA
30mA-121.8mA
30mA over
0.36mA
01
1/2
60.9mA
15mA-60.9mA
15mA over
0.18mA
10
1/4
30.45mA
7.5mA-30.45mA
7.5mA over
0.09mA
11
1/12
10.15mA
2.5mA-10.15mA
2.5mA over
0.03mA
I-DAC2 Gain setting
R_DAC1_GAIN
Gain set value
Max
output Setting range of Non missing code Current
current (typ)
output current (typ) warranty range (typ) resolution (typ)
00(11)
1
20.42mA
0mA-21.42mA
2.5mA over
0.084mA
10
1/2
10.71mA
0mA-10.71mA
1.25mA over
0.042mA
11
1/4
5.36mA
0mA-5.36mA
0.625mA over
0.021mA
(E_DAC1_GAIN)
I-DAC3 Gain setting
R_DAC1_GAIN
(E_DAC1_GAIN)
Gain set value Max
output Setting range of Non missing code Current
current (typ)
output current (typ) warranty range (typ) resolution (typ)
00(11)
1
21.42mA
0mA-20.42mA
2.5mA over
0.084mA
10
1/2
10.71mA
0mA-10.71mA
1.25mA over
0.042mA
11
1/4
5.36mA
0mA-5.36mA
0.625mA over
0.021mA
<Rev. 0.6E Preliminary>
-9-
2001/11
AKM Confidential
AK2571
3.5 Modulation for dithering through I-DAC1
I-DAC1 has a modulation function for dithering. It’s added to the current of I-DAC1 and output through IOUT1. Its
function is available to set R_EA_SW.
Figure 3-3 shows the block diagram and Table 3-8 / 3-9 explains the setting
Figure 3-3 EA Block diagram
EA frequency
set
(R_EA_FREQ)
EA gain set
(R_EA_GAIN)
GAIN
I-DAC1
+
IOUT1
Table 3-8 EA Dithering frequency
R_EA_FREQ
Setting frequency (Typ)
Deviation (typ)
Remarks
000
16kHz
TBD
(Default)
001
32kHz
TBD
010
64kHz
TBD
011
128kHz
TBD
100-111
256kHz
TBD
Additional gain
Deviation (typ)
Remarks
00
16%
TBD
(Default)
01
8%
TBD
10
4%
TBD
11
2%
TBD
(E_EA_FREQ)
Table 3-9 Additional gain
R_EA_GAIN
(E_EA_GAIN)
<Rev. 0.6E Preliminary>
-10-
2001/11
AKM Confidential
AK2571
3.6 Internal T_V converter
The internal temperature sensor’s output voltage function is shown in Figure 3-4. This offset is different for each device,
and is adjusted during factory test by AKM. If re-adjustment of the offset is necessary (for higher accuracy, etc.), it is
possible to rewrite the R(E)_TV_OFFSET. Table 3-10 diagrams the offset voltage and R_TV_OFFSET. The internal T_V
converter has a gain of –12.3mV / degree (typ) and the 8-bit ADC (full scale is 2.2V) is changed 0.7degree for each LSB.
Actually, only 5bits MSB of ADC is valid for feed forward APC, so the compensation data is renewed every 5.6 degrees.
The internal T_V converter monitors the surface temperature of the AK2571 and detects any difference between this
temperature, the ambient temperature and the temperature of external components. It is possible to increase the accuracy
of this function by “training” the device beforehand and writing the compensation data trained as described below.
1) Single-point temperature adjustment
Read R_TV at one ambient temperature, and using the T_V Conv. Gain (-0.7degree/LSB), calculates the 8-bit ADC value
and enter it into the look-up table address for Feed forward APC.
By performing this training, the offset error can be cancelled. Of course this training must be executed in conjunction with
an APC adjustment. Please refer to 5.3.1 APC/ATC adjustment.
2) Two-point temperature adjustment
Read R_TV at two ambient temperatures, calculate the T_V Conversion gain. From this gain, calculate the 8-bit ADC
value and enter it into the look-up table address for Feed forward APC.
By performing this training, the offset error and gain variation can be cancelled. Of course this training must be executed in
conjunction with an APC adjustment. Please refer to 5.3.1 APC/ATC adjustment.
Figure 3-4 Internal Temperature Sensor
InternalTem perature S ensor(T_V _C O N V ) (Typ characteristics)
2.2
2.0
Output voltage [
1.8
1.6
1.4
1.2
S hifed by offset adjustm ent
1.0
V = -0.0123t + 1.5709
0.8
0.6
0.4
0.2
0.0
-40
<Rev. 0.6E Preliminary>
0
40
Tem perature t [℃]
80
-11-
120
2001/11
AKM Confidential
AK2571
Table 3-10 R_TV_OFFSET setting
R_TV_OFFSET[4:0]
Offset voltage [mV]
E_TV_OFFSET[4:0]
(Reference value)
11111
+375
11110
+350
11101
+325
|
|
10001
+25
10000
0
01111
-25
|
|
00010
-350
00001
-375
00000
-400
Default value of E_TV_OFFSET is set by AKM.
3.7 Example schematics of connect ion to external components
Figures 3-5 to 3-10 illustrate typical system connections. When connecting to a negative voltage source, use a level shifter to
ensure that the signal voltages stays within the specified range.. In addition to that, I-DAC1 can’t be forced negative voltage
supply.
<Rev. 0.6E Preliminary>
-12-
2001/11
AKM Confidential
AK2571
Figure 3-5
Direct Modulation with Positive Power Supply
Figure-3-6
Direct Modulation with Negative Power Supply
LD-A
AK2571
LD
I-DAC2
LD Module
LD
IOUT2
AK2571
DC
IOUT1
I-DAC1
I-DAC3
IOUT2
I-DAC2
IOUT3
RF
VEE
Driver circuit
Driver Circuit
VEE
Figure 3-7
Direct Modulation with Voltage Controlled LD Driver
Figure 3-8
Direct Modulation with Voltage Controlled LD Driver
LD module
LD-A
LD
AK2571
I-DAC2
AK2571
I-DAC1
DC
BIAS
Current setting
Voltage
IOUT1
IOUT2
I-DAC3
Modulation
Current setting
Voltage
RF
BIAS
current set
voltage
VEE
Driner LSI
I-DAC2
LD
IOUT2
IOUT3
Driver circuit
Modulation
current set
voltage
VEE
Figure 3-9
EA Modulation
Figure 3-10
EA with Voltage Controlled LD Drive
AK2571
AK2571
I-DAC1
IOUT1
I-DAC1
IOUT1
LD module with
EA modulator
LD-A
LD-A
LD module with
EA modulator
LD
LD
EA
I-DAC2
IOUT2
I-DAC2
IOUT2
EA
EA-A
EA-A
VEE
VEE
I-DAC3
IOUT3
I-DAC3
Driver Circuit
EA BIAS
current set
voltage
IOUT3
Driner circuit
for EA
modulation
EA Modulation
current set
voltage
VEE
VEE
<Rev. 0.6E Preliminary>
-13-
2001/11
AKM Confidential
AK2571
4. ATC (Automatic Temperature Compensation)
Figure 4-1 ATC Block diagram
ALM polarity
(R_ALM_POL)
Temperature alarm
threshold
(E_TMPRTALM_WIN)
Detect term set
(E_LK_CNT_SET)
ATC_
LOCK
REFOUT
Regulator
Rth
vtemp
TEMPIN
RL
Gain &
Offset
ALM polarity
PID ALM (R_ALM_POL)
threshold
PIDALM
(E_PIDALM_SET)
COMP
TEMPALM
COMP
ATC_LOCK set
(E_LK_TMPRT_WIN)
ADC
Non sensed
TEC control way
value(E_PID_INACT)
(E_TEC_CTRL_SET)
PID max value(E_PID_MAX) (E_TEC_ANALOG) PWM devision
PID parameter
(R_TEC_PWM_SET)
(E_PID_P,E_PID_I,E_PID_D)
HEATP
Temperature data
(R_TMPRT_CRNT)
Initial temperature
OFFSET voltage
Target
(R_ATC_OFFSET)
(E_ATC_TRGT)
Parameter of ATC
feed back
(E_ATC_FB_SET)
LD ageing error
current
ATC_FB
(R_APC_CMPNST)
-
PIDALM
TEMPALM
PID
PID control
(R_PID_VALABS)
Temperature Target
(R_TMPRT__TRGT)
TEC_
CTRL
TECcontrol way
(E_TEC_CTRL_SET, E_TEC_ANALOG)
ATC Feed back Alarm
(E_WLALM_SET)
I-DAC4H
WLALM
COMP
COOLN
HEATN
ATC feed back
(R_ATC_CMPNST)
ALM polarity
(R_ALM_POL)
COOLP
TEC
control
IOUT4H
TECcontrol way
(E_TEC_CTRL_SET, E_TEC_ANALOG)
I-DAC4C
IOUT4C
WLALM
<Rev. 0.6E Preliminary>
-14-
2001/11
AKM Confidential
AK2571
4.1 ATC Block Explanation
Table 4-1 indicates the functions of the ATC block
Block
Function
Regulator
Supplies voltage to thermister included in the LD module. REFOUT=2.3V (typ). Thermister output
voltage (TEMPIN) error tracks the varying voltage supply temperature characteristics of REFOUT and
automatically calculates and cancels this in the AK2571.
Gain & Offset
AK2571 amplifies (x13 typically) the input signal to enable higher resolution from the 8-bit ADC. The input
signal should be set to the midpoint of its full scale to meet the target temperature of the offset setting
function. For example, when thermister R0=10kohm.@25 degree, B=3900, load resistance 6.8kohm., its
sensitivity is about 0.03degree/LSB.
ADC
8b-it A-to-D converter. Reference voltage is 2.2V (typ). Temperature signal from Gain & OFFSET is
converted to digital and transferred to PID calculator.
PID
Executes a PID (Proportion, Integration and differential) calculation to meet the temperature signal
(R_TMPRT_CRNT) at the target temperature (R_TMPRT_TRGT). Output data (R_PID_VALABS) is
composed of 13-bits absolute value and a positive/negative bit. Each PID parameter can be set in the
EEPROM. The cycle time for this calculation is 8mS (typ) and is set by the internal oscillator.
TEC_CTRL
Using the PID data (R_PID_VALABS), the TEC (Thermo Electric Cooler) is controlled by PWM or
Analog control. When PWM control is selected, the FET switch is controlled through the PWM division set
register (R_TEC_PWM_SET).
I-DAC4H
10b-it current D-to-A converter. When analog control for TEC is selected, the IDAC outputs current
following 10bits MSB data from PID. Its full-scale output current is 50mA (typ). When Analog-1 is selected
(Control the current direction by FET: refer to figure 4-4), it is possible for I-DAC4H to output both cooling
and heating current, depending on current direction. On the other hand, when Analog-2 is selected,
heating current is output through I-DAC4H (I-DAC4C output is GND) and cooling current is output
through I-DAC4C (I-DAC4H output is GND).
I-DAC4C
Remarks
ATC_FB
Change the target temperature according to LD aging error from PD monitor voltage. Its value
(R_ATC_CMPNST) is calculated from the parameter (E_ATC_FB_SET). This function assumes that
there is first order function between the LD aging error and moving the wavelength to the longer, can
compensate wavelength shift cause from aging. When use this function, please note this assumption
carefully.
ATC_LOCK
Detect the stabilization of LD temperature from start or reset of AK2571. The stabilization judge range
(E_LK_TMPRT_WIN) and its decision term (E_LK_CNT_SET) are set in EEPROM. If the LD
temperature data (R_TMPRT_CRNT) stays within the stabilization judge range for a period that is longer
than the decision term, the AK2571 moves to the next operation.
TEMPALMCOMP If the difference between LD temperature data (R_TMPRT_CRNT) and target temperature
(R_TMPRT_TRGT) exceeds the temperature alarm threshold (E_TEMPALM_WIN), TEMPALM is
triggered. RegisterI R_ALM_POL sets the polarity of this signal.
PIDALMCOMP
When the PID control value (R_PID_VALUE) exceeds the PID alarm threshold (E_PIDALM_SET), PID
alarm is triggered. RegisterI R_ALM_POL sets the polarity of this signal
WLALMCOMP
When the aging target temperature aging (R_ATC_CMPNST) is exceeds the threshold of the wavelength
aging error alarm (E_WLALM_SET), WLALM is output. Its polarity is selectable by the R_ALM_POL
register.
<Rev. 0.6E Preliminary>
-15-
2001/11
AKM Confidential
AK2571
4.2 PID control
Figure 4-2 explains the block diagram for PID control and table 4-3 indicates the parameter setting range
Figure 4-2 PID control
E_PID_P
Target temperature
(R_TMPRT_TRGT)
+
E_PID_D
Temperature data
(R_TMPRT_CRNT)
-
PID control value
(R_PID_VALABS)
Proportion
Parameter
(P)
+
E_PID_I
Differencial
Parameter
(D)
PID integration
value
(R_PID_INTGRL)
Integration
Parameter
(I)
Σ
Z -1
Table 4-3: PID parameter setting range
Parameter
EEPROM
Min.
Default
Max.
Proportion
E_PID_P
0
8
255
Integration
E_PID_I
0
7/256
255/256
Differential
E_PID_D
0
6/256
255/256
<Rev. 0.6E Preliminary>
-16-
2001/11
AKM Confidential
AK2571
4.3 TEC control
The TEC control process is illustrated in table 4-4. Figures 4-3 to 4-6 explain the circuit that drives TEC and table 4-5
indicate the pin strapping for different control modes.
Figure 4-3 PWM control
Figure 4-5 Analog control 2-1
AK2571
HEATP
AK2571
COOLP
Curreny
direction
control
COOLN
PID
HEATP
TEC
TEC
HEATN
COOLP
PID
PWM
COOLN
I-DAC4
IOUT4
IOUT4B
HEATN
Figure 4-4 Analog control-1
Figure 4-6 Analog control 2-2
AK2571
HEATP
TEC
COOLP
Current
direction
control
COOLN
PID
AK2571
HEATP
HEATN
COOLP
Currnt
direction
control
COOLN
PID
TEC
HEATN
I-DAC4C
IOUT4C
I-DAC4C
IOUT4H
I-DAC4H
IOUT4C
Current
amp
Table 4-5 pin status
PID data TEC
PID=0
OFF
PID>0
Heating
PID<0
Cooling
Control way
PWM
Analog-1
Analog-2
PWM
Analog-1
Analog-2
PWM
Analog-1
Analog-2
<Rev. 0.6E Preliminary>
IOUT4H
GND
GND
GND
GND
Current out
Current out
GND
Current out
GND
I-DAC4H
IOUT4C
GND
GND
GND
GND
GND
GND
GND
GND
Current out
-17-
HEAT_P
1
1
1
0
0
0
1
1
1
IOUT4H
HEAT_N
0
0
0
PWM
1
0
0
0
0
COOL_P
1
1
1
1
1
1
0
0
0
COOL_N
0
0
0
0
0
0
PWM
1
0
2001/11
AKM Confidential
AK2571
Figure 4-7 PWM division
Case-1
PID control value(R_PID_VALABS) = 2020
PWM division = 32
64*4 + 63*28 = 2020
8192/32=256
TS#1
64
TS#2
TS#3
64
64
TS#4
TS#5
64
TS#6
63
TS#32
63
63
Operation cycle (8ms typ)
Resolution=8192
Minimum pulse width = 8ms/8192
≅ 1us
63
1us
64
256
Case-2
PID control value(R_PID_VALABS) = 2020
PWM division = 64
32*36 + 31*28 = 2020
8192/16=128
TS#1
32
TS#2
32
TS#3
TS#4
TS#5
TS#6
TS#7
TS#8
TS#9
32
32
32
32
32
32
32
TS#61
31
TS#62 TS#63
31
31
TS#64
31
Operation cycle (8ms typ)
4.4 Gain & Offset
The AK2571 amplifies (typically x13) the input signal from the thermister to provide higher resolution for the 8-bit ADC. It
also adds an offset voltage to meet the middle of full scale at target temperature. Table 4-6 indicates temperature levels
that correspond to ADC values when using a thermister R0=10kohm@25degree, B=3900 and Table 4-7 indicates a
thermister R0=10kohm@25degree, B=3450. Both load resistances RL) are 6.8kohm, REFOUT is 2.3V. When adjusting
Offset voltage (R_ATC_OFFSET), target temperature must be a value between 96 (60h) and 160 (A0h).
<Rev. 0.6E Preliminary>
-18-
2001/11
AKM Confidential
AK2571
Table 4-6 Temperature corresponding to code of ADC (Thermister: R0=10kohm@25degree,B=3900)
R_ATC_OFFSET Offset voltage Temperature [degree] (typ)
[V]
ADC=0
ADC=96
ADC=128
ADC=160
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
<Rev. 0.6E Preliminary>
0.30
0.33
0.36
0.39
0.42
0.45
0.48
0.51
0.54
0.57
0.60
0.63
0.66
0.69
0.72
0.75
0.78
0.81
0.84
0.87
0.90
0.93
0.96
0.99
1.02
1.05
1.08
1.11
1.14
1.16
1.19
1.22
1.25
1.28
1.31
1.34
1.37
1.40
1.43
1.46
1.49
1.52
1.55
1.58
1.61
1.64
1.67
1.70
-7.6
-5.6
-3.8
-2.0
-0.3
1.3
2.8
4.3
5.7
7.1
8.5
9.8
11.1
12.4
13.6
14.8
16.0
17.2
18.4
19.6
20.7
21.9
23.0
24.1
25.3
26.4
27.5
28.7
29.8
30.9
32.1
33.2
34.4
35.6
36.7
37.9
39.1
40.3
41.6
42.8
44.1
45.4
46.7
48.1
49.5
50.9
52.3
53.8
-3.2
-1.5
0.2
1.8
3.3
4.7
6.2
7.5
8.9
10.2
11.5
12.7
14.0
15.2
16.4
17.6
18.8
19.9
21.1
22.2
23.4
24.5
25.6
26.8
27.9
29.0
30.2
31.3
32.4
33.6
34.7
35.9
37.1
38.3
39.5
40.7
42.0
43.2
44.5
45.8
47.2
48.5
49.9
51.3
52.8
54.3
55.9
57.5
-19-
-1.9
-0.2
1.4
2.9
4.4
5.8
7.2
8.6
9.9
11.2
12.5
13.7
14.9
16.1
17.3
18.5
19.6
20.8
21.9
23.1
24.2
25.4
26.5
27.6
28.8
29.9
31.0
32.2
33.3
34.5
35.6
36.8
38.0
39.2
40.4
41.7
42.9
44.2
45.5
46.8
48.2
49.6
51.0
52.5
54.0
55.5
57.1
58.7
ADC=256
-0.6
1.0
2.6
4.1
5.5
6.9
8.3
9.6
10.9
12.2
13.4
14.6
15.8
17.0
18.2
19.4
20.5
21.7
22.8
24.0
25.1
26.2
27.4
28.5
29.6
30.8
31.9
33.1
34.2
35.4
36.6
37.7
38.9
40.2
41.4
42.6
43.9
45.2
46.5
47.9
49.3
50.7
52.1
53.6
55.1
56.7
58.4
60.1
3.0
4.5
5.9
7.3
8.7
10.0
11.3
12.5
13.8
15.0
16.2
17.4
18.5
19.7
20.9
22.0
23.2
24.3
25.4
26.6
27.7
28.8
30.0
31.1
32.2
33.4
34.5
35.7
36.9
38.1
39.3
40.5
41.7
43.0
44.3
45.6
46.9
48.3
49.7
51.1
52.5
54.0
55.6
57.2
58.8
60.6
62.3
64.2
2001/11
AKM Confidential
AK2571
Table 4-6 Temperature levels corresponding to ADC values (Thermister: R0=10kohm@25degree,B=3450)
R_ATC_OFFSET Offset voltage Temperature [degree] (typ)
[V]
ADC=0
ADC=96
ADC=128
ADC=160
ADC=256
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
<Rev. 0.6E Preliminary>
0.30
0.33
0.36
0.39
0.42
0.45
0.48
0.51
0.54
0.57
0.60
0.63
0.66
0.69
0.72
0.75
0.78
0.81
0.84
0.87
0.90
0.93
0.96
0.99
1.02
1.05
1.08
1.11
1.14
1.16
1.19
1.22
1.25
1.28
1.31
1.34
1.37
1.40
1.43
1.46
1.49
1.52
1.55
1.58
1.61
1.64
1.67
1.70
-11.3
-9.2
-7.1
-5.2
-3.3
-1.5
0.2
1.8
3.4
4.9
6.5
7.9
9.4
10.8
12.2
13.5
14.9
16.2
17.5
18.9
20.2
21.5
22.7
24.0
25.3
26.6
27.9
29.1
30.4
31.7
33.0
34.3
35.7
37.0
38.3
39.7
41.1
42.5
43.9
45.3
46.8
48.3
49.8
51.4
53.0
54.6
56.3
58.0
-6.3
-4.4
-2.6
-0.8
0.9
2.5
4.0
5.6
7.1
8.5
10.0
11.4
12.7
14.1
15.4
16.8
18.1
19.4
20.7
22.0
23.3
24.6
25.8
27.1
28.4
29.7
31.0
32.3
33.6
34.9
36.2
37.5
38.9
40.3
41.6
43.0
44.5
45.9
47.4
48.9
50.4
52.0
53.6
55.3
57.0
58.8
60.6
62.4
-20-
-4.7
-2.9
-1.2
0.5
2.2
3.7
5.3
6.8
8.2
9.7
11.1
12.5
13.8
15.2
16.5
17.8
19.1
20.4
21.7
23.0
24.3
25.6
26.9
28.1
29.4
30.7
32.0
33.3
34.6
35.9
37.3
38.6
40.0
41.4
42.8
44.2
45.6
47.1
48.6
50.1
51.7
53.3
55.0
56.7
58.4
60.2
62.1
64.0
-3.3
-1.5
0.2
1.8
3.4
5.0
6.5
8.0
9.4
10.8
12.2
13.6
14.9
16.3
17.6
18.9
20.2
21.5
22.8
24.1
25.3
26.6
27.9
29.2
30.5
31.8
33.1
34.4
35.7
37.0
38.4
39.7
41.1
42.5
43.9
45.4
46.8
48.3
49.8
51.4
53.0
54.6
56.3
58.1
59.9
61.7
63.6
65.6
0.9
2.5
4.0
5.6
7.1
8.5
10.0
11.4
12.7
14.1
15.4
16.8
18.1
19.4
20.7
22.0
23.3
24.6
25.8
27.1
28.4
29.7
31.0
32.3
33.6
34.9
36.2
37.5
38.9
40.3
41.6
43.0
44.5
45.9
47.4
48.9
50.4
52.0
53.6
55.3
57.0
58.8
60.6
62.4
64.4
66.4
68.5
70.7
2001/11
AKM Confidential
AK2571
4.5 ATC Feedback function
The ATC Feedback function compensates for wavelength shifts caused by aging. R_CTRL_USER.Atc_fb = “1” enables the
function, “0” disables it. Turning on this function changes the target temperature according to LD aging error from the PD
monitor voltage. Its value (R_ATC_CMPNST) is calculated from (E_ATC_FB_SET). This function assumes that there is a
first order function between the LD aging error and wavelength increases and uses this function to compensate for this
shift caused by aging. When using this function, please note this assumption carefully. Figure 4-8 indicates the block
diagram for this function.
Figure 4-8 ATC Feedback Block
Initial current set
Iini
+
LD ageing current
(R_APC_CMPNST)
I-DAC
current step
(ΔIstep)
Parameter
Kc
I-DAC output
current
Iidac
LD set current
Ild
External
current amp
LD module
Gi (e.g. G=4)
Target temperature
shift value
(R_ATC_CMPNST)
Temperature shift step
ΔTstep = 0.03℃ (typ)
Set by E_ATC_FB_SET
Initial Target
PID control
Temperature set value
Target
temperature
(E_ATC_TRGT)
(R_TMPRT_TRGT)
Function of wavelength and
ageing current: Kw
e.g. Kw = 0.01nm/mA
Function of wavelength and
temperature: Kt
e.g. Kt = -0.1nm/℃
Its operation is described below
1) With LD aging error engaged, initiate the APC compensation circuit. LD compensation current (Digital) is added to
the I-DACs selected by R_APC_CMPNST.
2) Calculate the shift value of the target temperature (R_ATC_CMPNST) from the compensation current and the
parameter stored in E_ATC_FB_SET (=Kc).
3) Shift the target temperature (R_TMPRT_TARGET) which is the initial target temperature (E_ATC_TRGT) minus
the shift value of target temperature (R_ATC_CMPNST).
Kc as above is calculated by the expression below.
If the shift value of wavelength is ∆λ1, Compensation current (Analog) is ∆Ild,
∆λ1= Kw*∆Ild
(1)
If the rate of analog output current per one step of I-DACs is ∆Istep, the gain of external current amplifier is Gi,
The value of compensation current (Digital)
R_APC_CMPNST = ∆Ild / Gi / ∆Istep
(2)
The shift value of target temperature
R_ATC_CMPNST = Kc*R_APC_CMPNST
(3)
If the rate of temperature shift per one step of R_ATC_CMPNST is ∆Tstep, the value of wavelength shift by the shift of
target temperature is ∆λ2,
∆λ2=Kt*R_ATC_CMPNST*∆Tstep
(4)
In that sense the value of Kc to make ∆λ1=∆λ2, for compensation of the wavelength shift.
Kc=Kw*Gi / Kt* ∆Istep / ∆Tstep
(5)
For example: If Kw=0.01nm/mA, Gi=4, Kt=0.1nm/°C, ∆Istep=0.08mA/step, ∆Tstep=0.03°C/step, Kc=1.07.
Since this function does not actually watch the wavelength, care must be exercised when setting these values.
Parameter values of Kc can be selected from 0.125, 0.25, 0.375, 0.5, 0.625, 0.75, 1.0, 1.125, 1.25 and 1.5.
<Rev. 0.6E Preliminary>
-21-
2001/11
AKM Confidential
AK2571
5. Sequencer
5.1 Operation mode
The AK2571 has three operation modes shown below. Use the serial interface to change from one mode to another. Figure
5-1 shows the operating flowchart and table 5-1 indicates the circuit block capabilities.
1) Self-operation mode: Operates ATC and APC automatically according to the data stored in EEPROM.
2) Register access mode: Adjust the data to set the characteristics of LD. Read and write registers are accessed by writing
commands to the Digital interface.
3) EEPROM access mode: Fix the adjusted data and parameters in EEPROM. Data in register are written in
EEPROM and reset. All ATC and APC functions are disabled in this mode.
Figure 5-1
Register
access
mode
RST
POWER ON
Self
operation
mode
Retain the
value of
Register
RST
RST
RST
EEPROM
access
mode
Table 5-1
Register
EEPROM
Status
APC
Read
Write
Read
Write
P_EEP
ATC
Self operation mode
O.K.
Non
Non
Non
0
Auto operation by
EEPROM data
Auto operation by
EEPROM data
Register access
O.K.
O.K.
Non
Non
0
Operation by register
data
Auto operation by
register data
EEPROM access
Non
Non
O.K.
O.K.
1
Shut Down
Shut Down
5.2 Self operation mode
5.2.1
Start up sequence
The AK2571 has various start-up sequence patterns that set the control register (R_CTRL_AKM / R_CTRL_USER). The
AK2571 automatically executes the start up sequence stored in EEPROM when it is started or re-start. Table 5-2 and
Figure 5-2explains each sequence.
<Rev. 0.6E Preliminary>
-22-
2001/11
AKM Confidential
AK2571
Table 5-2
Condition
of finish
ATC status
APC status
APC_FB
ATC_FB
APCALM
ATCALM
Power ON
Status-1
ATC Lock
(Only ATC
work)
ATC Lock
Disable
Disable
Disable
User setting
User setting
Status-2
APC
(APC Count Count up
up work)
Normal
operation
Count up or Disable
Disable
(User setting)
Disable
User setting
User setting
Status-3
(Normal
operation)
Normal
operation
Normal
operation
User setting
User setting
User setting
User setting
Figure 5-2 Start up sequence
APC Count_Up
ATC Lock (ATC Work)
Reset ATC_LK_COUNTER
LD Temperature [℃]
(Thermister temperature）
R_LK_TMPRT_WIN
ATC_LK_COUNTER
UP
Countup I-DAC by one
step
Normal
Operation
R_TMPRT_
TRGT
ATC_COUNTER UP
Timer Count up
Expiring
ATC_LK_COUNTER
tothe thereshold
(E_LK_CNT_SET), move
to next status
Expiring count up of
the settled I-DAC,
move to next status
When the timer
expire, move
tonormal
operation,TIMERAL
M=L
Power-On-Reset Release
<Rev. 0.6E Preliminary>
Time [s]
-23-
When the timer expire,
doesn't reach to normal
operation, TIMERALM=H
2001/11
AKM Confidential
AK2571
5.2.2
Control registers
Figure 5-3 illustrates the register format. There are two areas in these registers, one is for AKM factory use and the other is
for user customization. Even though both areas are re-writable, the AKM values SHOULD NOT BE OVERWRITTEN.
If the AKM values are modified product functionality cannot be guaranteed.
Figure 5-3 Control Register
Self operation mode: Load the data from EEPROM to register
Register access mode: All data can be rewritable
R_CTRL_AKM
R_CTRL_USER
Register
D7
D6
D5
D4
D3
D2
D1
Apc_
Atc_
Apc_
Apc_
alm[4] alm[3] count[2] fb[1]
D0
D7
D6
D5
D4
D3
D2
Atc_ Reserved Timer Apc_
Atc_
Atc_
fb[0]
main[5] lock[4] main[3]
[7] [6]
D1
D0
Fix_cntl[2:0]
Atc_main / Atc_lock / Apc_main / Timer / Atc_fb / Apc_fb / Apc_cnt: 0: Disable 1: Enable
Atc_alm / Apc_alm: 0 ALM Enable, 1: ALM Disable
Fix_ctrl[2:0]:
000: Start up or APC Count-up, Except000: Normal operation
EEPROM
User available area
Factory usage area by AKM
E_INI_CNTL_AKM
E_INI_CTRL_USER
X
Initial Status
X
X
0
1
0
X
X
0
1
1
0
1
1
E_APC_CNT_CTRL_USER
1
0
0
0
0
0
0
1
1
1
E_APC_CNT_CTRL_AKM
APC Count-up
0
1
E_FIX_CTRL_AKM
E_FIX_CTRL_USER
Normal Operation
1
X
0
1
X: Forbidden（Ignore the setting)
5.2.3
ATC Lock
1) When temperature data (R_TMPRT_CRNT) enters the target temperature range (R_TMPRT_TRGT) +/- hysteresis
(E_LK_TMPRT_WIN) ATC_LOCK_COUNTER starts to count up every 8mS.
2) Once temperature data is out of the range, ATC_LOCK_COUNTER is reset.
3) LD temperature is stabilized when ATC_LOCK_COUNTER reaches the settled value (E_LK_CNT_SET),. When
this happens, the AK2571 completes the ATC Lock sequence and moves to Status-2.
5.2.4
APC Count up
1) Increment the selected I -DAC value by one step (each 8mS) to prevent abrupt heat increases from affecting ATC.
2) Count up ends when the I-DACx selected by E_APC_CNT_SET (Count up DAC) reaches the target value
(E_APC_CNT_CTRL_USER[7:0]).
3) The unselected I-DAC retains the feed forward APC value if the Count up DAC doesn’t reach settled value.
4) Although the unselected DAC doesn’t reach its feed forward APC (or fixed) value, if count up DAC reaches to the
settled value, the AK2571 moves to Status-3
5.2.5
Timer
1) Counts the time from power on reset or release of shut down.
2) If the AK2571 does not reach normal operation within the period set by the settling time register (E_TIMER_SET), ,
TIMERALM is output.
<Rev. 0.6E Preliminary>
-24-
2001/11
AKM Confidential
AK2571
5.2.6
Normal operation
After theAK2571 has been properly configured and is in “normal” operating mode, continuous temperature compensation
is performed every 8 milliseconds using the data in EEPROM.
5.3 Register access mode
Register access mode is used to for adjust the characteristics of the Laser Diode Module. Any characteristics can be
adjusted while monitoring by writing to the appropriate register. Please refer to “8. Registers” for details.
5.3.1
ATC and APC Adjustment Example
The following adjustment process example is based on the assumption that polarity of ALM, threshold level of ALM, PID,
Max current of APC feedback, etc. are already fixed and every parameter is written in the EEPROM continuously.
1) Change the operation mode from self-operation to register access by sending the appropriate command through the
Digital interface.
2) Common settings
2-1) Write zero (“0”) to all registers R_CTRL_AKM .to stop the AK2571 working.
2-2) Select I-DACx for APC by using the R_DAC_SET register.
2-3) If the temperature corresponding to wave length is known (either exactly or approximately), set the input
temperature offset by using the R_ATC_OFFSET register. (Please refer to “4.4 Gain & Offset”). In this process, the
target temperature must be set at the midpoint of the ADC (80h).
2-4) Write 80h to the target temperature register (R_TMPRT_TRGT)
2-5) Use register R_TEC_CTRL_SET to select a way to control the TEC.. When using Analog control use register
R_TEC_ANALOG to select Analog-1 or Analog –2.. If using Digital control, use register lR_TEC_PWM_SET to set
the PWM division.
3) ATC adjustment
3-1) Temperature Adjustment
When a “1” is written to the R_CTRL_AKM Atc_main(R_CTRL=08h), the ATC begins control of the TEC to meet
target the temperature. 10 to 30 seconds are required before the LD temperature is fully stabilized. This time depends
on the difference between ambient temperature and target temperature. Stabilization is detected from the ATC Lock
completion signal through the STATUS_MON pin moving from Low to High. To detect this signal, E_LK_CNT_SET
and E_LK_TMPRT_WIN must be set to the appropriate values, STATUS_MON pin must be set to ATC_LK
(R_STATUS_SET=000), and a “1” must be written R_CTRL_AKM.Atc_lk (R_CTRL_AKM=18h) prior to ATC
adjustment.
To complete the ATC adjustment by monitoring the temperature, a preliminary rough adjustment is made using the
offset (R_ATC_OFFSET) and secondary fine adjustment using the target temperature register(R_TMPRT_TRGT)
should be executed to match the temperature required.
3-2) Wavelength Adjustment
It is also possible to adjust the ATC monitoring wavelength. When doing this, the APC be adjusted to work to maintain
consistent light power. Writing “1” in R_CTRL_AKM.Apc_main ( R_CTRL_AKM=28h) starts APC. Follow the APC
adjustment instructions in the next section and roughly set R_DACx_GAIN and R_DACx corresponding to I-DAC for
use.
A preliminary rough adjustment is made using the offset (R_ATC_OFFSET) and secondary fine adjustment using the
target temperature register(R_TMPRT_TRGT) should be executed to match the temperature required.
<Rev. 0.6E Preliminary>
-25-
2001/11
AKM Confidential
AK2571
4) APC adjustment
4-1) I-DAC adjustment
a) Adjust R_DACx to set the light power of the LD. Firstly set register R_DACx_GAIN for the full code of I-DAC
being over 80h to get sufficient accuracy. But it is need to take the margin for LD aging compensation for the
APC Feed back DAC. R_DACx_GAIN of APC Feed back must be limited to remain Feed back compensation
current. For example R_DACx must not beyond 80h if aging compensation current is needed by the same
amount of initial current. And not beyond C0h if aging compensation current is needed by the half amount of
initial current.
b) When using the I-DAC1 dithering function, enable R_EA_SW, set the gain using register R_EA_GAIN and set
the frequency using R_EA_FREQ. Monitor the total I-DAC1 current since this dithering current is added to
R_DAC1 R_DAC1 must be adjusted with this in mind.
c) If the wavelength moves after the APC adjustment, adjust R_TMPRT_TRGT to match the wavelength or go
back and readjust the ATC.
4-2) PDMON Gain setting
Set the PD voltage gain monitoring. The range is from 0.4V to 1.1V / 0.1V step. This setting must be executed after
R_PDGAIN is set.
4-3) Initial aging error setting (R_APC_TRGT adjustment)
a) STATUSMON setting: Set R_STATUS_SET = “APC FB”. When the aging compensation current is added to
the I-DAC output, STATUS_MON becomes High.
b) R_CTRL_USER.Apc_fb = 1 executes the APC Feedback function. In this register access mode, actually the APC
Feedback function doesn’t add current to the R_DACx to make sure this adjustment.
c) Moving R_APC_TRGT, identify the point at which STATUS_MON becomes High. This is the initial aging set
point.
5) APC setting
If there are external components affected by ambient temperature changes (current amplifiers, driver IC etc.), training for
cancellation of temperature characteristics is needed. To do this:
5-1) Stabilize the ambient temperature
5-2) Read the R_TV[7:0] (internal T_V converter digital output) through the serial interface.
5-3) Adjust R_DACx to output adequate current at the temperature.
5-4) Store the data 5-2) as address and 5-3) as data in the look-up table.
5-5) Change temperature and repeat this sequence.
6) Set another wavelength
The AK2571 can store the data for four wavelengths in EEPROM. To get the data for another three wavelengths, repeat
the sequence from 2) to 5).
Wavelength selection is via pin control.
7) Writing the EEPROM
7-1) Compose the data to write in the EEPROM based on the adjustment above.
7-2) Change the mode to EEPROM mode.
7-3) Write the data in EEPROM through the serial interface.
8) Test
Change to Self-operation mode, and confirm all functions work. If there are problems, repeat steps1 to7 and readjust.
Caution: All the data in registers is reset when the power is removed or when the operating mode is changed.
<Rev. 0.6E Preliminary>
-26-
2001/11
AKM Confidential
AK2571
5.3.2
Confirmation of other functions
1) OPALM confirmation
When the APC adjustments are complete, set R_OPALM_SET.
Gradually decrement the value of R_DACx OPALM is output as a current. Confirm LD light power is settled value or not
by monitoring the output of PDMON.
2) Aging Error Compensation confirmation
After APC adjustments are complete, write “1” in R_CTRL.Apc_fb. decrement the value of R_DACx , but don’t reduce it
too much as OPALM is output. APC Feedback begins to function and will increase the value of R_APC_CMPNST. In this
register access mode, APC does not add to R_DACx and the light power of the LD does not increase, actually. Eventually
R_APC_CMPNST will equal E_APC_FB_MAX. If E_CUALM_SET is set to an equal value of E_APC_FB_MAX
beforehand, CUALM out expresses the increment of aging compensation current.
3) Aging shift of wavelength compensation confirmation
This confirmation can be done with 2) Aging Error Compensation confirmation. R_CTRL.Atc_fb=”1” enables the ATC
feedback confirmation. Decrement the value of R_DACx, but do not reduce it too much as OPALM is output. APC
Feedback begins to function and increases the value of R_APC_CMPNST. According to this value, R_ATC_CMPNST is
increased by the E_ATC_FB_SET parameter. R_ATC_CMPNST will eventually equal E_ATC_FB_MAX. If
E_WLALM_SET is set equal to E_ATC_FB_MAX and below the value of E_APC_FB_SET or E_ATC_FB_SET
beforehand, WLALM output indicates the shift of target temperature.
6. Monitor function
6.1 AMON pin analog monitor
Set R_MON_SET (E_MON_SET) register, and monitor the values in the registers below through MON-DAC. Table 6-1
indicates the registers that can be monitored. Output voltage ( Vmon) (typ) is expressed below.
Vmon = (2.1-0.5) / 255*K+0.5 [V]
K=the decimal value of the register
Table 6-1 Monitoring Register
R_MON_SET
Monitoring Function
Remarks
0
0
0
0
Fixed voltage
R_MON_DAC_FIX
0
0
0
1
PID control absolute value
R_RID_ABS[12:5]
0
0
1
0
APC feedback value
R_APC_CMPNST[7:0]
0
0
1
1
ATC target value
R_TMPRT_CRNT[7:0]
0
1
0
0
ATC feedback value
R_ATC_CMPNST[7:0]
0
1
0
1
IDAC1 set value
R_DAC1[7:0]
0
1
1
0
IDAC2 set value
R_DAC2[7:0]
0
1
1
1
IDAC3 set value
R_DAC3[7:0]
1
0
0
0
T_V converter output
R_TV[7:0]
<Rev. 0.6E Preliminary>
-27-
2001/11
AKM Confidential
AK2571
6.2 STATUS_MON pin output
Set R_STATUS_MON (E_STATUS_SET), and monitor the status in AK2571 through STATUS_MON pin. Table 6-2
indicates the setting
Table 6-2 STATUS_MON output
E_STATUS_SET[2:0]
STATUS_MONoutput
000
ATC_LOCKATCLockcountup
001
010
011
100
101
110
111
Remarks
APC_END
APCCount-upexpiring
E_FIX_CTRL
Movetonormaloperation
APC_FB
APCFeedbackworking
ATC_FB
ATCFeedbackworking
REG
Registeraccessmode
PID_SIGN
PIDcontroldirection
APC_COMP
APC_COMPoutput
0:counting
1:countup
0:APCCount-uporCount-updisable
1:APCCount-upexpiring
0:beforenormaloperation(startup)
1:NormalOperation
0:APCFeedbackCompensationcurrent=0
1:APCFeedbackCompensationcurrent>0
0:ATCFeedbacktargettemp.shift=0
1:ATCFeedbacktargettemp.shift>0
0:SelfoperationorEEPROMmode
1:Registeraccessmode
0:Heating
1:Cooling
0:PDINishigherthantarget
1:PDINislowerthantarget
7. EEPROM
The internal 4k-bits EEPROM is composed of 16-bits*256 addresses. The memory map is shown in Table 7-1. Two MSB
bits are set by WAVE0 and 1,. It is possible to change the target temperature via pin strapping if the adjustment data for
each wavelength is stored in an EEPROM address.. Table 7-2 indicate the relationship between WAVE0, 1 and the
EEPROM addresses. Addresses from [xx111010] to [xx111111], which contain system data, user program area and AKM
factory data, are valid regardless of the settings of WAVE0,1.
<Rev. 0.6E Preliminary>
-28-
2001/11
AKM Confidential
AK2571
Table 7-1 EEPROM Memory Map Overview
Address
D15-D8
00
00
0000
E_DAC1_TV[00001]
D7-D0
E_DAC1_TV[00000]
Wavelength-1: I-DAC1temperature
compensation value
1111
01
10
11
01
10
11
00
11
00
11
00
11
0000
1111
0000
1111
0000
1001
1010
1111
0000
1001
1010
1111
0000
1001
1010
1111
0000
1001
1001
1111
E_DAC1_TV[11110]
E_DAC1_TV[11111]
E_DAC2_TV
Wavelengh-1 I-DAC2 temperature compensation value
E_DAC3_TV
Wavelength-1 I-DAC3 temperature compensation value
Wavelength-1setting data for each wavelength
Common setting data-1
Wavelength-2 data
Common setting data-2
Wavelength-3 data
User program area
Wavelength-4 data
Factory usage by AKM
Table 7-2 Relation of WAVE0, 1and EEPROM [A7, A6]
WAVE1
WAVE0
Address 2bit from MSB
A7
A6
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
<Rev. 0.6E Preliminary>
-29-
Remarks
Wavelength-1
Wavelength-2
Wavelength-3
Wavelength-4
2001/11
AKM Confidential
AK2571
7.2 Data construction
1) Temperature compensation data
Force the temperature compensation current on the output of DAC1-3 using the internal T_V converter. Digital MSB
4-bits of data from the T_V converter becomes the address of EEPROM and 5-bit (R_TV[3]) selects the 8-bits data whether
D15-D8 or D7-D0. Table 7-3 indicate the temperature compensation data format.
Table 7-3 Temperature compensation data
Name
E_DAC1_TV
E_DAC2_TV
E_DAC3_TV
Address
A5, A4 A3-A0
00
0000
|
Function
I-DAC1
Temperature
compensation
data
A7, A6
xx
I-DAC2
Temperature
compensation
data
I-DAC3
Temperature
compensation
data
xx
01
0000
|
1111
xx
10
0000
|
1111
1111
Data
D15-D8
D7-D0
E_DAC1_TV E_DAC1_TV
[00001]
[00000]
|
|
E_DAC1_TV E_DAC1_TV
[11111]
[11110]
E_DAC2_TV E_DAC2_TV
[xxxx1]
[xxxx0]
E_DAC3_TV
[xxxx1]
E_DAC3_TV
[xxxx0]
(1) Setting data for each wavelength
Table 7-4 and 7-5 indicate the data construction for setting data of each wavelength.
Address is A3 toA0 ([A7:A6] is set by WAVE1, 0 and [A5, A4] is fixed [1,1])
Reg marked “1” indicate the existence of related register.
Table 7-4 setting data of each wavelength
Name
Bit
Function
Reg
A3-A0
Data
xx11
0000
D4-D0
Setting
00000: 0dB
11111: 21.7dB
0.7dB Step, Refer table3-3
000: 0.4V
111: 1.1V
0.1V Step, Refer table 3-2
Refer Table 4-6, 4-7
000000: 0.3V
101000: 1.7V
29.7mV / Step
E_PDGAIN
5
PDGAIN set
E_PDMON_SET
3
PDMON output voltage
1
set
0000
D7-D5
E_ATC_OFFSET
6
ATC OFFSET set
1
0000
D15-D8
E_MON_DAC_FIX
8
MON_DAC
fixed value
1
0001
D7-D0
Refer table 6-1
E_DAC1_GAIN
2
I-DAC1 Gain set
1
0010
D1-D0
Refer table 3-5
00: 1, 01: 1/2, 10: 1/4,
11: 1/12
E_DAC2_GAIN
2
I-DAC2 Gain set
1
0010
D3-D2
Refer table 3-6
00: 1, 01: 1/2, 10: 1/4
<Rev. 0.6E Preliminary>
1
A7-A4
output
-30-
2001/11
AKM Confidential
AK2571
E_DAC3_GAIN
2
I-DAC3 Gain set
1
0010
D5-D4
Refer table 3-7
00: 1, 01: 1/2, 10: 1/4
E_EA_SW
1
EA ON/OFF set
1
0010
D8
0: OFF, 1: ON
E_EA_GAIN
2
EA Gain set
1
0010
D10-D9
E_EA_FREQ
3
EA Frequency set
1
0010
D13-D11
E_APC_TRGT
7
APC Feedback
Reference voltage set
1
0011
D6-D0
E_APC_FB_MAX
8
APC Feedback limit
current set
0011
D15-D8
E_DAC1_FIX
8
I-DAC1Fixed
set
2
0100
D7-D0
E_DAC2_FIX
8
I-DAC2 Fixed current
2
set
0100
D15-D8
E_DAC3_FIX
8
I-DAC3 Fixed current
2
set
0101
D7-D0
E_ATC_FB_MAX
8
ATC Feedback target
shift limit set
0110
D7-D0
E_ATC_FB_SET
4
Parameter set for LD
compensation current to
target temperature
0110
D11-D8
0000: 0.125, 0001: 0.25
0010: 0.375, 0011: 0.5
0100: 0.625, 0101: 0.75
0110: 1.0, 0111: 1.125
1000: 1.25, 1001: 1.5
E_ATC_TRGT
8
ATC
target
2
temperature set
0111
D7-D0
0.03°C /LSB
E_TMPRT_ALM_WI
N
8
TEMPALM set
0111
D15-D8
E_CUALM_SET
8
CUALM set
1000
D7-D0
E_WL_ALM_SET
8
WLALM
(target
temperature shift ALM)
set
1000
D15-D8
<Rev. 0.6E Preliminary>
current
-31-
Refer table 3-9
00: 16%, 01: 8%
10: 4%, 11: 2%
Refer table 3-8
000: 16k, 001: 32k, 010: 64k, 011:
128k, 100: 256k
0000000: 1.5V
1111111: 2.1V
4.8mV/Step, Refer Table 3-4
2001/11
AKM Confidential
AK2571
Table 6-5 Data and address construction for each wavelength
Address
A3-A0 15
0000
0001
0010
14
0011
0100
0101
0110
0111
1000
1001
Data
13 12 11 10
9
8
7
6
5
4
3
2
1
0
E_ATC_OFFSET[5:0]
E_PDMON_SET[2:0]
E_PDGAIN[4:0]
E_MON_DAC_FIX[7:0]
E_EA_
E_DACi_GAIN
FREQ
GAIN SW
DAC3
DAC2
DAC1
E_APC_TRGT［6:0］
E_APC_FB_MAX[7:0]
E_DAC2_FIX[7:0]
E_ATC_FB_SET[3:0]
E_TMPRTALM_WIN[7:0]
E_WLALM_SET[7:0]
Reserved
E_DAC1_FIX[7:0]
E_DAC3_FIX[7:0]
E_ATC_FB_MAX[7:0]
E_ATC_TRGT[7:0]
E_CUALM_SET[7:0]
(2) Common setting data
Table 7-6 and 7-7 show common data settings in the EEPROM. Registers marked “1” indicate the existence of a related
register.
Table 7-6 Common setting data construction
Address
A7,A6 A5, A4 A3-A0
00
11
1010
Name
E_TEC_ANALOG
Bits
1
E_PID_PWM
2
Function
Reg
TEC Analog way 1
select
PWM division set
1
E_PID_CTRL
1
Analog / PWM set
1
1010
E_DAC_SET
3
I-DAC set
1
1010
E_APC_FF_SET
1
1011
E_APC_FB_SET
3
APC Feed forward 1
set
APC Feedback data 1
add I-DAC selection
E_APC_CNT_SET
2
APC
Count-up 1
finalize I-DAC select
1011
E_TV_OFFSET
5
Internal T_V conv. 1
1100
<Rev. 0.6E Preliminary>
-32-
1010
1011
Setting
0: Analog-1way
1: Analog-2way
00: Not divide
01: 32, 10:64, 11:128
0: Analog control
1: PWM control
0: Disable
1: Enable
[0]: I-DAC1
[1]: I-DAC2
[2]: I-DAC3
0: fixed current
1: compensation
0: not addition
1: addition
[0]: I-DAC1
[1]: I-DAC2
[2]: I-DAC3
00: I-DAC1
01: I-DAC2
10: I-DAC3
11: Disable
Refer Table 3-10
2001/11
AKM Confidential
AK2571
E_MON_SET
4
E_STATUS_SET
3
E_ALM_SHUTDW
2
OFFSET
adjustment
MON-DAC output 1
set
STATUS
MON 1
output set
ALM output set
1
Adjusted by AKM
E_ALM_POL
1
ALM polarity set
1
1110
E_OPALM_SET
3
OPALM threshold 1
set
1110
E_TIMER_SET
2
1111
E_INI_CTRL_USR
8
E_APC_CNT_CTRL_
USR
E_FIX_CTRL_USR
8
8
E_LK_TMPRT_WIN
8
E_LK_CNT_SET
2
TIMER ALM count
period set
Start up sequence
set
APC
Count-up
operation set
Normal operation
set
Window set for ATC
Lock window
ATC Lock period set
E_PID_D
8
E_PID_P
8
E_PID_I
8
E_PID_MAX
6
E_PIDALM_SET
1101
Refer table 6-1
1101
Refer table 6-2
1110
1010
0x: ALM enable
10: Fix not active
polarity
11: Fix active polarity
0: ALM detect “H”
1: ALM detect “L”
000: 1/2, 001: 1/3
010: 1/4, 011: 1/5
100: 1/6, 101: 1/8
00: 8s, 01: 16s
10: 32s, 11: 64s
Refer 5.2.2
2
1010
Refer 5.2.2
2
1011
Refer 5.2.2
1100
0.03 °C/LSB
1100
1
2
01
11
PID
differential
parameter
PID
proportion
parameter set
PID
integration
parameter set
PID
control
maximum value set
1101
00: 2s, 01: 4s,
10: 8s, 11: 16s
Refer Table 4-3
1101
Refer Table 4-3
1101
Refer Table 4-3
1101
8
PIDALM set
1111
E_PID_INACT_SET
8
PID not
window set
6bits MSB of
absolute control
(13bits)
8bits MSB of
absolute control
(13bit)
8bits LSB of
absolute control
(13bits)
USER program area
96
AKM adjust area
96
sense
1111
Start up sequence
operation set
10
11
11
11
1010
|
1111
1010
|
1111
PID
value
PID
value
PID
value
Don’t touch the data.
Table 7-7 Common data addresses
<Rev. 0.6E Preliminary>
-33-
2001/11
AKM Confidential
AK2571
Ｄａｔａ
Addrｅss
[7:6] [5:4]
00
11
[3:0]
15
14
13
12
11
10
1010
9
8
7
6
5
4
E_DAC_SET[2:0]
1011
3
2
Ctrl
CNT_SET
1100
E_STATUS_SET
1110
PWM[1:0] Ana
APC_FB_SET
FF
E_MON_SET[3:0]
E_OPALM_SET
POL
1111
11
0
E_TV_OFFSET[4:0]
1101
01
1
ALM_SH
TIMER_SET
1010
E_APC_CNT_CTRL_USR[7:0]
E_INI_CTRL_USR[7:0]
1011
E_FIX_CTRL_USR[7:0]
1100
E_LK_CNT_SET
1101
E_PID_P[7:0]
1110
E_PID_D[7:0]
E_PID_MAX[5:0]
1111
E_LK_TMPRT_WIN[7:0]
E_PID_I[7:0]
E_PID_INACT_SET[7:0]
E_PIDALM_SET[7:0]
8 Register
Table 8-1 and 8-2 show register contents and formats.
The EEP column indicates:
1: existence of same function in EEPROM
2: existence of related function inEEPROM.
Table 8-1 Construction of Registers
Register Name
Bits
Function
R_PDGAIN[4:0]
5
PDGAIN Set
R_PDMON_SET[7:5]
3
PDMON output voltage set
R_ATC_OFFSET[13:8]
6
ATC OFFSET set
R_MON_DAC_FIX[7:0] 8
R_DAC1_GAIN[1:0]
2
MON_DAC fixed value set
I-DAC1 Gain set
R_DAC2_GAIN[3:2]
2
I-DAC2 Gain set
R_DAC3_GAIN[5:4]
2
I-DAC3 Gain set
R_EA_SW[8]
R_EA_GAIN[10:9]
1
2
EA ON/OFF set
EA Gain set
<Rev. 0.6E Preliminary>
-34-
EEP Address
Setting
A5-A0
1
000000 00000: 0dB
11111: 21.7dB
0.7dB Step, refer table3-3
1
000000 000: 0.4V
111: 1.1V
0.1V Step, refer table 3-2
1
000000 Refer table 4-6, 4-7
000000: 0.3V
101000: 1.7V
29.7mV / Step
1
000001 Refer table 6-1
1
000010 Refer table 3-5
00: 1, 01: 1/2, 10: 1/4,
11: 1/12
1
000010 Refer table 3-6
00: 1, 01: 1/2, 10: 1/4
1
000010 Refer table 3-7
00: 1, 01: 1/2, 10: 1/4
1
000010 0: OFF, 1: ON
1
000010 Refer table 3-9
2001/11
AKM Confidential
AK2571
R_EA_FREQ[13:11]
3
EA frequency set
1
000010
R_APC_TRGT[6:0]
7
APC Feedback
Reference voltage set
1
000011
R_TEC_ANALOG[0]
1
TEC Analog control select
1
000100
R_PID_PWM[2:1]
2
PWM division set
1
000100
R_PID_CTRL[5:4]
1
Analog / PWM select
1
000100
R_DAC_SET[10:8]
3
I-DAC enable
1
000100
R_APC_FF_SET[0]
1
APC Feed forward select
1
000101
R_APC_FB_SET[3:1]
3
APC Feedback added I-DAC 1
select
000101
R_APC_CNT_SET[5:4]
2
APC Count-up finalize I-DAC 1
select
000101
R_TV_OFFSET[4:0]
5
1
000110
R_MON_SET[3:0]
4
R_STATUS_SET[6:4]
3
R_ALM_SHUTDW[1:0] 2
Internal T_V conv. Offset
adjustment
MON-DAC output set
STATUS MON output set
ALM output set
1
1
1
000111
000111
001000
R_ALM_POL[2]
1
ALM output polarity set
1
001000
E_OPALM_SET[10:8]
3
OPALM threshold set
1
001000
R_TIMER_SET[1:0]
2
TIMER ALM count period set
1
001001
R_TMPRT_TRGT[7:0]
8
ATC target temperature set
2
001010
R_CTRL_USR[7:0]
R_DAC1[7:0]
R_DAC2[7:0]
8
8
8
Control register set
I-DAC1 set
I-DAC2 set
2
2
2
001011
001100
001101
<Rev. 0.6E Preliminary>
-35-
00: 16%, 01: 8%
10: 4%, 11: 2%
Refer table 3-8
000: 16k, 001: 32k, 010:
64k, 011: 128k, 100: 256k
0000000: 1.5V
1111111: 2.1V
4.8mV/step, refer table3-4
0: Analog-1way
1: Analog-2way
00: not divide
01: 32, 10:64, 11:128
0: Analog way
1: PWM way
0: disable
1: enable
[0]: I-DAC1
[1]: I-DAC2
[2]: I-DAC3
0: fixed value
1: compensation data
0: not addition
1: addition
[0]: I-DAC1
[1]: I-DAC2
[2]: I-DAC3
00: I-DAC1
01: I-DAC2
10: I-DAC3
11: disable
Refer table 3-10
AKM factory usage
Refer table 6-1
Refer table 6-2
0x: ALM enable
10: Fix not active polarity
11: Fix active polarity
0: ALM detect “H”
1: ALM detect “L”
000: 1/2, 001: 1/3
010: 1/4, 011: 1/5
100: 1/6, 101: 1/8
00: 8s, 01: 16s
10: 32s, 11: 64s
E_ATC_TRGT –
R_ATC_CMPNST
Refer 5.2.2
2001/11
AKM Confidential
AK2571
R_DAC3[7:0]
R_STATUS[7:0]
R_ALM_ST[3:0]
R_TMPRT_CRNT[7:0]
R_TV[7:0]
8
8
4
8
8
R_APC_CMPNST[7:0]
R_ATC_CMPNST[7:0]
R_MON_DAC[7:0]
R_PDMOND[7:0]
R_PID_INTGRL[7:0]
8
8
8
8
8
R_PID_INTGRL[13:0]
14
R_PID_VALABS[14:0]
R_CTRL_AKM[7:0]
15
8
<Rev. 0.6E Preliminary>
I-DAC3 set
Status register
2
Theremistor temperature data
Internal
T_V
conv.
Temperature data
LD aging error current
Target temperature shift value
Monitor DAC set
PDMON output digital value
PID Integration value (under
decimal)
PID Integration value (integral
number 2’s)
PID control value
Control register
2
-36-
001110
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
111011
2001/11
AKM Confidential
AK2571
Table 8-2 Register Map
Ｄａｔａ
Addrｅss
[5:4] [3:0] 15 14 13 12 11
00 0000
10
9
8
R_ATC_OFFSET[5:0]
7
R･W
6
5
4
R_PDMON_SET[2:0]
0001
3
2
1
0
R_PDGAIN[4:0]
R/W
R_MON_DAC_FIX[7:0]
0010
R_EA_
FREQ
GAIN
SW
DAC3
R_DAC_SET[2:0]
Ctrl
0101
CNT_SET
0110
DAC1
R/W
PWM[1:0] Ana
APC_FB_SET
R/W
FF
R/W
R_TV_OFFSET[4:0]
0111
1000
DAC2
R/W
R_APC_TRGT［6:0]
0011
0100
R/W
R_DACi_GAIN
R_STATUS_SET
R_OPALM_SET
R/W
R_MON_SET[3:0]
R/W
POL
ALM_SH
R/W
R_TIMER_SET
R/W
1001
1010
R_TMPRT_TRGT[7:0]
R/W
1011
R_CTRL_USR[7:0]
R/W
1100
R_DAC1[7:0]
R/W
1101
R_DAC2[7:0]
R/W
1110
R_DAC3[7:0]
R/W
1111
01 0000
R_STATUS[7:0]
0001
R_ALM_ST[3:0]
R
R
0010
R_TMPRT_CRNT[7:0]
R
0011
R_TV[7:0]
R
0100
R_APC_CMPNST[7:0]
R
0101
R_ATC_CMPNST[7:0]
R
0110
R_MON_DAC[7:0]
R
0111
R_PDMOND[7:0]
R
R_PID_INTGRL[7:0]
R
1000
1001
1010
R_PID_INTGRL[21:8]
R_PID_VALABS[14:0]
11 1011
R
R
R_CTRL_AKM[7:0]
R/W
1. Digital I/F
<Rev. 0.6E Preliminary>
-37-
2001/11
AKM Confidential
AK2571
CSN must be set for each instruction. It cannot be used continuously.
Digital I/F can connect directly to a SPI interface In this case, set (CPOL, CPHA) = (0, 0) or (1, 1).
(CPOL, CPHA) = (0, 0) : Status output through DO pin
(CPOL, CPHA) = (1, 1) : Status output disable
1.1 Register access [READ] mode （RDREG)
CSN
SK
DI
1
2
3
4
5
6
7
8
0
1
0
1
1
A5
A4
A3
11
12
A0
18
27
D15
D14
D13
27
28
29
30
31
32
D3
D2
D1
D0
29
30
31
32
x
High-Z
DO
17
1.2 Register access [WRITE] mode （WRREG）
CSN
SK
DI
1
2
3
4
5
6
7
8
11
12
16
17
0
1
0
1
0
A5
A4
A3
A0
x
x
D15
<Rev. 0.6E Preliminary>
-38-
28
D4
D3
D2
D1
D0
2001/11
AKM Confidential
AK2571
1.3 EEPROM access mode（WRDS、WREN command）
CSN
SK
DI
1
2
3
4
5
6
7
8
9
1
0
1
0
I3
I2
I1
I0
x
10
x
11
x
26
27
28
29
30
x
x
x
x
x
31
32
x
x
I3 I2 I1 I0
0 0 0 0 ： WRDS
0 0 1 1 ： WREN
1.4 EEPROM access [WRITE] mode （WRITE）
CSN
SK
DI
1
2
3
4
5
6
7
8
9
10
15
16
17
18
29
30
1
0
1
0
0
1
0
0
A7
A6
A1
A0
D15
D14
D3
D2
31
D1
32
D0
High-Z
DO
Te/w
READY
READY
1.5 EEPROM access [READ] mode（READ）
CSN
SK
DI
DO
1
2
3
4
5
1
0
1
0
1
6
7
0
8
0
9
0
10
A7
A6
High-Z
<Rev. 0.6E Preliminary>
14
A2
15
A1
16
17
30
31
32
A0
D15
-39-
29
D3
D2
D1
D0
2001/11
AKM Confidential
AK2571
1.6 Move operation mode
CSN
SK
DI
1
2
3
4
5
6
7
8
9
10
15
16
17
18
29
30
31
32
1
1
1
1
I3
I2
I1
I0
x
x
x
x
x
x
x
x
x
x
I3
0
0
1
I2
0
1
1
I1
0
1
1
I0
0 ： Self operation（NORMAL）
1 ： Register access（REGMODE）
0 ： EEPROM mode（EEPMODE）
<Rev. 0.6E Preliminary>
-40-
2001/11
AKM Confidential
AK2571
2. Shut Down
2.1 Reset through RESETN pin
RESEN=“0”make same function of internal Power-On-Reset.
After its release, AK2571 begins to start up sequence same as Power ON.
2.2 Shut down control through SHUT_ATCN pin
SHUT_ATCN=”0” make AK2571 all power down.
After its release, AK2571 start from reset.
2.3 Shut down control through SHUT_APCN pin
SHUT_APCN=”0” make AK2571 only APC shut down which stop the current output through I-DAC1-3. After its release,
AK2571 start to work by the data before shut down soon.
<Rev. 0.6E Preliminary>
-41-
2001/11
AKM Confidential
AK2571
Electric Characteristics
(1) Absolute maximum rating
Parameter
Symbol
Voltage supply
(AVDD, L1DD, L2VDD, L3VDD, TVDD, VDD
DVDD)
Grand level
(AVSS, BVSS, LVSS, TVSS, DVSS, GND
DAVSS )
VIN
Input voltage（Beside VDDs）
IIN
Input current（Beside VDDs）
Storage temperature
Tstg
(2) Recommended operating conditions
All specifications are regulated under this condition
Parameter
Symbol
Voltage supply
VDD
Ambient Operating Temperature
Ta1
Ta2
Min
typ
max
Unite
-0.3
-
6.5
V
0
-
0
V
GND-0.3
-10
-55
-
VDD+0.3
10
130
V
mA
°C
Min
3.1
-20
+5
Typ
3.3
-
Max
3.5
+85
+50
Die surface temperature
Ta3
-20
*）Target temperature range for ATC. Not tested but design target value.
+115
(3) Current consumption
Parameter
Current consumption（all VDD pin）
Symbol
IDD
Min
-
Typ
TBD
Max
Remarks
VDD=all VDD
GND=all VSS
=all GND
Unite
Remarks
V 3.3V+/-6%
°C Package version
Target
°C ATC
temperature *)
°C Die version
Unite
Remarks
mA 1) 2)
*1) Exclude external load
*2) Setting code of I-DACx(x=1,2,3) is (00)、IDAC4 isｈ(000), all gain setting are default (Gain=”１”).
(4) EEPROM Characteristics
Parameter
min
max
Unite
Condition
EEPROM Re-write
10000
Times *1)
EEPROM data retention
10
Year at 85°C
*1) means total re-write times tolerance: All memory cells are rewrite even though only one address is re-written. In that
sense average tolerance is 39 times ( Total address: 256 address =４wavelength x 64 Address and 10000/256=39 times).
(5) Digital Input / Output DC characteristics
Parameter
Symbol
High level input voltage
VIH
Low level input voltage
VIL
High level output voltage
VOH
Low level output voltage
VOL
<Rev. 0.6E Preliminary>
min
0.7VDD
0.9VDD
-
-42-
typ
-
max
0.3VDD
0.4
Unite
Condition
V
V
V IOH= -0.2mA
V IOL= 0.2mA
2001/11
AKM Confidential
AK2571
(6) Digital Input / Output AC characteristics（Beside Serial Interface）
Parameter
Pin
Symbol
min
typ
Reset pulse width
Tpwr
RESETN
200
-
max
Unite
-
Remarks
ns Refer figure 1
Note) Duty Cycle：（Tpwh／(Tpwh＋Tpwl））×100 %
Tpwh
RESETN
50%
SKN
50%
50%
Tpwl
50%
50%
Tpwr
Figure 1 Reset pulse width
Figure 2 Input Clock Duty Cycle
(7) Digital Input / Output AC characteristics（Serial Interface）
Parameter
Pin Symbol
min
typ
SK interval
SK
Tskp
1
SK Duty Cycle
SK
40
50
CSN setup time before SK fall CSN
Tcss
100
SK
CSN hold time after SK rise
CSN
Tcsh
100
SK
CSN
Tsksl
100
SK setup time before CSN fall
SK
Input clock and data setup / SK
Tdis
200
hold time
DI
Tdih
SK fall to DO output latency
SK
Tpd
DO
READY
Programming time
Te/w
10
CSN high level hold time after READY
Trch
raise READY
CSN
CSN high level to DO output CSN
Toz
latency
DO
max
60
-
Unite
Remarks
μs Refer figure 3
％ Refer figure 2
Refer figure 3
ns
*1)
Refer figure 4
ns
ns
-
ns
300
ns
-
ms
100
ns
100
ns
Refer figure 6
Refer figure 3, 5
Refer figure 4,6
CL＝50pF
Refer figure 5
*2)
Refer figure 5
*2)
Refer figure 4,6
*1) SK must be high when CSN transitions to Low.
*2) When writing in EEPROM
It is forbidden to read or write continuously by keeping CSN low.
<Rev. 0.6E Preliminary>
-43-
2001/11
AKM Confidential
AK2571
CSN
Tskw
Tcss
Tskw
Tskp
SKN
Tdih
Tdis
DI
High-Z
DO
Figure 3: input command timing
CSN
Tcsh
SKN
不定
DI
Tpd
DO
Tpd
Tpd
D3
D2
D1
Toz
High-Z
D0
Figure 4: data output timing
CSN
Tcsh
Te/w
SKN
Tdis
DI
Tdih
D1
DO
D0
不定
High-Z
Trch
Tpd
READY
Figure 5: EEPROM write timing
<Rev. 0.6E Preliminary>
-44-
2001/11
AKM Confidential
AK2571
CSN
Tsksl
SKN
DI
Invalid
High-Z
Tpd
Toz
High-Z
DO
READY
Figure 6: status output through DO pin
* Status output
Monitoring DO pin, indicates the status of READY.
After the WRITE command is executed, SK is fixed Low and CSN moves from High to Low, DO pin changes to status
output mode and outputs a READY signal.
The READY signal through DO pin stops if CSN turns High or the first bit (“1”) of the next command is input. When the
next command is input, CSN must be set high once.
(8) ADC*（Time sharing）A to D converter Input / Output characteristics
Parameter
Condition
min
typ
Resolution
8
DNL
-1
INL
-2
Step (=1LSB)
8.63
Input voltage range
Peak voltage
Output digital code
(9) MON_DAC characteristics
Parameter
Condition
Resolution
DNL
*1)
INL
*1)
Step (=1LSB)
*1)
Output voltage range
Peak voltage
0.0
max
Unite
Bit
LSB
LSB
mV/step
1
2
2.2
V
D[7:0] (00)h-(FF)h (straight binary)
0.0V - 2.2V
Min
Typ
8
-1
－2
max
1
2
6.27
0.5
2.1
Input digital code
D[7:0] (00)h-(FF)h(straight binary)
0.5V - 2.1V
<Rev. 0.6E Preliminary>
-45-
Remark
Design
target
Design
target
Unite Remark
Bit
LSB
LSB
mV/step Remark
V
Design
target
*2)
2001/11
AKM Confidential
AK2571
*1) AMON output voltage
*2) Center voltage of Output ”Vmon” is indicated by the expression below, if DAC code = ”K”.
Vmon = (2.1 - 0.5 ) / 255 * K + 0.5 [V]
(10) DAC_APC characteristics
Parameter
Condition
Resolution
DNL
INL
Step (=1LSB)
Output voltage range
Peak voltage
min
Typ
7
-1
-2
max
1
2
4.8
1.5
Output digital code
2.1
Unite Remark
bit
LSB
LSB
mV/step
V
Design
target
*1)
D[6:0] (00)h-(7F)h (straight binary)
1.5V ～ 2.1V
*1) Center voltage of Output ”Vapc” is indicated by the expression below, if DAC code = ”K”.
Vapc = (2.1 – 1.5 ) / 127 * K + １.5 [V]
(11) IDAC１characteristics
Parameter
Condition
Resolution
INL
Maximum output current
min
typ
8
-2
109.6
121.8
max
+2
134.0
Unite
Remark
bit
LSB
mA ±10%
*1)*4)
mA *2)*4)
mA/step *3)*4)
V
*5)
LSB
Minimum output current
30
Step (=1LSB)
0.353
Output voltage
1.8
DNL
-1
+1
Input digital code
D[7:0] (00)h - (FF)h (straight binary)
*1) at maximum (FF)h setting, gain is 1.
*2) at minimum (00)h setting, gain is 1.
*3) output current ”Iidac1” is indicated by the expression below, if gain is ”G”, DAC setting code is ”K”.
Iidac1 = (maximum output current – minimum output current) / 255 * G * K + minimum output current [mA]
*4) maximum output current, minimum output current and resolution can be set by register.
E_DAC1_GAIN Gain Minimum output Maximum
Resolution
Remarks
[1:0]
current
output current (Design target)
(Design target)
(Design target)
00
1
30mA
121.8mA
0.36mA/step
Default
01
1/2
15mA
60.9mA
0.18mA/step
10
1/4
7.5mA
30.45mA
0.09mA/step
11
1/12
2.5mA
10.15mA
0.03mA/step
*5) Construct external circuit to ensure the voltage of IOUT1 doesn’t exceed this value. If it is over, output current
can’t be guaranteed.
<Rev. 0.6E Preliminary>
-46-
2001/11
AKM Confidential
AK2571
(12) EA_MOD characteristics
Dithering current by EA_MOD function is added to current of I-DAC1and output through IOUT1pin. Output current
through I-DAC1 shifts if this function is enabled by the register R_EA_SW(E_EA_SW).
(1) Dithering Frequency
The dither frequency is selected through register (EEPROM) R_(E_) EA_FREQ, and is derived by dividing the OSC
2.048MHz(typ) clock.
R_EA_FREQ Division
(E_EA_FREQ)
[2:0]
000
1/128
001
1/64
010
1/32
011
1/16
100
1/8
(2) Dithering current gain
R_EA_GAIN
(E_EA_GAIN)
[1:0]
00
01
10
11
Dithering Frequency
(Design target)
min
Typ
16kHz
32kHz
64kHz
128kHz
256kHz
Min
Default
Default
typ
8
-2
19.28
max
Remarks
Dithering current gain
(Design target)
min
typ
max
16%
8%
4%
2%
(13) IDAC2, IDAC3 characteristics
Parameter
Condition
Resolution
INL
Maximum output current
Remarks
21.42
max
+2
23.56
Unite
Remarks
bit
LSB
mA ±10%
*1)*5)
mA *2)*5)
mA/step *3)*5)
V
*4)
LSB
Minimum output current
2.68
Step (=1LSB)
0.084
Output voltage
1.8
DNL
-1
+1
Input digital code
D[7:0] (00)h - (FF)h (straight binary)
*1) at maximum (FF)h setting, gain is 1.
*2) at minimum (20)h setting, gain is 1. Linearity from (00)h to (20)h is not guaranteed.
*3) output current ”Iidac23” is indicated by the expression below, if gain is ”G”, DAC setting code is ”K”.
Iidac23 = (21.42 / 255) * G * K [mA]
*4) Construct external circuit to ensure the voltage of IOUT2 doesn’t exceed this value. If it is over, output current can’t be
guaranteed and APC operations may not work correctly.
*5) The register below sets the maximum output current, minimum output current and resolution. . Their performance is
regulated from a register value of (20)h. When the register value is below 20h, linearity is not guaranteed.
<Rev. 0.6E Preliminary>
-47-
2001/11
AKM Confidential
E_DAC2_GAIN
E_DAC3_GAIN
[1:0]
00
01
10
AK2571
Gain
1
1/2
1/4
Minimum output
Maximum
current
output current
(Design target) (Design target)
0mA
21.42mA
0mA
10.71mA
0mA
5.36mA
Resolution
Remarks
(Design target)
0.084mA/step
0.042mA/step
0.021mA/step
Default
(14) IDAC4 characteristics
Parameter
Condition
Min
Typ
Max
Unite
Remarks
Resolution
10
bit
Maximum output current
45.58
50.64
55.70
mA ±10% *1)
Minimum output current
3.2
mA *2)
Step (=1LSB)
0.050
mA/step *3)
Output voltage
1.8
V
*4)
DNL
-2
+2
LSB
Input digital code
D[9:0] 3FF - 000 (straight binary)
*1) Current at maximum setting (3FF)h .
*2) current of minimum setting (20)h.
Linearity from (00)h to (40)h is not guaranteed. However (00)h setting, will set an internal switch and force the
output to 0V.
*3) output current ”Iidac4” as indicated by the expression below, if DAC4 setting code is ”K”.
Iidac4= (50.64 / 255 ) * K [mA]
*4) Construct an external circuit to ensure that the IOUT4 voltage does not exceed this value. If this value is exceeded,
output current cannot be guaranteed and .APC operation may not function properly.
(15) Shut down characteristics
Parameter
Conditions
SHUTDOWN setup time Time
from
SHUT_APCN/SHUT_ATCN = “L”
to output of IDACx(1,2,3) become
Hi-Z and IDAC4 becomes OFF.
SHUTDOWN release time Time from SHUT_APCN = “H” to
IDACx(1,2,3) output settled
current.
min
typ
max
10
Unite
μs
Remark
500
μs
Only for
SHUT_
APCN
*1)
*1) SHUT DOWN release time is regulated in SHUT_APCN.
(16) T_V conversion characteristics
Parameter
Condition
T_V Conv. gain
Offset adjustment
min
typ
-0.7
max
Unite Remark
°C/step ±5%
Design
target
Regulated by the digital data after A-to-D conversion. Its offset is adjusted by AKM in testing.
<Rev. 0.6E Preliminary>
-48-
2001/11
AKM Confidential
AK2571
(17) Other Input / Output range characteristics
Parameter
Conditions
min
typ
max
Unite
Remarks
PD input range for Monitoring PDIN pin
0.2
1.5
V
Design target
PD monitor output range
PDMON pin
0.4
1.1
V
*1)
PDIN
voltage
0.1V/step
Design target
Gained
by
POMON/PDGAIN
0.4
1.5
V
Design target
Thermister input voltage TEMPIN pin
range
Regulator
voltage
for REFOUT pin
2.3
V
±5%
thermister
Design target
*1) PDIN voltage is user programmable by register setting(Refer 3.3.1) in the range of 0.4 to1.1V by 0.1V/step.
(18) Internal oscillator (OSC) characteristics (AKM adjust in testing)
Parameter
Condition
Min
Frequency
Adjusted by AKM in testing
<Rev. 0.6E Preliminary>
-49-
typ
2.048
max
Unite Remark
MHz ±20%
2001/11
AKM Confidential
AK2571
Pin / Function
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Pin name
TEST1
IOUT4H
NC
IOUT4C
NC
IOUT3
L2VDD
IOUT2
LVSS
NC
NC
IOUT1
WAVE1
WAVE0
SHUT_APCN
SHUT_ATCN
RESETN
TSK
TDI
L1VDD
NC
PDIN
23
24
25
26
27
28
29
30
31
PDMON
TESTA
TEMPIN
REFOUT
AVDD
NC
AVSS
BIAS
AMON
32
33
34
35
36
37
38
39
40
41
42
NC
CSN
NC
READY
DO
NC
DI
SK
DAVSS
DVDD
NC
<Rev. 0.6E Preliminary>
Function
AKM Test pin. Connect to GND .
I-DAC4 output(50mA max).TEC control (Heating)
NC pin. Connect to GND.
I-DAC4 output (50mA max). TEC control (Cooling)
NC pin. Connect to GND.
I-DAC3 output (20mA max). LD drive
Voltage supply for I-DAC2 and 3
I-DAC2 output (20mA max). LD drive
I-DAC GND
NC pin. Connect to GND.
NC pin. Connect to GND.
I-DAC1 output (120mA max). LD drive
Wavelength select. Switch EEPROM space.
Note
Shut down APC. ”L” = Shut down.
Shut down ATC and APC. ”L” = Shut down.
Reset input. ”L”= reset
AKM Test pin. Connect to GND in ordinary
Voltage supply for I-DAC1
NC pin. Connect to GND.
Monitors PD voltage input. PD current is averaged by the external
resistor and capacitor input.
Output gained thermister voltage
AKM Test pin. Connect to GND in ordinary
Input voltage from the thermister; divided by an external resistor.
Supply reference voltage for the thermister.
Voltage supply for analog circuit.
NC pin. Connect to GND.
GND for analog circuit.
Set the internal BIAS currents. Connect 12kΩ±1% to GND.
Outputs analog monitor signals through the DAC. Internal digital signal
monitoring by analog.
NC pin. Connect to GND.
Chip select
NC pin. Connect to GND.
Output = “L” when writing to the EEPROM .
Data output
NC pin. Connect to GND.
Data input
Serial clock input
GND for digital substrate. Connect to GND.
Voltage supply for digital circuit
NC pin. Connect to GND.
-50-
2001/11
AKM Confidential
43
44
45
46
DVSS
EEP
STATUS_MO
N
TIMERALM
47
OPALM
48
CUALM
49
TEMPALM
50
PIDALM
51
WLALM
52
53
NC
COOLP
54
HEATN
55
56
57
58
59
NC
TVSS
TVDD
NC
COOLN
60
HEATP
61
62
63
64
BVSS
L3VDD
NC
TEST2
<Rev. 0.6E Preliminary>
AK2571
GND for digital circuit
“H” output when the AK2571 is in EEPROM mode.
Monitors the AK2571 status.
Timer ALM. Outputs an alarm if the AK2571 doesn’t enter normal
operating mode within the settling period.
Loss of power. Outputs an alarm if the voltage from PDIN is below the
threshold.
Compensation current over alarm. Outputs an alarm if the
compensation current for aging is over the threshold.
Temperature alarm. Output alarm if voltage of TEMPIN is over the
threshold.
PID control ALM. Output alarm if current for TEC control is over the
threshold.
Target temperature shift alarm. Output alarm if the value of target
temperature shift is over the threshold.
NC pin. Connect to GND.
P-CH FET control signal for TEC. PID control directs for cooling, it
becomes Low.
N-CH FET control signal for TEC. PID control directs for heating, it
becomes High. PWM way selected as TEC control, switch corresponding
to PID control value and PWM division value.
NC pin. Connect to GND.
GND for P-CH/N-CH control signal
GND for P-CH/N-CH control signal
NC pin. Connect to GND.
N-CH FET control signal for TEC. PID control directs for cooling, it
becomes High. PWM way selected as TEC control, switch corresponding
to PID control value and PWM division value.
P-CH FET control signal for TEC. PID control directs for heating, it
becomes Low.
GND for substrate
Voltage supply for I-DAC4
NC pin. Connect to GND.
AKM Test pin. Connect to GND in ordinary usage.
-51-
2001/11
AKM Confidential
AK2571
Package Conditions
1) Package
: 64-LQFP
2) Marking
a.1pin indicate: Marked ○ is 1pin
b. AKM trademark: AKM
c. AKM marking: AK2571
d. Date code: YYWWXXX
YY: Year
WW: Week(1～52)
XXX： LOT code
12.0±0.4
10.0
48
33
49
32
AK2571
YYWW
10.0
17
64
1
16
0.15
0゜～10゜
M
0.22±0.05
0.5±0.2
<Rev. 0.6E Preliminary>
0.10±0.05
0.17±0.05
1.0±0.2
1.70MAX
0.5
+0.15
1.40
-0.05
12.0±0.4
AKM
0.10
-52-
2001/11