AKM AK2572

ASAHI KASEI
[AK2572]
AK2572
APC for Burst Mode Applicable Direct Modulation Laser Diode
FEATURES
OUTLINES
■Temperature compensation programming function
(APC_FF) of Bias current (0~85mA) and Modulation
current (0~10mA/0~2.2V) responding to the detected
temperature by the On-chip temperature sensor.
■Stable feedback function in the digital scheme
(APC_FB).
■SFP support TXFAULT function and 1k bit ID field
(EEPROM User Area).
■LD Power leveling function by either Hardware pin
control or Register setting.
■Various alarm functions of Optical output decline
(OPTALM), Excessive LD current (CURRALM),
Exceptional temperature (TEMPALM) and Irregular
external signals (EXTALM1 and EXTALM2).
■Operation adjustment function via 2-wire Digital
interface after assembled into sub-system.
■On-chip Oscillator allows a Self-running operation.
■ Single 3.3 V [Typ.] power supply.
The AK2572 enables to keep the optical power of the direct
modulation LD (Laser Diode) constant by the APC
(Automatic Power Control) circuit. It consists of a current
programming function (APC_FF) responding to the
temperature characteristics of each LD, and a Digital
feedback function (APC_FB) to adjust the LD current
based on the monitoring PD (Photo Diode) current.
The AK2572 is also applicable to the Burst mode
transmission. The device equips a Power leveling function
to switch a temperature compensation programming data
by either Hardware pin control or Register setting.
The On-chip EEPROM (Non-volatile memory) allows to
adjust and to keep the individual setting data for each LD
characteristics via 2-wire Digital interface after being
assembled into sub-system. As 1k bits User Area is
allocated in the EEPROM, which supports the ID field of
the SFP specification, a proper operation required for the
SFP module is realized by using the TXFAULT function.
APPLICATIONS
ORDERING GUIDE
For LD modules applied to Continuous and Burst mode
Product Number
AK2572
Package Type
QFN28 （5.2mm×5.2mm）
BLOCK DIAGRAM
AVDD
DVDD DVSS
AVSS
VDDMD
VDDBI VSSBI
TEMPMON
TEMP
-SENS
ADC
R_TEMP
IOUT1
I-DAC1
Imod
EEPROM
LDD LD
APC
V-DAC3
VOUT3 Vmod
PDMON
Monitor PD
PDIN
Cpd
IOUT2
I-DAC2
PDGAIN
Rpd
ALM Detection
TEMPALM
CURRALM
OPTALM
EXTALM2
EXTALM1
BURST
EXTALM2/MOD_CTRL
EXTALM1
BIAS
RB (12k)
*:Open Drain
**:Internally Pulled-up
<MS0290-E-01>
Ibias
BIAS_GEN
OSC
TEST1 TEST2 TEST3 TEST4
2-wire Digital I/F
SCL
BIAS
MON
(x0.012)
BIASMON
TXFAULT*
SHUTDOW N
CONTROL
TXDIS
SDA* W P**
-1-
2004/8
ASAHI KASEI
[AK2572]
＝ Table of Contents ＝
I.
PIN DESCRIPTION = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 4
II. ABSOLUTE MAXIMUM RATINGS = = = = = = = = = = = = = = = = = = = = = = = = = = = = 6
III. RECOMMENDED OPERATING CONDITIONS = = = = = = = = = = = = = = = = = = = = = 6
IV. ELECTRICAL CHARACTERISTICS = = = = = = = = = = = = = = = = = = = = = = = = = = = = 6
(1) Current Consumption - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 6
(2) EEPROM Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -6
(3) Digital Input / Output Pin DC Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -6
(4) Digital Input / Output Pin AC Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 7
(5) I-DAC1 Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8
(6) I-DAC2 Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8
(7) V-DAC3 Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -8
(8) Current Monitor (BIASMON) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9
(9) PDGAIN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -9
(10) DAC_APC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9
(11) BIASGEN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9
(12) Temperature Sensor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -9
(13) ADC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9
(14) Power On Reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9
(15) On-chip Oscillator - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9
(16) OPTALM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -9
V. PACKAGE INFORMATION = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 10
(1) Package Type - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10
(2) Marking Information - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -10
(3) Package Outline Dimension - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10
VI. CIRCUIT DESCRIPTION = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 11
1.
2.
3.
4.
5.
Operational Description Notation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11
Operation Setting - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12
I-DAC, V-DAC Functional Part - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -13
APC Functional Part - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -14
4.1 APC_FF Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -14
4.2 APC_FB Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15
4.2.1 APC_FB Circuit Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - -16
4.2.2 Normalization of PD Monitoring Current - - - - - - - - - - - - - - - - - - - -16
4.2.3 DAC_APC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 17
4.2.4 APC_FB Dividing Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 17
4.3 APC Operation Setting - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -17
4.4 On-Chip Temperature Sensor (TEMPSENS) Characteristics - - - - - - - - - - - - - 23
4.5 Current Monitor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -24
Burst Mode Operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -25
5.1 Power Leveling [1] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 25
5.2 Power Leveling [2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 26
<MS0290-E-01>
-2-
2004/8
ASAHI KASEI
[AK2572]
6.
Alarm Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -27
6.1 TEMPALM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27
6.2 OPTALM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -27
6.3 CURRALM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27
6.4 EXTALM1, EXTALM2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -27
6.5 TXFAULT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 28
6.5.1 Target Alarm Setting of TXFAULT Output - - - - - - - - - - - - - - - - - -28
6.5.2 Operation at TXFAULT Detection - - - - - - - - - - - - - - - - - - - - - - - - - -28
7. Shutdown Control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -29
7.1 Shutdown Operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 29
7.2 Operation at Shutdown Release - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -29
8. Start-Up Setting in SFP Support Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -30
8.1 TXFAULT Detection at Power-Up and after Release from Shutdown - - - - - - -30
8.1.1 OPTALM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -30
8.1.2 EXTALM1, EXTALM2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -30
8.2 At Power-On (at TXDIS＝”L”) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -31
8.3 At Power-On (at TXDIS＝”H”) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 31
8.4 At TXDIS Detection / Release - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -32
8.5 At TXFAULT Detection / Release - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 33
9. Digital Interface Configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -34
9.1 Memory Configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -34
9.2 Write Protect Operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 35
9.3 Read / Write Operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -36
9.3.1 Byte Write - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 36
9.3.2 Page Write - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 36
9.3.3 Current Address Read - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -36
9.3.4 Random Read - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -36
9.3.5 Sequential Read - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -37
9.3.6 Data Change - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 37
9.3.7 Start / Stop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -37
9.4 EEPROM Configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -38
9.5 Register Configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 40
10. Operation Modes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -44
10.1 Self-Operation Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -44
10.2 Adjustment Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 44
10.3 EEPROM Access Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -44
10.4 Mode Control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -44
10.5 Operation Mode Change Commands - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45
10.6 Mode Protection - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45
11. Example of Adjusting Sequence - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 46
VII. EXTERNAL CIRCUIT EXAMPLE = = = = = = = = = = = = = = = = = = = = = = = = = = = = 47
<MS0290-E-01>
-3-
2004/8
ASAHI KASEI
[AK2572]
I. PIN DESCRIPTION
Each symbol at I/ O column in the following table means,
PWR : Power（VDD） or VSS, Ai : Analog input, Ao : Analog output,
Di : Digital input, Di_pu : Digital input with pulled-up resistor,
Do : Digital output, Do_od : Digital output (Open drain), Dio_od : Digital input/output (Open drain)
Pin# Pin Name
1
TEST1
2
TEST2
3
TEST3
4
DVDD
5
DVSS
6
7
8
9
10
11
12
13
14
15
Function
Input pin for AKM test. Connect it to DVSS for Normal operation.
Input pin for AKM test. Connect it to DVSS for Normal operation.
Input pin for AKM test. Connect it to DVSS for Normal operation.
Power supply for Digital circuit.
Ground for Digital circuit.
Alarms such as Optical output decline (OPTALM), Excessive LD
current (CURRALM), Exceptional temperature (TEMPALM) and
Irregular external signals (EXTALM1 and EXTALM2) can be
selected by EEPROM / Register setting as target alarms available on
TXFAULT-pin output.
When any of the selected alarms (ALM) is detected, TXFAULT-pin
TXFAULT becomes ”High-Z“ output, and it becomes “H“ level with a pulled-up
resistor connection. This pin is open-drain type and should be
connected to DVDD via a 4.7k ~ 10kΩ resistor.
With RE_SFP_SET＝“0“ (SFP support mode setting), TXFAULTpin output is held at “H“ level when any of the selected alarms is
detected till the shutdown request is released by “H“ to “L“ transition
on TXDIS-pin.
Serial data input / output pin for Digital interface.
This pin is open-drain type and should be connected to DVDD via a
SDA
4.7k ~ 10kΩ resistor.
I/O
Di
Di
Di
PWR
PWR
Note
Connect it
to DVSS
Connect it
Do_od to Pulled-up
resistor
Connect it
Dio_od to Pulled-up
resistor
Should not
SCL
Serial clock input for Digital interface
Di
be left open
Burst signal input. It is active during “H“ input period (valid data
Should not
BURST
Di
period). When this pin is not used, connect it to DVSS.
be left open
When this pin is at “H“ input, Bias current DAC (I-DAC2) output
and Modulation current DAC (I-DAC1 or V-DAC3) output are
disabled. Refer to Table 7-1 and Table 7-2.
At RE_SFP_SET＝“0“ (SFP support mode setting), a logical sum of
Should not
TXDIS
Di
TXFAULT output and TXDIS-pin input become a disable request.
be left open
At RE_SFP_SET＝“1“, TXDIS-pin input becomes a disable request.
When this pin is externally pulled-up, use a higher than 4.7kΩ
resistor. When this pin is not used, connect it to DVSS.
AVDD
Power supply for Analog circuit.
PWR
AVSS
Ground for Analog circuit.
PWR
Monitoring PD (Photo Diode) voltage input.
The detected monitor PD current is I to V converted by external
resistor and capacitor. Please adjust the cut-off frequency of an LPF
PDIN
Ai
to be within 5k ~ 10kHz which is composed of external resistor (Rpd)
and capacitor (Cpd).
When this pin is not used, it is recommended to connect it to AVSS.
Bias current monitor. A current multiplied by 0.012 [Typ.] of the
I-DAC2 output current is sourced from this pin. When to convert the
BIASMON
Ao
current to a voltage by an external resistor, select the resistor value
such that BIASMON-pin voltage≦1.3 V.
VSSBI
Ground for I-DAC2.
PWR
<MS0290-E-01>
-4-
2004/8
ASAHI KASEI
[AK2572]
Pin Description (Continued)
Pin# Pin Name
Function
LD Bias current output (Current-sink type : Maximum sink current
＝85.0 mA [Typ.]). The current value is set by I-DAC2.
16
IOUT2
Please operate the device under IOUT2-pin voltage≧(VDD－1.7 V)
condition. When the voltage on this pin becomes lower, a sink
current error becomes larger.
17
VSSBI
Ground for I-DAC2
18
VDDBI
Power supply for I-DAC2.
I-DAC1 current output (Current-source type : Maximum sourcing
current 10.2 mA [Typ.]).
When RE_MODV_SEL＝“0“, this becomes an LD modulation
current output and when RE_MODV_SEL＝“1“, it is I to V
19
IOUT1
converted and it can be used as an APD control voltage or a
reference voltage for LDD (Laser Diode Driver) etc.. Please operate
the device under IOUT1-pin voltage≦1.3 V. When the voltage on
this pin becomes higher, a sourcing current error becomes larger.
20
VDDMD Power supply for I-DAC1.
V-DAC3 voltage output pin (Maximum output voltage: 2.2 V [Typ.]).
When RE_MODV_SEL＝“0”, this voltage can be used as either an
APD control voltage or LDD reference voltage etc.. When
21
VOUT3
RE_MODV_SEL＝“1“, this outputs an LD modulation current
control voltage. Please connect an external RC filter (LPF : R＝1kΩ
and C＝0.01μF are recommended) to this pin.
PDMON is the Normalized PDIN voltage output pin.
Adjust RE_PDGAIN so that PDMON voltage is equal to 1.0 V [typ].
22
PDMON
When APC_FB function or OPTALM function is used,
RE_PDGAIN adjustment is required.
23 TEMPMON On-chip temperature sensor voltage output.
BIAS resistor connection pin.
24
BIAS
Connect this pin to AVSS via a 12kΩ±1% resistor.
Irregular external signal detect [1] input pin. A polarity of
EXTALM1 detection can be selected by RE_EXTALM1_POL.
25 EXTALM1
EXTALM1 can be set as a target TXFAULT output alarm by
RE_EXTALM1_SET. When this pin is not used, connect it to DVSS.
This pin functions as MOD_CTRL input pin when both
RE_SFP_SET＝“1“ and RE_PWR_LVL1_SET＝“1“.
This pin becomes EXTALM2 input pin when either RE_SFP_SET
＝“0“ or RE_PWR_LVL1_SET＝“0“.
When MOD_CTRL-pin function (Power leveling [1] control signal
input pin) is selected, Power leveling [1] is executed by a Hardware
EXTALM2 /
26
MOD_CTRL pin control. In this case, then, EXTALM2-related function is
automatically turned off.
When EXTALM2-pin function (Irregular external signal detection
[2] input pin) is selected, EXTALM2 is set as a target TXFAULT
output alarm by RE_EXTALM2_SET, and RE_EXTALM2_POL
sets the polarity of EXTALM2 detection. When this pin is not used,
connect it to DVSS.
27
TEST4
Output pin for AKM test. Leave it open for Normal operation.
Write protect control pin. This pin is internally pulled-up via a 20kΩ
[Typ.] resistor. WP-pin and R_WP_CTRL set the limitation of an
28
WP
accessible EEPROM space via Digital interface. Please refer to
Section 9.2 for details.
<MS0290-E-01>
-5-
I/O
Note
Ao
PWR
PWR
Ao
PWR
Ao
Connect it to
external RC
filter
Ao
Ao
Ao
Connect it to
a resistor
Di
Should not
be left open
Di
Should not
be left open
Do
Open
Di_pu
2004/8
ASAHI KASEI
[AK2572]
Ⅱ．ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Power Supply Voltage VDD
Ground Level
VSS
Input Voltage
VIN
Input Current
IIN
Storage Temperature
Tstg
Min.
- 0.3
0.0
VSS－0.3
- 10
- 55
Max.
6.0
0.0
VDD＋0.3
10
130
Unit
V
V
V
mA
℃
Note
AVDD, DVDD, VDDMD, VDDBI
AVSS, DVSS, VSSBI (Base Voltage)
Excluding VDD-pins
Excluding VDD-pins
Ⅲ．RECOMMENDED OPERATING CONDITIONS
Item
Operating Ambient Temperature
Symbol
Min.
Typ.
Max.
Unit
Note
℃
Ta
- 40
+ 85
VDD
3.0
3.3
3.5
V
3.3V (-9% / +6%)
Power Supply Voltage
VSS
0.0
0.0
0.0
V
Base Voltage
< Important Notice > Please pay attention not to keep the condition of VDD≦1.5V which makes that the Power
On Reset function of AK2572 cannot operate correctly, AK2572 supplies the abnormal LD current and the
possibility of damaging LD increases.
Ⅳ．ELECTRICAL CHARACTERISTICS
(1) Current Consumption
Item
Symbol
Min.
Typ.
Max.
Unit
Note
－
Current Consumption (All VDD-pins)
IDD
21
26
mA
[*1], [*2]
[*1] It doesn’t include the output current of I-DACs.
[*2] R_DACx＝FFh (x＝1~3), R_DAC1,2_GAIN＝1, R_DAC3_GAIN＝0, PDGAIN＝0dB, PDIN＝1V
(2) EEPROM Characteristics
Item
Min.
Max.
Unit
Condition
－
EEPROM Write Cycle
1000
times
[*]
－
Junction
temperature
Tj＝85℃
EEPROM Data Retention Time
10
year
[*] This parameter is characterized and is not 100% tested.
< Important Notice > The adjusted data in AKM factory are stored in advance at address location (Device
Address＝A6h, Address＝60h) for the offset voltage of the On-chip temperature sensor. If such excessive
temperature stress is to be applied to the AK2572 which exceeds a guaranteed EEPROM data retention
conditions (for 10 years at 85℃), it is important to read the pre-determined data in advance and to re-write the
same data back into EEPROM after an exposure to the excessive temperature environment. Even if the
exposure time is shorter than the retention time, any accelerated temperature stress tests (such as baking) are
performed, it is recommended to read the pre-set data first and to re-write it after the test. Access to unused
address locations is not functionally guaranteed. Please refer to Section 9.4, “EEPROM Configuration”.
(3) Digital Input / Output Pin DC Characteristics
Item
Symbol
Min.
High Level Input Voltage
VIH
2.0
Low Level Input Voltage
VIL
High Level Output Voltage VOH 0.9VDD
Max.
0.8
Low Level Output Voltage
VOL
0.4
Input Leakage Current １
Input Leakage Current 2
IL1
IL2
10
350
<MS0290-E-01>
-6-
Unit
V
V
V
Condition
IOH ＝ - 0.2mA
IOL＝1mA (SDA-pin, TXFAULT-pin)
V
IOL＝0.2mA (Excluding SDA, TXFAULT)
μA
Excluding WP-pin
μA
WP-pin
2004/8
ASAHI KASEI
[AK2572]
(4) Digital Input / Output Pin AC Characteristics (Serial Interface)
tF
tR
SCL
tSU.STA
tHD.DAT
tSU.STO
tSU.DAT
tHD.STA
SDA (IN)
tAA
tDH
tBUF
SDA (OUT)
Symbol
ｔSCL
ｔLOW
ｔHIGH
ｔI
ｔAA
ｔBUF
ｔHD.STA
ｔSU.STA
ｔHD.DAT
ｔSU.DAT
ｔR
ｔF
ｔSU.STO
ｔDH
ｔWR
Parameter
Min.
Clock Frequency, SCL
Clock Pulse Width Low
4.7
Clock Pulse Width High
4.0
Noise Suppression Time
Clock Low to Data Out Valid
0.1
Time before a New Transmission
4.7
Start Hold Time
4.0
Start Setup Time
4.7
Data Hold Time
0
Data Setup Time
200
Input Rise Time
Input Fall Time
Stop Setup Time
4.0
Data Out Hold Time
100
Write Cycle Time
[*] This parameter is characterized and is not 100% tested.
<MS0290-E-01>
-7-
Max.
100
100
4.5
1.0
0.3
10
Unit
kHz
μs
μs
ns
μs
μs
μs
μs
μs
ns
μs
μs
μs
ns
ms
Note
[*]
[*]
2004/8
ASAHI KASEI
[AK2572]
(5) I-DAC1 Characteristics
Item
Condition
Min.
Typ.
Max.
Unit
Note
Resolution
8
bit
Straight Binary
Input Code＝FFh
Maximum Output
IOUT1＝1.3V
9.4
10.2
11.0
mA
Current 1 (Source)
RE_DAC1_GAIN＝1
Input Code＝FFh
Maximum Output
IOUT1＝1.3V
0.94
1.02
1.10
mA
Current 2 (Source)
RE_DAC1_GAIN＝0
RE_MODV_SEL＝0
Current Supply at
IOUT1＝VSS
μA
10
Shutdown
TXDIS＝“H” [*]
IOUT1＝1.3V
μA
RE_DAC1_GAIN＝1
1 LSB Current Step 1
40.0
IOUT1＝1.3V
μA RE_DAC1_GAIN＝0
1 LSB Current Step 2
4.0
IOUT1＝1.3V
DNL
-1
+1
LSB Input Code＝10h~FFh
IOUT1＝1.3V
INL
-2
+2
LSB Input Code＝10h~FFh
[*] At RE_SFP_SET＝“0“, a logical sum of TXFAULT output and TXDIS-pin input becomes a disable request.
Refer to Table 7-1.
(6) I-DAC2 Characteristics
Item
Condition
Min.
Typ.
Max.
Unit
Note
Resolution
8
bit
Straight Binary
Input Code＝FFh
Maximum Output
IOUT2＝VDD－1.7V
78.2
85.0
91.8
mA
Current 1 (Sink)
RE_DAC2_GAIN＝1
Input Code＝FFh
Maximum Output
IOUT2＝VDD－1.7V
39.1
42.5
45.9
mA
Current 2 (Sink)
RE_DAC2_GAIN＝0
Current Supply at
IOUT2＝VDD
μA
TXDIS＝“H” [*]
100
Shutdown
μA RE_DAC2_GAIN＝1
1 LSB Current Step 1 IOUT2＝VDD－1.7V
333
μA RE_DAC2_GAIN＝0
1 LSB Current Step 2 IOUT2＝VDD－1.7V
167
IOUT2＝VDD－1.7V
DNL
-1
+1
LSB Input Code＝10h~FFh
IOUT2＝VDD－1.7V
INL
-2
+2
LSB Input Code＝10h~FFh
[*] At RE_SFP_SET＝“0“, a logical sum of TXFAULT output and TXDIS-pin input becomes a disable request.
Refer to Table 7-1.
(7) V-DAC3 Characteristics
Item
Condition
Min.
Typ.
Max.
Unit
Note
Resolution
8
bit
Straight Binary
Input Code＝FFh
Maximum Output
10kΩ (to VSS)
1.11
1.20
1.29
V
Voltage 1
RE_DAC3_GAIN＝1
Input Code＝FFh
Maximum Output
10kΩ (to VSS)
2.03
2.20
2.37
V
Voltage 2
RE_DAC3_GAIN＝0
Minimum Output
10kΩ (to VDD)
Input Code＝00h
0.2
V
Voltage
RE_MODV_SEL＝1
Voltage Supply at
10kΩ (to VDD)
0.2
V
Shutdown
TXDIS＝“H” [*]
10kΩ (to VSS)
RE_DAC3_GAIN＝1
1 LSB Voltage Step 1
4.7
mV
10kΩ (to VSS)
RE_DAC3_GAIN＝0
1 LSB Voltage Step 2
8.6
mV
10kΩ (to VSS)
DNL
-1
+1
LSB Input Code＝20h~FFh
10kΩ (to VSS)
INL
-2
+2
LSB Input Code＝20h~FFh
[*] At RE_SFP_SET＝“0“, a logical sum of TXFAULT output and TXDIS-pin input becomes a disable request.
Refer to Table 7-1.
<MS0290-E-01>
-8-
2004/8
ASAHI KASEI
[AK2572]
(8) Current Monitor (BIASMON)
Item
Condition
BIASMON Current
Maximum Output
Current 1 (Source)
Maximum Output
Current 2 (Source)
(9) PDGAIN
Item
PDIN Input Range
PDGAIN Gain Error
Min.
BIASMON＝1.3V
Typ.
Max.
0.012
Unit
Time
Note
Based on I-DAC2
Input Code＝FFh
Input Code＝FFh
RE_DAC2_GAIN＝1
Input Code＝FFh
RE_DAC2_GAIN＝0
BIASMON＝1.3V
0.94
1.02
1.10
mA
BIASMON＝1.3V
0.47
0.51
0.55
mA
Condition
PDMON＝1V±10%
PDIN→PDMON
Min.
0.08
- 0.5
Typ.
Max.
2.5
+ 0.5
Unit
V
dB
Condition
Test mode, PDMON-pin
Test mode, PDMON-pin
Test mode, PDMON-pin
Min.
1.135
0.752
-1
Typ.
1.195
0.792
Max.
1.255
0.832
+1
Unit
V
Condition
12kΩ±1%
Min.
Typ.
1.2
Max.
Unit
V
Note
Unit
mV/℃
V
Note
[*]
(10) DAC_APC
Item
Maximum Output Voltage
Minimum Output Voltage
DNL
(11) BIASGEN
Item
BIAS-pin Voltage
(12) Temperature Sensor
Item
Condition
Min.
Typ.
Max.
Voltage Slope
TEMPMON-pin Voltage - 12.14 - 11.56 - 10.98
Ta＝35 ℃
Offset Adjustment Target
1.215
[*] This parameter is characterized and is not 100% tested.
Note
Note
LSB
(13) ADC
Item
Resolution
Maximum Input Voltage
Minimum Input Voltage
DNL
INL
(14) Power On Reset
Item
Detect Voltage
(15) On-chip Oscillator
Item
Clock Frequency
(16) OPTALM
Item
OPTALM Detect
Level
<MS0290-E-01>
Condition
Min.
2.09
Typ.
8
2.20
0
-1
-2
Max.
Note
Straight Binary
±5%
+1
+2
Unit
bit
V
mV
LSB
LSB
2.31
Condition
Min.
2.3
Typ.
2.5
Max.
2.7
Unit
V
Note
Condition
Test mode
Min.
Typ.
8.192
Max.
Unit
MHz
Note
Min.
1 / 3.2
1 / 4.3
1 / 6.4
1 / 7.5
Typ.
1/3
1/4
1/6
1/7
Max.
1 / 2.8
1 / 3.7
1 / 5.6
1 / 6.5
Condition
1/3 setting, PDGAIN＝0dB
1/4 setting, PDGAIN＝0dB
1/6 setting, PDGAIN＝0dB
1/7 setting, PDGAIN＝0dB
-9-
Unit
Time
Time
Time
Time
Note
2004/8
ASAHI KASEI
[AK2572]
Ⅴ．PACKAGE INFORMATION
(1) Package Type :
28 pin - QFN
(2) Marking Information :
a） PIN#1 Indication : ○
b） Marking Code :
AK2572
c） Date Code :
YWWX (4 Digit)
Y:
Year
WW : Week (1 ~ 52)
X:
Manufacturing Identification
AK２５７２
ＹＷＷＸ
45°
5.0±0.10
6
55
5.0±0.10
AX
M 0 .3
0.
C
5.2±0.20
0.60±0.10
0.
4-
5.2±0.20
+
-0 0 .1
.2
(3) Package Outline Dimension
45°
<MS0290-E-01>
+0.17
-0.28
+0.20
-0.10
0.80
-0.02
+0.03
0.05
0.02
0.21±0.05
0.50
0.05 M
0.78
0.22±0.05
-10-
2004/8
ASAHI KASEI
[AK2572]
Ⅵ．CIRCUIT DESCRIPTION
1. Operational Description Notation
In order to distinguish various pre-set parameter sources from EEPROM, Registers or Device pins, “ Identifier –
Main name “ notation is used in the AK2572 circuit description as shown in Table 1-1. For ease of operational
description, internal signals are sometimes defined which are all expressed in small letters.
Table 1-1 Definition of Terms
Identifier
Register
R_
EEPROM
E_
Either or Both Register
or/and EEPROM
RE_
BLOCK
Internal node
Main name
Remark
REGISTER name
Indicating Register
（All Capital）
EEPROM name
Indicating EEPROM
（All Capital）
REGISTER name
Indicating either or both
EEPROM name
Register or/and EEPROM
（All Capital）
BLOCK name
（All Capital）
signal name
（All small letter）
Example
R_DAC2
E_BIAS_TC
RE_DAC3_GAIN
I-DAC1
vpd
Identification words are assigned to the name of Register / EEPROM as shown in Table 1-2 so that each
function can be easily assumed by each name.
Table 1-2 Identification Word Classification
Classification
Suffix
Contents
Example
Identification
_SET
Functional setting
RE_APC_FF_SET
suffix
_SEL
Functional selection
E _MODV_SEL
_TC
Temperature compensation value
E_MOD_TC
_WIN
Window width setting by ALM set
RE_TEMP_WIN
RE_APC_TRGT
_TRGT Target value
Functional
APC
APC related, common for I-DAC1, I-DAC2 and V-DAC3 RE_APC_FF_SET
identification
DAC
I-DAC, V-DAC related
E_DAC_SET
word
BIAS
Bias current ( I-DAC2 ) related
R_BIAS_FF
MOD
MOD current ( I-DAC1, V-DAC3 ) related
E_MOD_TC
EXTRA EXTRA DAC ( DAC not set to MOD ) related
R_EXTRA
TEMP Temperature sensor related
R_TEMP
PWR
Power leveling function related
R_PWR_SEL
ALM
Alarm related
R_TEMPALM_SET
FF
FeedForward function
RE_APC_FF_SET
FeedBack function
FB
RE_APC_FB_SET
FB dividing
FBRT
R_MOD_FBRT
TIMER Timer related
R_TIMER_OPTALM
Gain adjust
GAIN
E_DAC1_GAIN
BURST Burst mode support function related
E_BURST_ALM
Status signals
ST
R_TXFLT_ST
Signal polarity
POL
E_EXTALM1_POL
< Note > Numeric values in the circuit description of the AK2572 are expressed in Binary, Decimal or
Hexadecimal. In order to identify the differences, setting values in Hexadecimal are expressed with a small
character “h“ suffix.
<MS0290-E-01>
-11-
2004/8
ASAHI KASEI
[AK2572]
2. Operation Setting
The AK2572 can operate following functions as shown in Table 2-1 by EEPROM / Register setting. For further
details, please refer to the circuit description at the next page and thereafter.
Table 2-1 AK2572 Operation Setting
Set-up
RE_BURST_SET
RE_SFP_SET [*3]
RE_PWR_LVL1_SET [*3]
RE_PWR_LVL2_SET
RE_APC_FF_SET
RE_APC_FB_SET
RE_OPTALM_SET
RE_CURRALM_SET
Continuous mode
Burst mode
SFP_MSA support
Shutdown request
Related setting
0
1
0
0
00 ~ 11 （0 ~ 3）
00 ~ 11 （0 ~ 3）
0/1
0/1
○
×
○
×
Logical sum (ORed)
TXDIS
of TXFAULT and
TXDIS
1
1
0
0
1
1
0
11 （3）
0
0
0
×
○
×
TXDIS
Power leveling [1]
×
×
○
EXTALM2
/ MOD_CTRL-pin
EXTALM2
EXTALM2
MOD
_CTRL
Power leveling [2]
×
○
×
APC_FF function
APC_FB function
□ ［*1］
□ ［*1］
○ ［*2］
× ［*2］
OPTALM
□ ［*1］
× ［*2］
CURRALM
□ ［*1］
× ［*2］
MOD_CTRL-pin
E_MOD_TC［1］
E_MOD_TC［2］
RE_PWR_SEL
E_BIAS_TC［0］~［3］
E_MOD_TC［0］~［3］
RE_OPTALM
RE_TIMER_OPTALM
E_CURRALM_BIAS_TC
E_CURRALM_MOD_TC
［*1］ These functions are determined by the corresponding EEPROM / Register setting. Therefore the operations
of “□“ depend on the user’s setting.
［*2］ In Burst mode setting (RE_BURST_SET＝“1”, RE_SFP_SET＝”1”), it is assumed that only APC_FF
function is used and no APC_FB function is used (Monitor PD, CURRALM and OPTALM are not used).
[*3] Setting of RE_SFP_SET＝“0” and R_PWR_LVL1_SET＝“1“ is prohibited.
<MS0290-E-01>
-12-
2004/8
ASAHI KASEI
[AK2572]
3. I-DAC, V-DAC Functional Part
The AK2572 equips Current source type I-DAC1 (Max. sourcing current＝10.2 mA [Typ.]) and Voltage output
type V-DAC3 (Max. output voltage＝2.2 V [Typ.]) for the LD modulation current setting, and Current sink type
I-DAC2 (Max. sink current＝85.0 mA [Typ.] ) for the bias current setting. Selection of enable / disable each DAC
is set by RE_DAC_SET. Output current of I-DAC1 (Max. value＝10.2 mA / 1.02 mA [Typ.]) and I-DAC2 (Max.
value＝85.0 mA / 42.5 mA [Typ.]), and output voltage of V-DAC3 (Max. value＝2.2 V / 1.2 V [Typ.]) can be
switched by gain setting. This gain switching allows to lower current consumption and to improve the accuracy
per 1 LSB. In Tables 3-1 ~ 3-3, the characteristics of I-DAC2, I-DAC1 and V-DAC3 are shown.
I-DAC2 directly sets the LD bias current. A current multiplied by a factor of 0.012 [Typ.] of I-DAC2 set value is
output (Current source) on BIASMON-pin.
Table 3-1 I-DAC2 characteristics (I-DAC2 is set “Enabled” / “Disabled” by RE_DAC_SET [1]＝“1” / “0”)
Max. output current (Code＝FFh)［Typ］ Range ［Typ］ Current/step ［Typ］
RE_DAC2_GAIN Gain
333 μA
1
1
85.0 mA
0 ~ 85.0 mA
167 μA
0
1/2
42.5 mA
0 ~ 42.5 mA
[Note] I-DAC2 characteristics : Resolution＝8 bits, DNL＝±1 LSB (DAC code＝10h ~ FFh)
Output current variation at Maximum DAC code (FFh)＝Typ.±8 %
Temperature compensation data (Retained in EEPROM), which are set for I-DAC1 and V-DAC3, can be
selected by RE_MODV_SEL setting as shown in Table 3-4.
When E_MOD_TC (128 address locations) is assigned as the setting data, I-DAC1(RE_MODV_SEL＝“0”)
generates a reference current of the modulation current to external Laser Diode Driver (LDD), and V-DAC3
(RE_MODV_SEL＝“1”) generates a reference voltage of the Modulation current to external LDD. A voltage
driver type LDD can also be adopted by converting an I-DAC1 output current to a voltage by external
resistors or by using V-DAC3 output voltage. When E_EXTRA_TC (32 address locations) is assigned as the
setting data, I-DAC1 output (RE_MODV_SEL＝“1”) or V-DAC3 output (RE_MODV_SEL＝“0”) can be used
as APD control voltage or LDD reference voltage etc.. When temperature compensation by E_EXTRA_TC is
not required, same data should be written at all address locations.
Table 3-2 I-DAC1 characteristics (I-DAC1 is set “Enabled” / “Disabled” by RE_DAC_SET [0]＝“1” / “0”)
RE_DAC1_GAIN Gain Max. output current (Code＝FFh)［Typ］ Range ［Typ］ Current / step［Typ］
40 μA
1
1
10 .2 mA
0 ~ 10 .2 mA
4 μA
0
1/10
1.02 mA
0 ~ 1.02 mA
[Note] I-DAC1 characteristics : Resolution＝8 bits, DNL＝±1 LSB (DAC code＝10h ~ FFh)
Output current variation at Maximum DAC code (FFh)＝Typ.±8 %
Table 3-3 V-DAC3 characteristics (V-DAC3 is set “Enabled” / “Disabled” by RE_DAC_SET [2]＝“1” / “0”)
RE_DAC3_GAIN Gain
Max. output voltage (Code＝FFh)［Typ］ Range ［Typ］ Voltage / step［Typ］
1
1.2 / 2.2
1.2 V
0 ~ 1.2 V
4.7 mV
0
1
2.2 V
0 ~ 2.2 V
8.6 mV
[Note] V-DAC3characteristics : Resolution＝8 bits, DNL＝±1 LSB (DAC code＝20h ~ FFh)
Output voltage variation at Maximum DAC code (FFh)＝Typ.±8 %
Table 3-4 RE_MODV_SEL setting
RE_MODV_SEL
I-DAC1
V-DAC3
0
E_MOD_TC
E_EXTRA_TC
1
E_EXTRA_TC
E_MOD_TC
[Note] Although E_MOD_TC has 128 address locations and E_EXTRA_TC has 32 address locations,
temperature resolution of each temperature compensation data is 0.75 ℃ [typ.] because of the
temperature compensation data is derived from a linear interpolation method (Refer to Section 4.1).
<MS0290-E-01>
-13-
2004/8
ASAHI KASEI
[AK2572]
4. APC Functional Part
Circuit configuration of the APC part is shown in Figure 4-1. The AK2572 is formed with APC_FF function
which sets the programmed current with corresponding to the detected temperature by On-chip temperature
sensor and APC_FB function which controls with feedback function to keep the monitoring photo diode current
constant. By properly combining APC_FF and APC_FB functions together by EEPROM / Register setting, a
proper LD Bias current / Modulation current can be generated.
Figure 4-1 APC Circuit Block Diagram
TEMPMON
On-chip temperature sensor
offset adjusting
(RE_TEMP_OFFSET)
TEMPALM threshold
(E_TEMPALM)
TEMP
ALM
V-DAC3 operation setting (RE_DAC_SET[2])
V-DAC3 gain setting (RE_DAC3_GAIN)
Tempalm
I-DAC1,V-DAC3 data selection
(RE_MODV_SEL) R_DAC3
V-DAC3
VOUT3
EXTRA_DAC value (R_EXTRA)
Temp. sensor
(TEMPSENS)
ADC
(Time sharing)
Burst mode setting (RE_BURST_SET)
Temperature
equivalent value
(R_TEMP)
EEPROM
MOD: APC_FF value (R_MOD_FF)
+
MOD data
MOD: APC_FB dividing
(RE_MOD_FBRT)
I-DAC1 operation setting
(RE_DAC_SET[0])
I-DAC1 gain setting
(RE_DAC1_GAIN)
IMOD
BURST_
CONTROL
BURST
EXTALM polarity setting
(RE_EXTALM1_POL)
(RE_EXTALM2_POL)
EXTALM1
Pin setting
(RE_SFP_SET）
(RE_PWR_LVL1_SET）
EXTALM
EXTALM2
/MOD_CTRL
APC_FB initial value setting
(RE_APC_INIT_SET)
Power Leveling[1] setting
(RE_PWR_LVL1_SET)
(RE_SFP_SET)
Extalm1
Extalm2 Power Leveling[2] setting
(RE_PWR_LVL2_SET)
(RE_PWR_SEL)
Digital Filter
APC_
COMP
PDGAIN setting
(RE_PDGAIN)
BIAS: APC_FB dividing
APC_FB setting
I-DAC2 operation setting
(RE_APC_FB_SET) (RE_BIAS_FBRT)
(RE_DAC_SET[1])
I-DAC2 gain setting
K_BIAS
(RE_DAC2_GAIN)
_FBRT
BIAS: APC_FF value
(R_BIAS_FF)
Rpd
+
BIAS data
(R_DAC2)
1/N
1/s
APC target
(RE_APC_TRGT)
vpd
DAC_APC
vapc_ref
IBIAS
IOUT2
BIASMON
x 0.012
Over current threshold
(RE_CURRALM_MOD)
(RE_CURRALM_BIAS)
CURRALM
Curralm
R_DAC1/R_DAC3
R_DAC2
OPALM threshold (RE_OPTALM)
ATT
IOUT1
I-DAC2
APC_FB value
(R_APC_FB)
PDIN
PDGAIN
Cpd
R_DAC1
I-DAC1
Mod_Ctrl
PDMON
Monitor
PD
K_MOD
_FBRT
APC_FF setting
(RE_APC_FF_SET)
Bｕｒｓｔ_ｃｔｒｌ
OPTALM
_COMP
Optalm
optalm_ref
4. 1 APC_FF Function
APC_FF functional block diagram is shown in Figure 4-2. Output voltage of On-chip temperature sensor, which
responds to the detected temperature, is A-to-D converted (8 bits) in every temperature detection cycle (64 msec
[Typ.]). The resulting data (R_TEMP) is used as an EEPROM address and the data (8 bits) retained in
EEPROM at that address location is read out. The read out data is set to DAC and by supplying a proper
current to LD in response to temperature characteristics of each LD, APC_FF function is realized as in the
procedure above. Namely, the EEPROM address corresponds to temperature and the data corresponds to the
bias current and the modulation current at that temperature.
Although allocated EEPROM space for APC_FF is 7 bits (128 address locations), it is extended to 8 bits
equivalent data (256 address locations) by utilizing a linear interpolation of the current programming data as
shown in the following equation.
< Linear interpolation of E_BIAS_TC and E_MOD_TC >
Given that the detected temperature data are R_TEMP［7:0］＝z＝2x, 2x+1, R_TEMP［7:1］＝x, and the
temperature compensated data retained in EEPROM are E_BIAS_TC(x), E_MOD_TC(x), and the data
derived from linear interpolation are R_BIAS_FF(z), R_MOD_FF(z) respectively,
R_BIAS_FF(z)＝E_BIAS_TC(x－1)＋｛E_BIAS_TC(x)－E_BIAS_TC(x－1)｝×R_TEMP［0］/ 2
R_MOD_FF(z)＝E_MOD_TC(x－1)＋｛E_MOD_TC(x)－E_ MOD _TC(x－1)｝×R_TEMP［0］/ 2
But at x＝0 (R_TEMP［7:0］＝z＝0, 1), E_BIAS_TC(x)＝E_BIAS_TC(x－1)＝E_BIAS_TC(0)
E_MOD_TC(x)＝E_MOD_TC(x－1)＝E_MOD_TC(0)
<MS0290-E-01>
-14-
2004/8
ASAHI KASEI
[AK2572]
< Linear interpolation of E_EXTRA_TC >
Given that the detected temperature data are R_TEMP［7:0］＝z＝8y, 8y+1, ･･･, 8y+7, R_TEMP［7:3］＝y,
and the temperature compensated data retained in EEPROM is E_EXTRA_TC(y), and data calculated by
linear interpolation is R_EXTRA(z) (DAC loading E_EXTRA_TC data is selected by RE_MODV_SEL ),
R_EXTRA(z)＝E_EXTRA_TC(y－1)＋｛E_EXTRA_TC(y)－E_EXTRA_TC(y－1)｝×R_TEMP［2:0］/ 8
But at y＝0 (R_TEMP［7:0］＝z＝0 ~ 7), E_EXTRA_TC(y)＝E_EXTRA_TC(y－1)＝E_EXTRA_TC(0)
In order to keep the optical power of LD constant by APC_FF method, regardless of environmental temperature
changes, it is necessary to write and store the data of Bias current and Modulation current at each in the
temperature-corresponding EEPROM address when to adjust each LD module. In normal operation, On-chip
oscillator for temperature compensation of the current to drive LD modules automatically executes the
temperature detection and the current setting.
Those temperature compensated data for Bias current, Modulation current and EXTRA_DAC which are all
derived from the linear interpolation, have approximately 0.75 ℃ resolution and can automatically adjust LD
current and reference voltage for external circuit in approximately 0.75 ℃ step. The On-chip temperature sensor
is designed to cover the temperature range from - 40 ℃ ~ +115 ℃ under the ADC operating voltage range (0 ~
2.2 V [Typ.]). As to the relation between temperature sensor and ADC code, please refer to Section “4.4 On-chip
Temperature Sensor Characteristics“.
Figure 4-2 APC_FF Functional Block Diagram
Read out the data in
EEPROM with referring
Digital code as EEPROM
address
Output voltage from
TEMPSENS is
A-to-D converted
ADC
(8bit)
On-chip Temperature
Sensor (TEMPSENS)
R_TEMP[7:1]
Set the read out data into
I-DAC1(V-DAC3) and
I-DAC2, then control LD
current
R_MOD_FF
EEPROM
I-DAC1
(V-DAC3)
LDD
Imod
LD
ADC output
R_TEMP[7:0]
R_BIAS_FF
I-DAC2
Digital code changes in
response to temperature
change
Ibias
Address
Data
Temperature t [℃]
Voltage V [V]
TEMPSENS output
Output voltage proportionally
changes in response to
temperature change
Temperature t [℃]
Memory for Imod
(I-DAC1 or V-DAC3)
128 address
R_MOD_FF, R_BIAS_FF (Linear interpolation of APC_FF data):
R(z) = E(x-1) + {E(x)-E(x-1)} *
Memory for Ibias
(I-DAC2)
128 address
R_TEMP[0]
2
E(x): E_BIAS_TC or E_MOD_TC at x=R_TEMP[7:1]
R(z): R_BIAS_FF or R_MOD_FF at z=R_TEMP[7:0]=2x, 2x+1
A proper current value data
should be written in advance
at each address location
which corresponds to each
temperature value
4.2 APC_FB Function
APC_FB functional block diagram is shown in Figure 4-3.
In APC_FB block, an amplified PDIN voltage by gain value (vpd) and DAC_APC output voltage (vapc_ref) are
compared at APC_COMP, and the feedback current (R_APC_FB) is calculated at digital filter so that vpd and
vapc_ref are equal. The cut-off frequency (fpd), which is fixed by Rpd and Cpd, should be set as follows:
5 kHz＜fpd＜10 kHz
<MS0290-E-01>
-15-
2004/8
ASAHI KASEI
[AK2572]
Figure 4-3 APC_FB Functional Block Diagram
APC_FF
TEMPSENS
ADC
R_TEMP
+
R_DAC2
R_DAC1/R_DAC3
APC_FB Initial value setting is possible in
response to temperature at the start-up
PDMON
A proper APC_FB initial value setting
can shorten the start-up time
512kHz [Typ.]
Monitor
PD
PDGAIN
Rpd
APC_
COMP
comp_out
Dispersion of monitor PD current
is cancelled and a normalized
voltage is output on PDMON-pin
Cpd
RE_APC_TRGT
DAC_APC
R_APC_FBIV
DIGITAL FILTER
vpd
PDIN
DAC
EEPROM
1/N
1/s
R_APC_FB
DAC code is incremented or
decremented by 1 LSB step in order
to prevent the excessive current
vapc_ref
4.2.1 APC_FB Circuit Block Diagram
The operation of each block is shown in Table 4-1.
Table 4-1 APC_FB Block Diagram Descriptions
Block
Function
Note
Amplified PDIN voltage by gain value (vpd) and APC target value (vapc_ref) are
APC_
compared and if “vpd＜vapc_ref”, UP (increment) request or if “vpd≧vapc_ref”, DOWN
COMP
(decrement) request is output on digital filter. The comparison is made at 512 kHz [Typ.].
DIGITAL From the APC_COMP result, R_APC_FB value is calculated so that vpd and vapc_ref
FILTER are equal.
Amplified PDIN voltage by gain value is output on PDMON-pin. Input range is 0.08 V ~
PDGAIN 2.5V. Adjust the gain so that PDMON output voltage is equal to 1.0V [Typ.]. When to set
a normalized voltage lower than 1.0 V, adjust it by utilizing external resistor-divider etc..
APC reference voltage (vapc_ref) is output. Output voltage is adjustable by
DAC_APC RE_APC_TRGT setting. APC_FB operates such that the amplified PDIN voltage by gain
value equals to DAC_APC output.
4.2.2 Normalization of PD Monitoring Current
A monitor PD current is converted into average voltage by an external resistor and a capacitor and it is fed on
PDIN-pin. Input voltage range of PDIN at initial adjustment is listed in Table 4-2.
PDIN voltage is amplified by gain value at PDGAIN block and it is output on PDMON-pin. Adjust PDGAIN so
that output voltage on PDMON-pin is 1.0 V [Typ.]. In Table 4-3, adjustable range of RE_PDGAIN is listed.
When a lower than 1.0 V [Typ.] is required as a normalized voltage, voltage-divide it by an external
resistor-divider etc..
Table 4-2 PDIN Input Condition
Item
Min.
PDIN input voltage
0.08V
Table 4-3 PDGAIN Setting
RE_PDGAIN
00 0000 (00h)
00 0001 (01h)
･･･
11 1110 (3Eh)
11 1111 (3Fh)
<MS0290-E-01>
Max.
2.5V
Set-up gain ［Typ.］
23.5 dB
23.0 dB
･･･
- 7.5 dB
- 8.0 dB
-16-
Note
Note
0.5 dB / step
2004/8
ASAHI KASEI
[AK2572]
4.2.3 DAC_APC
DAC_APC outputs APC_FB reference voltage (vapc_ref). vapc_ref is adjusted by RE_APC_TRGT.
The relation of RE_APC_TRGT and vapc_ref is shown in Table 4-4.
Table 4-4 DAC_APC Setting
DAC_APC output : vapc_ref ［Typ.］
R_APC_TRGT
0 0000 (00h)
0.792 V
･･･
･･･
0 1111 (0Fh)
0.987 V
1 0000 (10h)
1.000 V
1 0001 (11h)
1.013 V
･･･
･･･
1 1111 (1Fh)
1.195 V
Note
13mV / step
4.2.4 APC_FB Dividing Function
The AK2572 has a function to divide the R_APC_FB value into both Bias current and Modulation current,
which is calculated by APC_FB function. By utilizing this function, the extinction ratio can be kept constant by
applying feedback operation on Bias and Modulation currents.
Block diagram in Figure 4-4 and the coefficient factor used for dividing calculation in Table 4-5 are shown.
Figure 4-4 APC Feedback Dividing Block Diagram
RE_DAC1_GAIN
(RE_DAC3_GAIN)
RE_MOD_FBRT
R_APC_FB
K_MOD
_FBRT
R_MOD_FB
K_BIAS
_FBRT
R_BIAS_FB
RE_BIAS_FBRT
I-DAC1
(V-DAC3)
I-DAC2
Imod
(Vmod)
Ibias
RE_DAC2_GAIN
Table 4-5 K_BIAS_FBRT, K_MOD_FBRT
RE_APC_FB_SET
K_BIAS_FBRT
00 (0)
0
01 (1)
0
10 (2)
1
K_MOD_FBRT
0
1
0
Note
Without Feed Back (FB)
FB on Modulation current control only
FB on Bias current control only
FB ratio is divided for both Bias and
11 （3）
R_MOD_FBRT/128
R_BIAS_FBRT/128
Modulation currents [*]
[*] R_BIAS_FBRT≦127, R_MOD_FBRT≦127 (Be noted that full range of APC_FB current from I-DACs is
limited since the dividing coefficients are mutually multiplied)
4.3 APC Operation Setting
Combination of APC function is set by RE_APC_FF_SET and RE_APC_FB_SET. Setting examples are
shown in Table 4-6 and Figures 4-5 ~ 4-13. Handling of the data, which are retained in the temperature
compensated Bias data space (E_BIAS_TC) and the temperature compensated Modulation data space
(E_MOD_TC), is automatically altered by APC setting. Relation between APC setting and the data retained in
EEPROM space is listed in Table 4-7. As to the memory space of E_BIAS_TC and E_MOD_TC, please refer to
Table 9-3. Lists of the data for each APC combination are shown in Table 4-8 and 4-9.
RE_APC_FF_SET is configured with 2 bits and it selects the I-DAC for FF (Feed Forward) setting.
RE_APC_FB_SET is configured with 2 bits and it selects the I-DAC for FB (FeedBack) setting.
The upper bit shows the BIAS side and the lower bit shows the MOD (Modulation) side.
<MS0290-E-01>
-17-
2004/8
ASAHI KASEI
[AK2572]
Table 4-6 APC Operation Setting Examples
RE_APC RE_APC
BIAS
MOD
_FF_SET _FB_SET Current Current
Note
Figure
Set MOD (Modulation) for FF (Feed Forward) setting.
Degraded LD characteristic is compensated by BIAS
01
10
FB
FF
only. Initial value of BIAS FB (FeedBack) can be 4-5
(1)
(2)
programmed in response to a start-up temperature
(Set by RE_APC_INIT_SET).
Set BIAS for FF setting.
10
01
Degraded LD is compensated by MOD only. Initial
FF
FB
4-6
(2)
(1)
value of MOD FB can be programmed in response to
a start-up temperature (Set by RE_APC_INIT_SET).
11
00
Set both BIAS and MOD for FF setting. No
FF
FF
4-7
(3)
(0)
compensation of degraded LD is made.
11
01
Set both BIAS and MOD for FF setting.
FF
FF+FB
4-8
(3)
(1)
Compensation of degraded LD is made by the MOD.
11
10
Set both BIAS and MOD for FF setting.
FF+FB
FF
4-9
(3)
(2)
Compensation of degraded LD is made by BIAS.
Compensation of degraded LD is made in accordance
00
11
with the dividing coefficient for BIAS and MOD initial
FB
FB
4-10
(0)
(3)
value of FB can be programmed in response to a
start-up temperature (Set by RE_APC_INIT_SET).
MOD outputs a current that is sum of the divided FB
current and the FF setting current.
01
11
BIAS outputs a current that is proportional to the
FB
FF+FB
4-11
(1)
(3)
divided FB current. Initial value of BIAS FB can be
programmed in response to a start-up temperature
(Set be RE_APC_INIT_SET).
BIAS outputs a current that is sum of the divided FB
current and the FF setting current.
10
11
FB
FF+FB
MOD outputs a current that is proportional to the 4-12
(2)
(3)
divided FB current. APC_FB initial value setting is
prohibited in this setting [*].
Both in BIAS and MOD, a current that is
11
11
proportional to the divided FB is added to the FF
FF+FB
FF+FB
4-13
(3)
(3)
setting current and compensation of degraded LD is
made by the FB current.
[*] RE_APC_INIT_SET＝“1” setting is prohibited when RE_APC_FF_SET＝”10 (2)” and RE_APC_FB_SET
＝”11 (3)” (BIAS＝FF＋FB / MOD＝FB)
Fig.4-5 Setting Example 1 (BIAS＝FB,MOD＝FF)
RE_DAC1_GAIN
(RE_DAC3_GAIN)
R_MOD_FF
R_MOD_FB
=0
R_APC_FB
I-DAC1(V-DAC3)
R_MOD
0
R_BIAS_FB
=R_APC_FB
Imod
(Vmod)
R_MOD_FB
=R_APC_FB
R_APC_FB
I-DAC1(V-DAC3)
R_MOD
1
R_BIAS_FB
=0
Ibias
85/255
R_BIAS=R_BIAS_FB=R_APC_FB
G_DAC1
(G_DAC3)
RE_DAC1_GAIN
(RE_DAC3_GAIN)
R_MOD_FF=0
I-DAC2
R_BIAS_FF=0
<MS0290-E-01>
10/255
(2.2/255)
R_BIAS
1
R_MOD=R_MOD_FF
Fig.4-6 Setting Example 2 (BIAS＝FF,MOD＝FB)
G_DAC2
R_BIAS=R_BIAS_FF
-18-
Ibias
85/255
R_MOD=R_MOD_FB=R_APC_FB
Imod
(Vmod)
I-DAC2
R_BIAS_FF
RE_DAC2_GAIN
G_DAC1
(G_DAC3)
R_BIAS
0
G_DAC1= 1 or 0.1
G_DAC2= 1 or 0.5
G_DAC3= 1 or 1.2/2.2
10/255
(2.2/255)
G_DAC2
RE_DAC2_GAIN
G_DAC1= 1 or 0.1
G_DAC2= 1 or 0.5
G_DAC3= 1 or 1.2/2.2
2004/8
ASAHI KASEI
[AK2572]
Fig.4-7 Setting Example 3 (BIAS＝FF,MOD＝FF)
RE_DAC1_GAIN
(RE_DAC3_GAIN)
R_MOD_FF
R_MOD_FB
=0
R_APC_FB
I-DAC1(V-DAC3)
R_MOD
0
R_BIAS_FB
=0
Fig.4-8 Setting Example 4 (BIAS＝FF,MOD＝FF+FB)
10/255
(2.2/255)
G_DAC1
(G_DAC3)
Imod
(Vmod)
R_APC_FB
0
R_MOD
R_BIAS_FB
=0
R_BIAS
1
Ibias
G_DAC2
85/255
R_BIAS_FF
R_MOD=R_MOD_FF
10/255
(2.2/255)
Imod
(Vmod)
Ibias
G_DAC2
85/255
R_BIAS_FF
RE_DAC2_GAIN
G_DAC1
(G_DAC3)
I-DAC2
0
R_MOD=R_MOD_FF+R_MOD_FB
=R_MOD_FF+R_APC_FB
G_DAC1= 1 or 0.1
G_DAC2= 1 or 0.5
G_DAC3= 1 or 1.2/2.2
R_BIAS=R_BIAS_FF
I-DAC1(V-DAC3)
R_MOD_FB
=R_APC_FB
I-DAC2
R_BIAS
RE_DAC1_GAIN
(RE_DAC3_GAIN)
R_MOD_FF
RE_DAC2_GAIN
G_DAC1= 1 or 0.1
G_DAC2= 1 or 0.5
G_DAC3= 1 or 1.2/2.2
R_BIAS=R_BIAS_FF
Fig.4-9 Setting Example 5 (BIAS＝FF+FB,MOD＝FF) Fig.4-10 Setting Example 6 (BIAS＝FB,MOD＝FB)
RE_DAC1_GAIN
(RE_DAC3_GAIN)
R_MOD_FF
R_MOD_FB
=0
R_APC_FB
0
R_BIAS_FB
=R_APC_FB
10/255
(2.2/255)
G_DAC1
(G_DAC3)
R_APC_FB
K_MOD
_FBRT
R_BIAS
Ibias
K_BIAS
_FBRT
G_DAC2
RE_BIAS_FBRT
R_BIAS_FF
RE_DAC2_GAIN
R_MOD
R_BIAS_FB
R_BIAS
10/255
(2.2/255)
G_DAC1
(G_DAC3)
Imod
(Vmod)
Ibias
G_DAC2
85/255
R_BIAS_FF=0
R_MOD=R_MOD_FB
（R_MOD_FB=K_MOD_FBRT*R_APC_FB）
G_DAC1= 1 or 0.1
G_DAC2= 1 or 0.5
G_DAC3= 1 or 1.2/2.2
R_BIAS=R_BIAS_FF+R_BIAS_FB
=R_BIAS_FF+R_APC_FB
R_MOD_FB
I-DAC2
85/255
R_MOD=R_MOD_FF
Imod
(Vmod)
I-DAC2
1
RE_DAC1_GAIN
(RE_DAC3_GAIN)
R_MOD_FF=0
I-DAC1(V-DAC3)
I-DAC1(V-DAC3)
R_MOD
RE_MOD_FBRT
R_BIAS=R_BIAS_FB
（R_BIAS_FB=K_BIAS_FBRT*R_APC_FB）
RE_DAC2_GAIN
G_DAC1= 1 or 0.1
G_DAC2= 1 or 0.5
G_DAC3= 1 or 1.2/2.2
Fig.4-11 Setting Example 7 (BIAS＝FB,MOD＝FF+FB) Fig. 4-12 Setting Example 8 (BIAS＝FF+FB,MOD＝FB)
RE_MOD_FBRT
RE_DAC1_GAIN
(RE_DAC3_GAIN)
R_MOD_FF
I-DAC1(V-DAC3)
R_APC_FB
K_MOD
_FBRT
R_MOD_FB
R_MOD
R_BIAS_FB
R_BIAS
10/255
(2.2/255)
G_DAC1
(G_DAC3)
RE_MOD_FBRT
Imod
(Vmod)
I-DAC1(V-DAC3)
R_APC_FB
K_MOD
_FBRT
R_MOD_FB
R_MOD
R_BIAS_FB
R_BIAS
I-DAC2
K_BIAS
_FBRT
RE_BIAS_FBRT
R_BIAS_FF=0
R_BIAS=R_BIAS_FB
（R_BIAS_FB=K_BIAS_FBRT*R_APC_FB）
10/255
(2.2/255)
G_DAC1
(G_DAC3)
Imod
(Vmod)
I-DAC2
Ibias
K_BIAS
_FBRT
G_DAC2
85/255
R_MOD=R_MOD_FF+R_MOD_FB
（R_MOD_FB=K_MOD_FBRT*R_APC_FB）
RE_DAC1_GAIN
(RE_DAC3_GAIN)
R_MOD_FF=0
RE_BIAS_FBRT
RE_DAC2_GAIN
R_BIAS_FF
R_MOD=R_MOD_FB
（R_MOD_FB=K_MOD_FBRT*R_APC_FB）
G_DAC1= 1 or 0.1
G_DAC2= 1 or 0.5
G_DAC3= 1 or 1.2/2.2
Ibias
85/255
R_BIAS=R_BIAS_FF+R_BIAS_FB
（R_BIAS_FB=K_BIAS_FBRT*R_APC_FB）
G_DAC2
RE_DAC2_GAIN
G_DAC1= 1 or 0.1
G_DAC2= 1 or 0.5
G_DAC3= 1 or 1.2/2.2
Fig.4-13 Setting Example 9 (BIAS＝FF+FB, MOD＝FF+FB)
RE_MOD_FBRT
RE_DAC1_GAIN
(RE_DAC3_GAIN)
R_MOD_FF
I-DAC1(V-DAC3)
R_APC_FB
K_MOD
_FBRT
R_MOD_FB
R_MOD
R_BIAS_FB
R_BIAS
10/255
(2.2/255)
G_DAC1
(G_DAC3)
Imod
(Vmod)
I-DAC2
K_BIAS
_FBRT
RE_BIAS_FBRT
R_BIAS_FF
R_MOD=R_MOD_FF+R_MOD_FB
（R_MOD_FB=K_MOD_FBRT*R_APC_FB）
R_BIAS=R_BIAS_FF+R_BIAS_FB
（R_BIAS_FB=K_BIAS_FBRT*R_APC_FB）
<MS0290-E-01>
Ibias
85/255
G_DAC2
RE_DAC2_GAIN
G_DAC1= 1 or 0.1
G_DAC2= 1 or 0.5
G_DAC3= 1 or 1.2/2.2
-19-
2004/8
ASAHI KASEI
[AK2572]
Table 4-7 Relation of APC Operation Setting and Register Retaining Temperature Compensation Data
E_BIAS_TC [*1]
E_MOD_TC [*1][*2]
RE_APC_ RE_APC_ RE_APC_
(Temperature compensation
(Temperature compensation
FF_SET
FB_SET
INIT_SET
Data for I-DAC2)
Data for I-DAC1or V-DAC3)
－
－
00 (0)
x
－
－
0
01 (1)
－
1
R_APC_FBIV
00 (0)
－
－
0
10 (2)
－
1
R_APC_FBIV
－
－
0
11 (3)
－
1
R_APC_FBIV
－
00 (0)
x
R_MOD_FF
－
0
R_MOD_FF
01 (1)
1
Prohibited
01 (1)
－
0
R_MOD_FF
10 (2)
1
R_APC_FBIV
R_MOD_FF
－
0
R_MOD_FF
11 (3)
1
R_APC_FBIV
R_MOD_FF
－
00 (0)
x
R_BIAS_FF
－
0
R_BIAS_FF
01 (1)
1
R_BIAS_FF
R_APC_FBIV
10 (2)
－
0
R_BIAS_FF
10 (2)
1
Prohibited
－
0
R_BIAS_FF
11 (3)
1
Prohibited
11 (3)
xx
x
R_BIAS_FF
R_MOD_FF
［*1］ As to the EEPROM memory space of E_BIAS_TC, E_MOD_TC, refer to Table 9-3.
［*2］ By RE_MODV_SEL setting, DAC (either I-DAC1 or V-DAC3) loading the temperature
compensation data retained in E_MOD_TC is selected. Refer to Table 3-4.
［*3］ Register content
Register
Content
Note
R_BIAS_FF
Bias current data (APC_FF)
Set to I-DAC2
R_MOD_FF
Modulation current data (APC_FF)
Set to either I-DAC1 or V-DAC3.
Added to the APC_FF value after
R_APC_FBIV
APC_FB initial data.
dividing calculation.
<MS0290-E-01>
-20-
2004/8
ASAHI KASEI
[AK2572]
Table 4-8 Operation Setting and APC Operation at Self-Operation Mode
RE_APC_ RE_APC RE_APC_
R_BIAS_FF
FB_SET _FF_SET INIT_SET
R_MOD_FF
R_APC
_FBIV
R_BIAS
_FBRT
R_MOD
_FBRT
K_BIAS
_FBRT
K_MOD
_FBRT
0
0
0
0
0
0
0
0
－
－
－
－
－
－
－
－
0
0
0
0
0
0
0
0
－
－
－
－
－
－
－
－
－
－
－
－
－
－
E_BIAS
_FBRT
E_BIAS
_FBRT
E_BIAS
_FBRT
E_BIAS
_FBRT
E_BIAS
_FBRT
－
E_BIAS
_FBRT
－
－
－
－
－
－
－
－
－
－
－
－
－
－
E_MOD
_FBRT
E_MOD
_FBRT
E_MOD
_FBRT
E_MOD
_FBRT
E_MOD
_FBRT
－
E_MOD
_FBRT
0
0
0
－
0
0
0
1
1
1
1
1
－
1
R_BIAS
_FBRT/128
R_BIAS
_FBRT/128
R_BIAS
_FBRT/128
R_BIAS
_FBRT/128
R_BIAS
_FBRT/128
－
R_BIAS
_FBRT/128
1
1
1
－
1
1
1
0
0
0
0
0
－
0
R_MOD
_FBRT/128
R_MOD
_FBRT/128
R_MOD
_FBRT/128
R_MOD
_FBRT/128
R_MOD
_FBRT/128
－
R_MOD
_FBRT/128
00 (0)
00 (0)
01 (1)
10 (2)
11 (3)
x
x
x
x
01 (1)
00 (0)
11 (3)
0
1
0
1 [*]
0
1
x
0
1
0
1
0
1 [*]
x
0
0
0
－
E_BIAS_TC
E_BIAS_TC
E_BIAS_TC
0
0
0
0
E_BIAS_TC
－
E_BIAS_TC
0
0
E_MOD_TC
－
0
0
E_MOD_TC
0
0
E_MOD_TC
E_MOD_TC
0
－
E_MOD_TC
FB
FB
FB
－
FB
FB
FB
FB
FB
FB
FB
FB
－
FB
0
E_MOD_TC
0
－
0
E_MOD_TC
0
0
E_BIAS_TC
0
E_BIAS_TC
0
－
0
00 (0)
0
0
0
FB
0
1
0
0
FB
E_BIAS_TC
0
0
E_MOD_TC
FB
0
1
0
E_MOD_TC
FB
E_BIAS_TC
0
E_BIAS_TC
0
FB
0
1 [*]
－
－
－
－
FB
0
01 (1)
10 (2)
10 (2)
11 (3)
00 (0)
01 (1)
10 (2)
11 (3)
01 (1)
10 (2)
11 (3)
x
0
0
0
E_MOD_TC
E_BIAS_TC
0
E_BIAS_TC E_MOD_TC
R_APC
_FB
E_BIAS_TC E_MOD_TC
MOD
BIAS
(R_DAC1
(R_DAC2)
or R_DAC3)
0
0
0
FF
FF
0
FF
FF
E_BIAS E_MOD
_TC
_TC
－
－
FF
FF
－
FF
－
FF
0
0
0
－
FF
FF
FF
FB
FB
FB
FB
FF + FB
－
FF + FB
FB
FB
FF + FB
－
FB
FB
FF + FB
0
0
FF
FF
0
－
FF
FB
FB
－
－
FB
FB
FB_INIT
－
FB
FF + FB
－
FF
FB
FF + FB
FB_INIT
FF
FF + FB
FB
FF
－
－
－
－
－
FF + FB
FF + FB
FF
FF
－－
－
FB_INIT
－
FF
－
－
－
FF
FF
FB_INIT
FF
FF
－
－
－
FB_INIT
－
FF
FF
FB_INIT
－
FF
－
－
FF
FF
[*] It is prohibited to set <RE_APC_FB_SET＝”01”, RE_APC_FF_SET＝”01”, RE_APC_INIT_SET＝”1”>, <RE_APC_FB_SET＝”10”, RE_APC_FF_SET＝”10”,
RE_APC_INIT_SET＝”1”> or <RE_APC_FB_SET＝”11”, RE_APC_FF_SET＝”10”, RE_APC_INIT_SET＝”1”>.
< MS0290-E-01>
-21-
2004/8
ASAHI KASEI
[AK2572]
Table 4-9 Operation Setting and APC Operation at Adjustment Mode
R_APC
_FBIV
R_BIAS_
FBRT
R MOD _
FBRT
K_ BIAS
_FBRT
K_ MOD
_FBRT
BIAS
(R_ DAC2)
0
FB
FB
0 [*2]
I/F
I/F
I/F [*1]
I/F [*1]
I/F [*1]
I/F [*1]
I/F [*1]
I/F [*1]
FB
0 [*2]
I/F
I/F
FB
FB
0 [*2]
0 [*2]
FB
I/F
I/F
I/F
FB
FB
0
0 [*2]
I/F
FB
0 [*2]
I/F
I/F
FB
FF + FB
1
0 [*2]
I/F
FB
I/F
I/F
I/F
FB
FF + FB
0
I/F
0 [*2]
FB
0 [*2]
I/F
I/F
FF + FB
FB
1
I/F
0 [*2]
FB
I/F
I/F
I/F
FF + FB
FB
0
I/F
I/F
FB
0 [*2]
I/F
I/F
FF + FB
FF + FB
1
I/F
I/F
FB
I/F
I/F
I/F
0
1
0
R_MOD_FBRT
/128
R_MOD_FBRT
/128
R_MOD_FBRT
/128
R_MOD_FBRT
/128
R_MOD_FBRT
/128
R_MOD_FBRT
/128
R_MOD_FBRT
/128
R_MOD_FBRT
/128
FF
FF
FB
0 [*2]
0
0
1
R_BIAS_FBRT
/128
R_BIAS_FBRT
/128
R_BIAS_FBRT
/128
R_BIAS_FBRT
/128
R_BIAS_FBRT
/128
R_BIAS_FBRT
/128
R_BIAS_FBRT
/128
R_BIAS_FBRT
/128
MOD
(R_ DAC1
or R_DAC3)
FF
FB
FF
FF + FB
FF + FB
RE_APC
_FB_SET
RE_APC
_FF_SET
RE_APC_
INIT_SET
00 (0)
01 (1)
10 (2)
xx
xx
xx
x
x
x
I/F
I/F
I/F
I/F
I/F
I/F
0
0 [*2]
1
00 (0)
01 (1)
11 (3)
10 (2)
11 (3)
R_ BIAS _FF R_MOD_FF R_APC_FB
“I/F” notation in the table indicates that the register setting can be executed via Digital I/F.
[*1] Setting changes of R_BIAS_FBRT and R_MOD_FBRT are possible via Digital I/F, but APC_FB dividing coefficients K_BIAS_FBRT and K_MOD_FBRT are
not affected.
[*2] Register setting is possible but data is treated as “0”.
< MS0290-E-01>
-22-
2004/8
ASAHI KASEI
[AK2572]
4.4 On-chip Temperature Sensor (TEMPSENS) Characteristics
Characteristic of the On-chip temperature sensor (TEMPSENS) in Figure 4-14, and the relation of AD code
(R_TEMP [7:1] : EEPROM address equivalent) versus Temperature relation in Table 4-10 are shown.
The On-chip temperature sensor characteristic is expressed as :
V [V]＝－0.01156 * t + 1.62 [Typ.]
where temperature t ［℃］、and output voltage V [V]. The output voltage of the detected temperature by the
temperature sensor has a negative slope characteristic with - 11.56 mV/℃±7% (Reference value by design).
Output voltage from the temperature sensor is A-to-D converted by 8 bits ADC (Max. input voltage＝2.2 V
[Typ.]) into the digital code R_TEMP [7:0] and inverted.
7 bits data of the digital code R_TEMP [7:1] is used as EEPROM address, and temperature compensation
data for Bias current (E_BIAS_TC) and Modulation current (E_MOD_TC) are read out.
The relation of Temperature and A-to-D converted code is expressed as :
8 bits AD code : R_TEMP［7:0］＝255－int(- 1.334*t +188.3) [Typ.]
7 bits AD code : R_TEMP［7:1］＝127－int(- 0.667*t +94.0) [Typ.]
Be noted that as output voltage from On-chip temperature sensor is A-to-D converted into digital code and
inverted, AD code against the detected temperature of On-chip temperature sensor exhibits a positive slope
characteristic. Temperature change per each 1 LSB in 8 bits AD code “R_TEMP [7:0]” is +0.75 ℃/LSB [Typ.]
and temperature change per each 1 LSB in 7 bits AD code “R_TEMP [7:1]” is +1.5 ℃/LSB [Typ.].
Therefore temperature compensation data for Bias current (E_BIAS_TC) and Modulation current
(E_MOD_TC) are written in every 1.5 ℃ increment. However, as the temperature compensation data is
derived from a linear interpolation of the detected temperature by the On-chip temperature sensor (refer to
Section 4.1), resolution of R_BAIS_FF and R_MOD_FF data to be loaded to DAC is 0.75 ℃. As On-chip
temperature sensor detects the chip surface temperature, temperature difference exists between the LD
temperature and the detected temperature by the On-chip temperature sensor.
Temperature detect error of the On-chip temperature sensor can be tuned as follows :
(1) Slope calculation at 2 different temperature points :
Read the TEMPSENS output (TEMPMON) or the A-to-D converted code (R_TEMP) at 2 different
temperature points and calculate the slope characteristic. It can adjust and correct the characteristics
including the error on the slope of the On-chip temperature sensor.
(2) Tuning at a single temperature point :
Read the A-to-D converted code (R_TEMP) while LD adjustment is made, and calculate the AD code at a
given temperature, based on the +0.75 ℃ / LSB slope characteristic. It cannot compensate the error of
On-chip temperature sensor in this method.
Figure 4-14 On-chip TEMPSENS Characteristics [Typ.]
Output Voltage V [V]
2.5
2.0
1.5
1.0
0.5
0.0
-40
-20
0
20
40
60
80
100
120
Temperature t [℃]
< MS0290-E-01>
-23-
2004/8
ASAHI KASEI
[AK2572]
Table 4-10 Relation between R_TEMP［7:1］ and detected temperature of the On-chip temperature sensor [Typ.]
R_TEMP
Temperature R_TEMP
Temp.
R_TEMP
Temp.
R_TEMP
Temp.
［7:1］
[℃]
［7:1］
[℃]
［7:1］
[℃]
［7:1］
[℃]
0
- 50.2
32
- 2.2
65
45.7
96
93.7
1
- 48.7
33
- 0.7
66
47.2
97
95.2
2
- 47.2
34
0.8
67
48.7
98
96.7
3
- 45.7
35
2.3
68
50.2
99
98.2
4
- 44.2
36
3.8
69
51.7
100
99.7
5
- 42.7
37
5.3
70
53.2
101
101.2
6
- 41.2
38
6.8
71
54.7
102
102.7
7
- 39.7
39
8.3
72
56.2
103
104.2
8
- 38.2
40
9.8
73
57.7
104
105.7
9
- 36.7
41
11.3
74
59.2
105
107.2
10
- 35.2
42
12.8
75
60.7
106
108.7
11
- 33.7
43
14.3
76
62.2
107
110.2
12
- 32.2
44
15.8
77
63.7
108
111.7
13
- 30.7
45
17.3
78
65.2
109
113.2
14
- 29.2
46
18.8
79
66.7
110
114.7
15
- 27.7
47
20.3
80
68.2
111
116.2
16
- 26.2
48
21.8
81
69.7
112
117.7
17
- 24.7
49
23.3
82
71.2
113
119.2
18
- 23.2
50
24.8
83
72.7
114
120.7
19
- 21.7
51
26.3
84
74.2
115
122.2
20
- 20.2
52
27.7
85
75.7
116
123.7
21
- 18.7
53
29.2
86
77.2
117
125.2
22
- 17.2
54
30.7
87
78.7
118
126.7
23
- 15.7
55
32.2
88
80.2
119
128.2
24
- 14.2
56
33.7
89
81.7
120
129.6
25
- 12.7
57
35.2
90
83.2
121
131.1
26
- 11.2
58
36.7
91
84.7
122
132.6
27
- 9.7
59
38.2
92
86.2
123
134.1
28
- 8.2
60
39.7
93
87.7
124
135.6
29
- 6.7
61
41.2
94
89.2
125
137.1
30
- 5.2
62
42.7
95
90.7
126
138.6
31
- 3.7
63
44.2
65
92.2
127
140.1
[*] When writing APC_FF data into EEPROM, be noted that AD code data (EEPROM address equivalent
where APC_FF data is stored) becomes larger when detected temperature of the On-chip temperature
sensor is higher (The relation of detected temperature of the On-chip sensor and output voltage is reversed).
4.5 Current Monitor
A current multiplied by 0.012 factor of the I-DAC2 output current (Sink current) is output as Sourcing current
on BIASMON-pin.
< MS0290-E-01>
-24-
2004/8
ASAHI KASEI
[AK2572]
5. Burst Mode Operation
The AK2572 is put into Burst mode support operation by setting RE_BURST_SET＝“1”.
When the Burst mode operation is enabled, do not use APC_FB function. Control the LD current by APC_FF
function only (RE_APC_FF_SET＝“3”, RE_APC_FB_SET＝“0”), and OPTALM and CURRALM should not
be selected as the target alarm on TXFAULT-pin (RE_OPTALM_SET＝“0”, RE_CURRALM_SET＝“0”).
Figure 5-1 Burst Mode Operation
Burst ON (Active)
Burst OFF (Inactive)
ON (Output Current / Voltage)
ON (Output Current / Voltage)
ON
ON
ON (Update Data)
ON (Update Data)
Hold Data
Update Data
Burst Signal (BURST-pin)
I-DAC1, I-DAC2, V-DAC3
Temperature Detection
APC_FF Operation
R_DACx (x=1~3)
EXTALM1
EXTALM2
TEMPALM
61ns [typ]
ON/OFF
ON
ON
ON
ON
(1) Alarm mask function
EXTALM1 and EXTALM2 can be masked for 61 ns [Typ.] at the rising edge of Burst signal by
RE_BURST_ALM setting. By enabling this masking operation, EXTALM1 and EXTALM2 for
TXFAULT-pin output (Logical “OR” function of alarms set by EEPROM / Register) is masked but output to
status register R_TXFLT_ST is not masked and ALM detect result is always retained in that register.
(2) APC operation masking function
Updating APC_FF data (R_BIAS_FF, R_MOD_FF) and temperature detection by the On-chip temperature
sensor are always executed. DAC setting data (R_DACx [x＝1~3]) are updated during the Burst OFF.
During the Burst ON, DAC setting data are not updated but the updated data made during the previous
Burst OFF period is held.
5. 1 Power Leveling ［1］
In Power Leveling [1] mode, the data to be loaded to register (R_MOD_FF) from one of two patterns of the
Modulation current temperature compensation data which are retained in EEPROM is selected by Hardware
pin control (MOD_CTRL-pin) and it can be used as APC_FF data.
EXTALM2 / MOD_CTRL-pin becomes MOD_CTRL control pin when both RE_PWR_LVL1_SET and
RE_SFP_SET are set to “1”, and Power Leveling [1] function is available. EEPROM data is set to each DAC by
MOD_CTRL-pin as shown in Table 5-1.
< MS0290-E-01>
-25-
2004/8
ASAHI KASEI
[AK2572]
Table 5-1 EEPROM Address Space in Power Leveling [1]
RE_MODV_SEL
1
0
MOD_CTRL-pin
H
L
H
L
EEPROM
Device Address
Address
DAC
－
－
E_MOD_TC [2]
A0h
00h ~ 7Dh [*]
V-DAC3
I-DAC1
－
－
E_MOD_TC [1]
A4h
00h ~ 7Fh
V-DAC3
I-DAC1
E_BIAS_TC
A4h
80h ~ FFh
I-DAC2
I-DAC2
I-DAC2
I-DAC2
E_EXTRA_TC
A6h
00h ~ 1Fh
I-DAC1
I-DAC1
V-DAC3
V-DAC3
[*] Since Write Protect control register is allocated at “Device Address＝A0h / Address＝7Eh, 7Fh”, E_MOD_TC
[2] has 126 address locations. Therefore E_MOD_TC [2] has 2 fewer address locations as compared with
E_MOD_TC [1] and E_BIAS_TC. So the linear interpolation of E_MOD_TC [2] is executed as follows :
R_MOD_FF(z)＝E_MOD_TC2(x－1)＋｛E_MOD_TC2(x)－E_MOD_TC2(x－1)｝×R_TEMP [0] / 2
when z＝R_TEMP [7:0]＝0 ~ 5, E_MOD_TC(x)＝E_MOD_TC(x－1)＝E_MOD_TC(0)
where the detected temperature data is R_TEMP [7:0]＝z＝2x+5,2x+4, R_TEMP [7:1]＝x, E_MOD_TC[2] as
E_MOD_TC2(x) and the obtained data by a linear interpolation is R_MOD_FF(z).
5. 2 Power Leveling [2]
In Power Leveling [2] mode, the data to be loaded to register (R_BIAS_FF, R_MOD_FF) can be selected by
R_PWR_SEL setting among 4 patterns of Bias current and Modulation current temperature compensation
data that are retained in EEPROM.
Power Leveling [2] is enabled by setting RE_PWR_LVL1_SET＝“0” and RE_PWR_LVL2_SET＝“1”.
When the write protect is released (WP-pin＝“H” and R_WP_CTRL＝“0”), R_PWR_SEL [1:0] data at “Device
Address＝A8h / Address＝2Fh” can be altered in Self-Operation Mode.
When Power Leveling [2] is enabled, a linear interpolation of the temperature compensation data is executed by
using R_TEMP [7:3], R_TEMP [2:0] and the data in EEPROM as shown in Table 5-2.
R_BIAS_FF(z)＝E_BIAS_TCn(y－1)＋｛E_BIAS_TC n(y)－E_BIAS_TCn(y－1)｝×R_TEMP [2:0] / 8
R_MOD_FF(z)＝E_MOD_TCn(y－1)＋{E_MOD_TCn(y)－E_MOD_TCn(y－1)}×R_TEMP [2:0] / 8
when y＝0 (R_TEMP [7:0]＝z＝0~7), E_BIAS_TCn(y)＝E_BIAS_TCn(y－1)＝E_BIAS_TCn(0) and
E_MOD_TCn(y)＝E_MOD_TCn(y－1)＝E_MOD_TCn(0).
where the detected temperature data R_TEMP [7:0]＝z＝8y, 8y+1, ・・・, 8y+7, R_TEMP [7:3]＝y, the
temperature compensation data retained in EEPROM is E_BIAS_TCn(y), E_MOD_TCn(y), n＝0~3 and the
obtained data by a linear interpolation is R_BIAS_FF(z), R_MOD_FF(z) respectively.
Table 5-2 EEPROM Address Space in Power Leveling [2]
RE_ PWR_LVL2_SET＝”0”
RE_ PWR_LVL2_SET＝”1”
R_TEMP ［7:1］
Data
Address
RE_PWR_SEL R_TEMP ［7:3］
Data
0
00h ~ 1Fh
E_MOD0_TC
1
00h ~ 1Fh
E_MOD1_TC
00h ~ 7Fh E_MOD_TC 00h ~ 7Fh
2
00h ~ 1Fh
E_MOD2_TC
3
00h ~ 1Fh
E_MOD3_TC
0
00h ~ 1Fh
E_BIAS0_TC
1
00h ~ 1Fh
E_BIAS1_TC
00h ~ 7Fh E_BIAS_TC 80h ~ FFh
2
00h ~ 1Fh
E_BIAS2_TC
3
00h ~ 1Fh
E_BIAS3_TC
< MS0290-E-01>
-26-
Address
00h ~ 1Fh
20h ~ 3Fh
40h ~ 5Fh
60h ~ 7Fh
80h ~ 9Fh
A0h ~ BFh
C0h ~ DFh
E0h ~ FFh
2004/8
ASAHI KASEI
[AK2572]
6. Alarm Function
In Table 6-1, the outline of the AK2572 Alarm (ALM) functions such as TEMPALM, OPTALM, CURRALM,
EXTALM1 and EXTALM2, and TXFAULT output function where alarms to be selected by EEPROM/Register
setting are logically OR-ed, are listed.
Table 6-1 ALM Function Outlines
ALM
Detect time
[Typ.]
Condition to output alarm
Note
When detected temperature equivalent value
Temp. sense period=64ms
64 ms
exceeds ALM set value (E_TEMPALM)
Set by RE_TEMPALM_SET
When monitor PD input voltage becomes lower
Holding APC FB value
5 μs [*]
OPTALM
than ALM set value (RE_OPTALM)
Set by RE_OPTALM_SET
When a current to be set to DAC exceeds ALM set
125 μs
CURRALM
Set by RE_CURRALM_SET
value (RE_CURRALM_BIAS / MOD)
EXTALM1 When same polarity ALM signal is input on
Set by RE_EXTALM1_SET
1 μs
EXTALM2 EXTALM1/2-pin as set by RE_EXTALM1/2_POL
Set by RE_EXTALM2_SET
Automatically shutdown
When any of the ALMs is detected as target alarms
Depend on
when any target alarm is
available on TXFAULT-pin output which are set by
the detected
TXFAULT
detected and RE_SFP_SET
EEPROM / Register setting (Refer to note above in
target alarm
＝”0”
this table)
[*] The detect time does not include the delay time caused by a time constant of external Rpd and Cpd.
TEMPALM
6.1 TEMPALM
TEMPALM is generated when the following relation is established after digitally comparing the A-to-D
converted temperature sensor output value (R_TEMP [7:0]) with the ALM set value (R_TEMPALM) :
R_TEMP≧E_TEMPALM
6.2 OPTALM
1/3, 1/4, 1/6 or 1/7 value of the APC target value (apc_ref) can be set as OPTALM set value (optalm_ref) by
RE_OPTALM setting. OPTALM detect is done by an analog comparator and it is generated when the following
relation is established
vpd＜optalm_ref
6.3 CURRALM
CURRALM is generated when one of the following 3 conditions is met after digitally comparing DAC setting
value for Modulation current (R_DAC1 [I-DAC1 set value] or R_DAC3 [V-DAC3 set value]) or DAC setting value
for Bias current (R_DAC2 [I-DAC2 set value]) with the CURRALM setting value (R_CURRALM_BIAS,
R_CURRALM_MOD):
R_DAC2 (Upper 4 bits)＞R_CURRALM_BIAS
or R_DAC1(Upper 4 bits)＞R_CURRALM_MOD, or R_DAC3(Upper 4 bits)＞R_CURRALM_MOD
Alarm threshold values R_CURRALM_BIAS and R_CURRALM_MOD can be set in accordance with the LD
temperature characteristic (Set by approximately every 6 ℃ step with the data in E_CURRALM_BIAS_TC,
E_CURRALM_MOD_TC, Refer to Table 9-3).
CURRALM is also generated when either of R_DAC1 (R_DAC3) or R_DAC2 becomes its full code (FFh).
When a shutdown request is made, CURRALM is set to “Inactive“ polarity.
6.4 EXTALM1, EXTALM2
When the same polarity ALM signal is input on EXTALM1-pin as set by RE_EXTALM1_POL, EXTALM1
detection is made. On the other hand, when the same polarity ALM signal is input on EXTALM2 /
MOD_CTRL-pin as set by RE_EXTALM2_POL, EXTALM2 detection is made if RE_PWR_LVL1_SET＝”0” or
RE_SFP_SET＝”0” (EXTALM2 / MOD_CTRL -pin is set to EXTALM2-pin)
When RE_EXTALM1/2_POL＝"0", the ALM detect polarity of “H” at EXTALM1/2-pin is set.
When RE_EXTALM1/2_POL＝"1", the ALM detect polarity of “L” at EXTALM1/2-pin is set.
< MS0290-E-01>
-27-
2004/8
ASAHI KASEI
[AK2572]
6. 5 TXFAULT
6.5.1 Target Alarm Setting of TXFAULT Output
As shown in Table 6-2, target Alarms (ALMs) available on TXFAULT output can be selected by EEPROM /
Register setting. Logical “OR” function of the selected ALMs becomes TXFAULT output signal.
Table 6-2 Target ALM Setting of TXFAULT Output
Device Address / Address
Status register
Target ALM
Mask setting [*1]
Note
(A8h / 19h) [*2]
EEPROM
Register
R_TXFLT_ST [3]
RE_EXTALM2_SET［5］
EXTALM2
[*3]
R_TXFLT_ST [2]
RE_EXTALM1_SET［4］
EXTALM1
A6h / 65h
A8h / 05h
CURRALM RE_CURRALM _SET［3］
R_TXFLT_ST [1]
RE_OPTALM _SET［2］
OPTALM
R_TXFLT_ST [0]
TEMPALM RE_TEMPALM_SET［7］
A6h / 66h
A8h / 06h
R_TXFLT_ST [4]
［*1］Logical “OR” function of those ALMs, where corresponding bits are set by “1” in mask setting by
EEPROM / Register, becomes TXFAULT output signal.
［*2］When ALM is detected, “1” is written in the corresponding bit of the ALM.status register.
［*3］When RE_PWR_LVL1_SET＝”0” or RE_SFP_SET＝”0”, EXTALM2 / MOD_CTRL-pin is set as
EXTALM2 input pin and EXTALM2 function is enabled.
6.5.2 Operation at TXFAULT Detection
Operation at TXFAULT detection differs by RE_SFP_SET setting. Operation at different settings is listed in
Table 6-3.
When at RE_SFP_SET＝”0”, any of the ALMs being set by EEPROM / Register is detected, TXFAULT signal
is generated and “H” output is held and DAC output is put into shutdown condition. But when a shutdown
request is made via TXDIS-pin, a previous TXFAULT output level before the shutdown request is kept and
even if any ALM is detected during the shutdown, TXFAULT signal is not output. When the shutdown
request is released (transition of “L” to “H”) via TXDIS-pin, release of TXFAULT (TXFAULT output is “L”) is
made. For more details, please refer to section “7. Shutdown Control“. DAC output is not shutdown during the
Adjustment Mode even if TXFAULT is detected.
When at RE_SFP_SET＝”1”, any of the ALMs being set by EEPROM / Register is detected, TXFAULT signal
is generated (TXFAULT output is “H”), when all selected ALMs are cleared, TXFAULT is also cleared
(TXFAULT output is “L”).
When the shutdown condition is set, CURRALM is forced to “Disabled output“ state.
Table 6-3 TXFAULT Operation
Shutdown Logical “OR” of
RE_SFP_SET request via target ALM for
TXDIS-pin TXFAULT
0
0
1
0
1
x
1
< MS0290-E-01>
0
x
1
x
TXFAULT
Operation
0
1 (Hold)
Hold the previous TXFAULT level
just before shutdown request
Logical “OR” of target ALMs for
TXFAULT
Logical “OR” of target ALMs for
TXFAULT
Normal operation
Shutdown
-28-
Shutdown
Normal operation
Shutdown
2004/8
ASAHI KASEI
[AK2572]
7. Shutdown Control
7.1 Shutdown Operation
The AK2572 can be put into the shutdown condition by setting TXDIS-pin to “H”.
The condition for shutdown in Table 7-1, and operation during shutdown in Table 7-2 are shown.
Table 7-1 Shutdown Condition
TXDIS RE_SFP_SET TXFAULT
Operation
Note
0
Normal operation
0
0
1
Shutdown
Operation at TXFAULT detection for SFP support
1
x
Normal operation
1
x
x
Shutdown
Shutdown request via TXDIS-pin
Table 7-2 Operation during Shutdown
Function
Operation during Shutdown
Note
I-DAC1,2 output Hi-Z
[*]
V-DAC3 output 0.2 V [Max.]
[*]
Based on the detected temperature, temperature compensation data for I-DAC
APC
and V-DAC are updated. But I-DAC output is in Hi-Z state and V-DAC output
Feed Forward
voltage is 0.2 V [Max.]
During shutdown requested via TXDIS, a value just before the shutdown is held.
APC
During shutdown requested by TXFAULT (RE_SFP_SET＝“0”), a value just
Feed Back
before the shutdown is held and it is reset at shutdown release by TXDIS.
ALM
Normal operation (CURRALM is set to “ Disabled output“ state)
At RE_SFP_SET =”0”, a value just before the shutdown is held.
TXFAULT
At RE_SFP_SET =”1”, logical “OR” function of the selected ALMs is output.
[*] DAC output (I-DAC1 or V-DAC3), which is selected as EXTRA_DAC, is not shutdown.
7.2 Operation at Shutdown Release
Since the AK2572 continues its temperature detection and APC feed forward operation even during the
shutdown, current value that is set by Feed Forward function is temperature compensated even if any
temperature difference occurs before or after the shutdown.
On the other hand, whether a value just before the shutdown is held or an initial value is set as APC Feed Back
data (R_APC_FB) can be selected by RE_TEMP_DET setting. When to hold a value just before the shutdown, a
temperature at shutdown release (R_TEMP) and a temperature just before shutdown (to be retained at
R_TEMP_STDW) are compared. If the difference is larger than the set value (RE_TEMP_WIN), namely, when
the following relation is satisfied, ABS(R_TEMP–R_TEMP_STDW)＞RE_TEMP_WIN, a function to set
R_APC_FB to initial value is activated so that an excess power emission of LD and a turn-on delay of LD are
eliminated. As initialization of R_APC_FB is executed with being based on the detected temperature just before
shutdown release, a turn-on operation is accelerated if the initial setting function of APC_FB is selected
(RE_APC_INIT_SET＝“1”). In Table 7-3, R_APC_FB values at shutdown release are listed.
Table 7-3 R_APC_FB Values at Shutdown Release
RE_
TXRE_
Temperature
R_APC_FB
SFP_SET FAULT TEMP_DET difference
0
x
Initial value
0
0
Held value
0
1
1
Initial value
1
x
x
Initial value
0
x
Initial value
0
Held value
1
x
1
1
Initial value
< MS0290-E-01>
-29-
Note
ABS(TEMP–TEMP_STDW)＜TEMP_WIN
ABS(TEMP–TEMP_STDW)＞TEMP_WIN
Shutdown released by TXDIS
ABS(TEMP–TEMP_STDW)＜TEMP_WIN
ABS(TEMP–TEMP_STDW)＞TEMP_WIN
2004/8
ASAHI KASEI
[AK2572]
8. Start-Up Setting in SFP Support Mode
8.1 TXFAULT Detection at Power-Up and after Release from Shutdown
8.1.1 OPTALM
In SFP support mode setting (RE_SFP_SET＝”0”), a mask time can be programmed for TXFAULT detection by
OPTALM during the shutdown release so that a time constant delay derived from the external Rpd and Cpd for
detection of the averaged monitor-PD current at the turning-on of LD must be taken into consideration. Block
diagram in Figure 8-1, and pre-settable mask time relation in Table 8-1 are shown.
In the AK2572, the delay time can be shortened by accelerated start-up setting which is made by initial value
setting function of R_APC_FB and so on.
But when OPTALM is selected as one of the TXFAULT target ALMs, and a mask time is set to be shortened, be
noted that LD optical power will not reach the expected level within the mask time and it may be shutdown
through OPTALM detection to TXFAULT control sequence if initial set value of APC_FF or APC_FB is far off.
Figure 8-1 OPTALM Detection Block Diagram
LD
PDGAIN setting
(RE_PDGAIN)
Monitor
APC_
COMP
DIGITAL
FILTER
APC Feedback value (R_APC_FB)
PD
PDIN
vpd
TXFAULT
CONTROL
PDGAIN
Cpd
Rpd
A time constant delay at
shutdown release derived
from the external Rpd and
Cpd must be taken into
consideration
vapc_ref
APC target
(R_APC_TRGT)
OPALM setting
(R_OPTALM)
OPTALM
_COMP
DAC_APC
ATT
OPTALM threshold
(optalm_ref)
Table 8-1 Time to Valid TXFAULT Detection by OPTALM
RE_
RE_TIMER RE_APC_ RE_APC Mask time for TXFAULT
SFP_SET _OPTALM INIT_SET _FF_SET detection by OPTALM
0
x
x
160 ms [Typ.]
0
00, 01, 10
160 ms [Typ.]
0
1
x
11
2 ms [Typ.]
1
x
2 ms [Typ.]
1
x
x
x
0 ms
Note
Accelerated start-up setting
Accelerated start-up setting
Non-support SFP
8.1.2 EXTALM1, EXTALM2
In SFP support mode setting (RE_SFP_SET＝”0”), a mask time can be set for TXFAULT detection by
EXTALM1 and EXTALM2 at the shutdown release.
In Table 8-2, a delay time relation to be set is shown.
Table 8-2 Time to Valid TXFAULT Detection by EXTALM1, EXTALM2
RE_TIMER_EXTALM1
Mask time for TXFAULT detection
Note
RE_SFP_SET
by EXTALM1, EXTALM 2
RE_TIMER_EXTALM2
0
0 ms
0
1
2 ms [Typ.]
1
X
0 ms
Non-support SFP
< MS0290-E-01>
-30-
2004/8
ASAHI KASEI
[AK2572]
8.2 At Power-On (at TXDIS=”L”)
Start-up sequence at power-on（at TXDIS＝”L”） is shown in Figure 8-2.
Figure 8-2 Start-up Sequence at Power-on (at TXDIS=”L”)
VDD
TXDIS
2ms [Typ.]
TXFAULT with OPTALM enable
(When to set accelerated start-up sequence)
LD Current
APC Feedback
Normal operation
APC FF value or
APC FB initial value
APC FF value
APC FB initial procedure
Power On Reset
ALM operation
Initialization
TXFAULT enable without OPTALM
(When not to set accelerated start-up sequence)
TXFAULT with
OPTALM enable
t_init: 160ms [Typ.]
8.3 At Power-On (at TXDIS＝”H”)
Start-up sequence at power-on (at TXDIS＝“H”) is shown in Figure 8-3.
Figure 8-3 Start-up Sequence at Power-on (at TXDIS＝“H”)
VDD
TXDIS
2ms [Typ.]
LD Current
TXFAULT with OPTALM enable
(When to set accelerated start-up sequence)
APC Feedback
Normal operation
APC FF value or
APC FB initial value
APC FF value
APC FB initial procedure
Power On Reset
ALM Operation
Initialization
TXFAULT enable without OPTALM
(When not to set accelerated start-up sequence)
TXFAULT with
OPTALM enable
t_init: 160ms [typ]
< MS0290-E-01>
-31-
2004/8
ASAHI KASEI
[AK2572]
8.4 At TXDIS Detection / Release
TXDIS detection / release sequence is shown in Figure 8-4.
Figure 8-4 TXDIS Detection / Release Sequence
VDD
10μs [Min.]
TXDIS
TXFAULT
TXFAULT operation when accelerated
start-up sequence is selected is same as that
when no temperature difference exists
Both of the temperature at
Rising and Falling edge of
TXDIS signal are compared
No temperature
difference exists
TXFAULT enable without OPTALM
TXFAULT with OPTALM enable
TXFAULT disable
2ms [Typ.]
APC Feedback
Normal operation
LD Current
APC FB initial procedure
t_off＜10μs
t_on＜1ms
Temperature
difference exists
TXFAULT with
OPTALM enable
t_init:160ms[Typ.]
< MS0290-E-01>
-32-
2004/8
ASAHI KASEI
[AK2572]
8.5 At TXFAULT Detection / Release
TXFAULT detection / release sequences are shown in Figure 8-5 and Figure 8-6.
Figure 8-5 TXFAULT Detection / Release Sequence (When FAULT is released by TXDIS reset)
VDD
TXDIS
t_reset: 10μs [Min.]
FAULT
TXFAULT
2ms
[Typ.]
TXFAULT with OPTALM enable
(When to set accelerated start-up sequence)
LD Current
t_init: 160ms[Typ.]
Depend on the detcted ALM
(Refer to Table 6-1)
TX_FAULT enable
without OPTALM
TXFAULT with
OPTALM enable
Figure 8-6 TXFAULT Detection / Release Sequence (When FAULT is not released)
VDD
TXDIS
t_reset: 10μs[Min.]
FAULT
TXFAULT
LD Current
t_fault
Depend on the detcted ALM
(Refer to Table 6-1)
TXFAULT detection with OPTALM
When to set accelerated start-up sequence: 2ms [Typ.]
When not to set accelerated start-up sequence: 160ms [Typ.]
TXFAULT detection with EXTALM1,2
2ms [Typ] or 0ms (Set by RE_TIMER_EXTALM1,2)
< MS0290-E-01>
-33-
2004/8
ASAHI KASEI
[AK2572]
9. Digital Interface Configuration
9.1 Memory Configuration
EEPROM and Register configuration is shown in Figure 9-1. Access to EEPROM and Register is executed via
2-wire Digital Interface (I/F).
Figure 9-1 Memory Configuration
Device
Address-1
Device
Address-2
Address
0000 0000
~
0111 1101
1010
000
(A0h)
1010
001
(A2h)
1010
010
1010
011
(A6h)
1010
100
(1K)
Write Protect Control (2Address)
1000 0000
~
1111 1111
No Memory
0000 0000
~
1111 1111
No Memory
0000 0000
~
0111 1111
Temperature Compensation Data for Imod
(1K)
(2K)
100
[2] E_MOD_TC2 for Power Leveling [1] when
RE_SFP_SET="1" and
RE_PWR_LVL1_SET="1"
Power Leveling [1] (Select the data for
Imod by MOD_CTRL-pin) is available
when RE_SFP_SET="1" and
RE_PWR_LVL1_SET="1"
Power Leveling [2] is available when
RE_PWR_LVL2_SET="1"
(RE_PW R_LVL1_SET="0"）
Selected by RE_PWR_SEL[1:0]
[E_MOD_TC(1K): I-DAC1 or V-DAC3]
I-MOD0
I-BIAS1
I-MOD1
1111 1111
I-BIAS2
I-MOD2
0000 0000
~
I-BIAS3
I-MOD3
0001 1111
0010 0000
~
0011 1111
0100 0000
~
0101 1111
Temperature Compensation Data for Ibias
[E_BIAS_TC(1K): I-DAC2]
Temp. Compensation Data for EXTRA DAC
[E_EXTRA_TC(256): V-DAC3 or I-DAC1]
(=Not DAC for Imod)
Temperature Data for APC_FB target
Write Protect Control (WP)
[E_APC_TRGT_TC(256)]
Temperature Data for CURRALM Threshold
Register
A0h/7Eh
R_WP_CTRL[0] (Protect Control)
A0h/7Fh
R_PASSW D[7:0] (Password)
[E_CURRALM_BIAS/MOD_TC(256)]
0110 0000
~
0111 1111
Set-up Data
1000 0000
~
1111 1111
No memory
EEPROM
A6h/7Eh
E_WP_CTRL[0] (Protect Control)
A6h/7Fh
E_PASSWD[7:0] (Password )
(256)
(1K)
Write Protect is enable when W P-pin="L" or
R_WP_CTRL[0]="1" (W P-pin setting has a
higher priority than R_WP_CTRL)
* Only A0h(1K) area is possible to Read
when Write Protect is enable
0000 0000
~
1111 1110
Register
1111 1111
Operation Mode Change Command
(A8h)
1010
[1] USER AREA for SFP_MSA support when
RE_SFP_SET="0"
I-BIAS0
~
Switch I-DAC1
and V-DAC3 by
RE_MODV_SEL
setting
User Area or
Temperature Compensation Data for Imod [2]
0111 1110
0111 1111
1000 0000
(A4h)
Contents
Write Protect is released when WP-pin="H"
and R_W P_CTRL[0]="0"
* Full access is possible when when W rite
Protect is released (When R_PASSWD[7:0]
via Digital I/F agree with E_PASSWD[7:0],
access to R_WP_CTRL[0] becomes possible)
[*] Device address is configured with Device address-1 (“1010 “＝“Ah”) and Device address-2.
Device address-2 in 3 bits Binary expression is converted into Hexadecimal code by multiplying it by 2.
For example, when Device address-1＝“1010” and Device address-2＝“011”, Device address becomes
“A6h”.
< MS0290-E-01>
-34-
2004/8
ASAHI KASEI
[AK2572]
9.2 Write Protect Operation
Accessible range and Device address via Digital I/F are determined by Write Protect setting as shown in Table
9-1.
Table 9-1 Write Protect Operation
Item
R_WP_CTRL
Device address
ACK
Access to
EEPROM / Register
Operation mode
Page Write
Sequential Read
WP = “H”
WP = “L”
0
1
x
1010 xxx
1010 000
1010 000
When corresponding Device address is input via Digital I/F [*1]
A0h only
A0h only
Full Access [*2]
Read only
Read only
Self-Operation Self-Operation
Transition to any operation mode is possible
Mode only
Mode only
Sequential write operation of EEPROM is possible in
－
－
every 16 bytes. Sequential write operation of Register
(Address after A8h/3Eh is folded back to A8h/00h).
Sequential read operation of both EEPROM and
Register is possible within the designated address
area respectively. Address after A6h/FFh is folded Sequential read is possible in
back to A0h/00h in EEPROM and address after accessible EEPROM area.
A8h/3Fh is folded back to A8h/00h in Register.
“Non-actual space“ address is not skipped.
［*1］ ACK signal is not returned during the writing operation into EEPROM.
［*2］ When Write Protect is released (WP-pin＝“H” and R_WP_CTRL＝”0”), writing into R_PWR_SEL[1:0] at
address = A8h / 2Fh is possible in Self-Operation Mode.
About Write Protect Setting
* The data for fully accessible setting (E_WP_CTRL＝”0”, E_PASSWD＝”0”) is programmed at AKM.
(a) Write Protect operation is “ON” when WP-pin at “L”.
WP-pin setting has a higher priority than R_WP_CTRL (Register for Write Protect setting).
(b) Write Protect operation is controlled to be “ON ” or “OFF” by R_WP_CTRL when WP-pin is at “H”.
Access to R_WP_CTRL is possible only when R_PASSWD [7:0] (Register for Write Protect password), which
is loaded via digital I/F, agrees with E_PASSWD [7:0] that is the password retained in advance.
Be noted that other than “00h” should be written into E_PASSWD [7:0] to enable Write Protect.
- R_WP_CTRL＝”0” → Full access is possible
- R_WP_CTRL＝”1” → Only the area in Device address＝’1010 000（A0h）‘ is accessible (Read Only),
especially only Write Protect control register (R_PASSWD, R_WP_CTRL) are writable
Accordingly, when Self-Operation Mode is set by R_WP_CTRL＝“1”, access to the adjusting data is executed
as the following procedure,
(1) Make it enable to access to R_WP_CTRL by setting the same value to R_PASSWD as is retained in
E_PASSWD in advance.
(2) Set R_WP_CTRL＝ “0” to enable full access.
(3) When to modify EEPROM content, shift the mode into EEPROM Access Mode and then modify data.
At the Power-on or when Self-Operation Mode is set, R_PASSWD is reset to “00h” and E_WP_CTRL value
is loaded to R_WP_CTRL. So, if E_WP_CTRL is set to “0”, Write Protect operation is automatically released
at Power-on or when Self-Operation Mode is set.
Table 9-2 Write Protect Control Register / EEPROM
Register
EEPROM
D7
D6
D5
－
－
－
A0h / 7Eh
A6h / 7Eh
A0h / 7Fh
A6h / 7Fh
< MS0290-E-01>
-35-
D4
－
D3
D2
－
－
PASSWD
D1
－
D0
WP_CTRL
2004/8
ASAHI KASEI
[AK2572]
9.3 Read / Write Operation
9.3.1 Byte Write
Byte Write operation is shown in Figure 9-2. Select address and then input the data to be written.
Figure 9-2 Byte Write
1 0 1 0
SDA
S
T
A
R
T
0 0
Device
Address-1
Device
R/
Address-2 W
0
A
C
K
Address
(MSB First)
0
A
C
K
Data
(MSB First)
A
C
K
S
T
O
P
9.3.2 Page Write
Page Write operation is shown in Figure 9-3. Up to 16 bytes of data can be written at one time. In Page Write
operation, the lower 4 bits of the 8 bits address are effective and the upper 4 bits data does not change.
Therefore after writing data at “xxxx 1111”, next address to be written is “xxxx 0000”.
Figure 9-3 Page Write
1010
SDA
00
0
S Device Device R/ A
T Address-1Address W C
-2
K
A
R
T
Address
(MSB First)
A
C
K
0
Data (Address)
0
....
A Data (Address + 1) A
C
C
K
K
0
0
A Data (Address + n) A S
C
C T
K
K O
P
9.3.3 Current Address Read
Current Address Read operation is shown in Figure 9-4. Address location where data is to be read out is “most
recently accessed address + 1”.
Figure 9-4 Current Address Read
SDA
1 0 1 0
S
T
A
R
T
Device
Address-1
1 0
Device
R/
Address-2 W
A
C
K
1
Data
(MSB First)
N
O
A
C
K
S
T
O
P
9.3.4 Random Read
Random Read operation is shown in Figure 9-5. When to execute Random Read operation, assign an address
to be read out by Dummy Write operation, and issue a Read instruction.
Figure 9-5 Random Read
SDA
1 0 1 0
S
T
A
R
T
Device
Address-1
0 0 *
Device R/ A
Address-2 W C
K
0
Address
(MSB First)
A S
C T
K A
R
T
Dummy Write
< MS0290-E-01>
-36-
1 0 1 0
Device
Address-1
1 0
Device R/ A
Address-2 W C
K
1
Data
(MSB First)
*: Don't care when Write Protect "ON"
N
O
A
C
K
S
T
O
P
2004/8
ASAHI KASEI
[AK2572]
9.3.5 Sequential Read
Sequential Read operation is shown in Figure 9-6. After the data at the designated address is output by read
instruction, next address data can be read out if ACK signal is generated without stop bit signal that is sent
from a master controller
Figure 9-6 Sequential Read
SDA
....
10
Device R/ A
Address-2 W C
K
0
Data-1
(MSB First)
A
C
K
0
Data-2
....
A
C
K
1
0
A
C
K
Data-n
N
O
A
C
K
S
T
O
P
9.3.6 Data Change
Data Change timing chart is shown in Figure 9-7. Data change (SDA) is made while SCL is at “L”.
Figure 9-7 Data Change
SCL
SDA
DATA STABLE
DATA
CHANGE
9.3.7 Start / Stop
Start / Stop timing chart is shown in Figure 9-8. While SCL is at “H”, Start is effective by setting SDA from “H”
to “L”, and Stop is effective by setting SDA from “L” to “H”.
Figure 9-8 Start / Stop
SCL
SDA
START
< MS0290-E-01>
STOP
-37-
2004/8
ASAHI KASEI
[AK2572]
9.4 EEPROM Configuration
EEPROM configuration is listed in Table 9-3. EEPROM configuration of adjustment data area is listed in Table
9-4 and Table 9-5. The access to EEPROM depends on its operation modes (Refer to Table 10-1). And the access
to EEPROM is also limited by Write Protect setting (Refer to Section 9.2).
< Important Notice > The adjusted data in AKM factory are stored in advance at address location (Device
Address＝A6h, Address＝60h) for the offset voltage of the On-chip temperature sensor. If such excessive
temperature stress is to be applied to the AK2572 which exceeds a guaranteed EEPROM data retention
conditions (for 10 years at 85℃), it is important to read the pre-determined data in advance and to re-write the
same data back into EEPROM after an exposure to the excessive temperature environment. Even if the
exposure time is shorter than the retention time, any accelerated temperature stress tests (such as baking) are
performed, it is recommended to read the pre-set data first and to re-write it after the test. Access to unused
address locations is not functionally guaranteed.
Table 9-3 EEPROM Address Configuration
Device
Address
Address
A0h
00h (0) ~ 7Dh (125)
A0h 80h (128) ~ FFh (255)
A2h
00h (0) ~ FFh (255)
Data (D7 ~ D0)
Initial
value
00h
－
－
Note
User Area (1k bits)
[*1]
No Memory
No Memory
E_MOD_TC (1k bits)
A4h
00 h (0) ~ 7Fh (127)
00h [*2]~[*4]
Temperature Compensation Data for Imod
E_BIAS_TC (1k bits)
A4h 80h (128) ~ FFh (255)
00h [*2], [*3]
Temperature Compensation Data for Ibias
E_EXTRA_TC (256 bit)
00h
[*5]
A6h
00h (0) ~ 1Fh (31)
Temperature Compensation Data for EXTRA DAC
E_APC_TRGT_TC (256 bit)
A6h
20h (32) ~ 3Fh (63)
00h
[*5]
Temperature Compensation Data for APC target
E_CURRALM_BIAS / MOD_TC (256 bit)
A6h
40h (64) ~ 5Fh (95)
FFh
[*5]
Temperature Compensation Data for CURRALM threshold
－
A6h
60h (96) ~ 6Ah (106)
Adjustment Data (88 bit)
Reserved (152 bit）
－
A6h
6Bh (107) ~ 7Dh (125)
A6h
7Eh (126), 7Fh (127)
Write Protect Control (16 bit)
00h
［*1］With both RE_SFP_SET＝”1” and RE_PWR_LVL1＝”1”, this area becomes setting area for Imod
temperature compensation data [2] (E_MOD_TC2) of Power Leveling [1] function.
［*2］R_TEMP (Upper 7 bits A-to-D code of the temperature sensor) and address are corresponded (1.5 ℃/step)
and then the temperature compensation data is written.
［*3］With RE_PWR_LVL1＝“0” and RE_PWR_LVL2＝“1”, these area become setting area for Ibias and Imod
temperature compensation data of Power Leveling [2] function.
［*4］With both RE_SFP_SET＝”1” and RE_PWR_LVL1＝”1”, this area becomes setting area for Imod
temperature compensation data [1] (E_MOD_TC1) of Power Leveling [1] function.
［*5］Upper 5 bits of R_TEMP and address are corresponded (6.0 ℃/step), and then the temperature
compensation data is written.
< MS0290-E-01>
-38-
2004/8
ASAHI KASEI
[AK2572]
Table 9-4 EEPROM : Adjustment Data Configuration
EEPROM
Address
Function
Bit Initial
Factory
4
setting
Factory
4
setting
Note
E_VREFTRIM [7:4]
60h
On-chip oscillator frequency
E_TEMP
_OFFSET [3:0]
60h
Temperature sensor offset
E_PWR_SEL [7:6]
61h
EEPROM data switching at
Power Leveling [2]
2
0
E_BURST_ALM [5:4]
61h
EXTALM mask setting at
Burst mode
2
0
E_BURST_SET [3]
E_PWR_LVL2
_SET [2]
E_SFP_SET [1]
E_PWR_LVL1_SET [0]
E_APC_FF_SET [7:6]
E_APC_FB_SET [5:4]
E_APC_INIT_SET [3]
E_DAC3_GAIN [2]
E_DAC2_GAIN [1]
E_DAC1_GAIN [0]
E_TIMER
_OPTALM [6]
E_EXTALM2_POL [5]
E_EXTALM1_POL [4]
61h
Burst mode setting
1
0
0:Non-masked, 1:Masked
[5]: EXTALM2,
[4]: EXTALM1
0:OFF, 1:ON
61h
Power Leveling [2] setting
1
0
0:OFF, 1:ON
61h
61h
62h
62h
62h
62h
62h
62h
1
1
2
2
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
1
0
0
E_TEMP_DET [3]
63h
SFP_MSA support setting
Power Leveling [1] setting
APC FF setting
APC FB setting
APC_FB initial value setting
V-DAC3 gain setting
I-DAC2 gain setting
I-DAC1 gain setting
OPTALM mask time setting
for SFP_TXFAULT detection
EXTALM2 polarity setting
EXTALM1 polarity setting
Temperature difference detection
at Shutdown release
1
0
E_DAC_SET [2:0]
63h
DAC operation setting
3
0
E_OPTALM [7:6]
E_PDGAIN [5:0]
E_EXTALM2_SET [5]
E_EXTALM1_SET [4]
E_CURRALM_SET [3]
E_OPTALM_SET [2]
E_TIMER
_EXTALM2 [1]
E_TIMER
_EXTALM1 [0]
E_TEMPALM_SET [7]
64h
64h
65h
65h
65h
65h
OPTALM threshold
PD gain setting
EXTALM2 setting for TXFAULT
EXTALM1 setting for TXFAULT
CURRALM setting for TXFAULT
OPTALM setting for TXFAULT
EXTALM2 mask time setting
for SFP_TXFAULT detection
EXTALM1 mask time setting
for SFP_TXFAULT detection
TEMPALM setting for TXFAULT
Window setting for Temperature
difference detection
DAC setting for Imod
(Data setting for I-DAC1,V-DAC3)
APC_FB dividing value for Imod
APC_FB dividing value for Ibias
TEMPALM threshold
2
6
1
1
1
1
0
00h
0
0
0
0
1
0
1
0
1
0
8
00h
0:ON, 1:OFF
Refer to Table 5-1
Refer to Table 4-6
Refer to Table 4-6
0: OFF, 1: ON
0:Gain＝1, 1:Gain＝1.2/2.2
0:Gain＝1/2, 1: Gain＝1
0:Gain＝1/10, 1: Gain＝1
0:160ms, 1:2ms [Typ.]
(Refer to Table 8-1)
0:“H” active, 1:“L” active
0:“H” active, 1:“L” active
0:OFF, 1:ON
Refer to Section 7.2
0:OFF, 1:ON
[2]: V-DAC3, [1]: I-DAC2
[0]: I-DAC1
0 : 1/3, 1: 1/4, 2 : 1/6, 3 : 1/7
Refer to Table 4-3
0:OFF, 1:ON (Target)
0:OFF, 1: ON (Target)
0:OFF, 1: ON (Target)
0:OFF, 1: ON (Target)
0:0ms , 1:2ms [Typ.]
（Refer to Table 8-2）
0:0ms , 1:2ms [Typ.]
（Refer to Table 8-2）
0:OFF, 1: ON (Target)
Refer to Section 7.2 and
Table 4-10
1
0
Refer toTable 3-4
7
7
8
00h
00h
00h
Refer to Section 4.2.4
Refer to Section 4.2.4
Refer toTable 4-10
63h
63h
63h
65h
65h
66h
E_TEMP_WIN [7:0]
67h
E_MODV_SEL [7]
68h
E_MOD_FBRT [6:0]
E_BIAS_FBRT [6:0]
E_TEMPALM [7:0]
68h
69h
6Ah
< MS0290-E-01>
-39-
Refer to Table 5-2
2004/8
ASAHI KASEI
[AK2572]
Table 9-5 EEPROM : Adjustment Data Setting Map (“0” must be written where data bit is marked with “0”)
Address
D7
D6
D5
D4
D3
D2
D1
D0
VREFTRIM
TEMP_OFFSET
60h
61h
PWR_SEL
BURST_ALM
BURST
_SET
PWR_LVL2
_SET
SFP_SET
PWR_LVL1
_SET
62h
APC_FF_SET
APC_FB_SET
APC_INIT
_SET
DAC3
_GAIN
DAC2
_GAIN
DAC1
_GAIN
63h
0
EXTALM2 EXTALM1
_POL
_POL
TEMP
_DET
64h
TIMER_
OPTALM
OPTALM
PDGAIN
65h
0
0
66h
TEMPALM
_SET
0
67h
68h
69h
6Ah
DAC_SET
EXTALM2 EXTALM1
_SET
_SET
0
CURRALM
_SET
OPTALM
_SET
TIMER_
EXTALM2
TIMER_
EXTALM1
0
0
0
0
0
TEMP_WIN
MODV
_SEL
－
MOD_FBRT
BIAS_FBRT
TEMPALM
9.5 Register Configuration
In Table 9-6 and Table 9-7, Register configuration is shown. As to the access limitations via Digital I/F, please
refer to Table 9-1. Details of “ R/W ” column and “ Form “ column in Table 9-6 are described below.
(1) “R/W” column
R:
Read only operation is possible in Adjustment Mode and in Self-Operation Mode when Write Protect
operation is released. Writing the data into these Registers via Digital I/F is impossible.
R/W : Read / Write operation is possible in Adjustment Mode, and Read operation is possible in
Self-Operation Mode when Write Protect operation is released.
Data written via Digital I/F is retained till operation mode is altered or data is modified. The AK2572
allows LD module adjustment at the product shipment by modifying the data in R/W registers.
R/FW: In addition to R/W function above, Read / Write operation is possible in Self-Operation Mode when
Write Protect operation is released.
(2) “Form“ column
U : Unsigned
S : Signed （2’s Complement ）
Table 9-6 Register Configuration
Register
Address
R_VREFTRIM [7:4]
00h
R_TEMP
00h
_OFFSET [3:0]
Function
On-chip oscillator frequency
Bit Form R/W
4
U R/W
Temperature sensor offset
4
U
R/W
Note
R_PWR_SEL [7:6]
01h
EEPROM data switching at
Power Leveling [2]
2
U
R/W
R _BURST_ALM [5:4]
01h
EXTALM mask setting at
Burst mode
2
U
R/W
R _BURST_SET [3]
R_PWR_LVL2
_SET [2]
R_SFP_SET [1]
R_PWR_LVL1_SET [0]
01h
Burst mode setting
1
U
0:Non-masked, 1:Masked
[5]: EXTALM2,
[4]: EXTALM1
R/W
0:OFF, 1:ON
01h
Power Leveling [2] setting
1
U
R/W
0:OFF, 1:ON
01h
01h
SFP_MSA support setting
Power Leveling [1] setting
１
1
U
U
R/W
R/W
0:ON, 1:OFF
Refer to Table 5-1
< MS0290-E-01>
-40-
Refer to Table 5-2 [*1]
2004/8
ASAHI KASEI
[AK2572]
Table 9-6 Register Configuration (Continued)
Register
Address
Function
R_APC_FF_SET [7:6]
02h
APC FF setting
R_APC_FB_SET [5:4]
02h
APC FB setting
R_APC_INIT_SET [3]
02h
APC_FB initial value setting
R_DAC3_GAIN [2]
02h
V-DAC3 gain setting
1
U
R/W
R_DAC2_GAIN [1]
R_DAC1_GAIN [0]
R_TIMER
_OPTALM [6]
R_EXTALM2_POL [5]
R_EXTALM1_POL [4]
02h
02h
1
1
U
U
R/W
R/W
1
U
R/W
1
1
U
U
R/W
R/W
R_TEMP_DET [3]
03h
I-DAC2 gain setting
I-DAC1 gain setting
OPTALM mask time setting
for SFP_TXFAULT detection
EXTALM2 polarity setting
EXTALM1 polarity setting
Temperature difference
detection at Shutdown release
1
U
R/W
R_DAC_SET [2:0]
03h
3
U
R/W
R_OPTALM [7:6]
R_PDGAIN [5:0]
04h
04h
2
6
U
U
R/W
R/W
Note
Refer to Table 4-6
Refer to Table 4-6
0: OFF, 1: ON
0:Gain＝1
1:Gain＝1.2/2.2
0:Gain＝1/2, 1: Gain＝1
0:Gain＝1/10, 1: Gain＝1
0:160ms, 1:2ms [Typ.]
(Refer to Table 8-1)
0:“H” active, 1:“L” active
0:“H” active, 1:“L” active
0:OFF, 1:ON
Refer to Section 7.2
0:OFF, 1:ON
[2] : V-DAC3,
[1] : I-DAC2
[0] : I-DAC1
0:1/3, 1:1/4, 2:1/6, 3:1/7
Refer to Table 4-3
1
U
R/W
0:OFF, 1:ON (Target)
1
U
R/W
0:OFF, 1: ON (Target)
1
U
R/W
0:OFF, 1: ON (Target)
1
U
R/W
1
U
R/W
1
U
R/W
1
U
R/W
0:OFF, 1: ON (Target)
0:0ms , 1:2ms [Typ.]
（Refer to Table 8-2）
0:0ms , 1:2ms [Typ.]
（Refer to Table 8-2）
0:OFF, 1: ON (Target)
8
U
R/W
Refer to Section 7.2 and
Table 4-10
1
U
R/W
Refer to Table 3-4
7
U
R/W
Refer to Section 4.2.4
7
U
R/W
Refer to Section 4.2.4
8
5
8
8
U
U
U
U
R/W Refer to Table 4-10 [*2]
R/W
Refer to Table 4-4
R/W
I-DAC1 or V-DAC3
R/W
I-DAC2
V-DAC3 or I-DAC1
R/W
(DAC isn’t for Imod)
R_EXTALM2_SET [5]
R_EXTALM1_SET [4]
R_CURRALM_SET [3]
R_OPTALM_SET [2]
R_TIMER
_EXTALM2 [1]
R_TIMER
_EXTALM1 [0]
R_TEMPALM_SET [7]
R_TEMP_WIN [7:0]
R _MODV_SEL [7]
R_MOD_FBRT [6:0]
R_BIAS_FBRT [6:0]
R_APC_FBIV [7:0]
R_APC_TRGT [4:0]
R_MOD_FF [7:0]
R_BIAS_FF [7:0]
R_EXTRA [7:0]
R_CURRALM
_BIAS [7:4]
R_CURRALM
_MOD [3:0]
< MS0290-E-01>
03h
03h
03h
DAC operation setting
OPTALM threshold
PD gain setting
EXTALM2 setting for
05h
TXFAULT
EXTALM1 setting for
05h
TXFAULT
CURRALM setting for
05h
TXFAULT
05h OPTALM setting for TXFAULT
EXTALM2 mask time setting
05h
for SFP_TXFAULT detection
EXTALM1 mask time setting
05h
for SFP_TXFAULT detection
06h Set TEMPALM for TXFAULT
Window setting for
07h
Temperature difference
detection
DAC setting for Imod (Data
08h
setting for I-DAC1, V-DAC3)
APC_FB dividing value for
08h
Imod
APC_FB dividing value for
09h
Ibias
0Ah
APC FB initial value
0Bh
APC target setting
0Ch
APC_FF value for Imod
0Dh
APC_FF value for Ibias
Bit Form R/W
2
U R/W
2
U R/W
1
U R/W
0Eh
EXTRA DAC value
8
U
0Fh
CURRALM setting for Ibias
4
U
R/W
Refer to Section 6.3
0Fh
CURRALM setting for Imod
4
U
R/W
Refer to Section 6.3
-41-
2004/8
ASAHI KASEI
[AK2572]
Table 9-6 Register Configuration (Continued)
Register
Address
Function
Bit Form R/W
Temperature equivalent value
R_TEMP [7:0]
10h
8
U
R
(AD code of temperature sensor)
R_TEMP
Temperature equivalent value at
14h
8
U
R
_STDW [7:0]
just before Shutdown request
R_TXFLT_ST
[4:0]
19h
Alarm status
5
U
R
R_DAC1 [7:0]
R_DAC2 [7:0]
R_DAC3 [7:0]
1Bh
1Ch
1Dh
I-DAC1 value
I-DAC2 value
V-DAC3 value
8
8
8
U
U
U
R
R
R
R_APC_FB [7:0]
1Eh
APC_FB value
8
S
R
R_MODE [2:0]
1Fh
Operation mode
3
U
R
AKM test
28h~2Bh
2Eh
For AKM test
－
－
－
Note
Refer to Table 4-10
Refer to Section 7.2 and
Table 4-10
1: Active, 0: Inactive
[4] TEMPALM
[3] EXTALM2
[2] EXTALM1
[1] CURRALM
[0] OPTALM
[*3]
[*3]
[*3]
[7]Sign of APC_FB [*2]
[6:0] Upper 7bits of APC_FB
001:Self-Operation Mode
010:Adjustment Mode
100:EEPROM Access Mode
R_PWR
EEPROM data switching at
2Fh
2
U R/FW
Refer to Table 5-2 [*1]
_SEL [1:0]
Power Leveling [2]
［*1］ Finally modified value in either R_PWR_SEL [7:6] (R/W) at address “01h” or R_PWR_SEL [1:0] (R/FW) at
address “2Fh” becomes valid R_PWR_SEL set value and is updated and retained in R_PWR_SEL at both
address locations. And with R_PWR_LVL1_SET＝“0” and R_PWR_LVL2_SET＝“1”, Power Leveling[2] is
available and write in Self-Operation Mode can be executable only to R_PWR_SEL [1:0] (R/WF) at address
“2Fh” when Write Protect operation is released.
［*2］ Data configuration is shown in Figure 9-9. Register is configured with the signed 9 bits data, but Read /
Write operation via Digital I/F is processed in 8 bits configuration.
［*3］ In Bias current setting DAC and Modulation current setting DAC, Digital code for DAC is given as following
equation and negative value at R_DACx is set to “0”.
R_DACx＝R_DACx_FF＋R_DACx_FB (x＝1 ~ 3)
Figure 9-9 Signed Register Configuration
Register (9 bits 2's complement)
Body (8 bits)
Sign
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read data via Digital I/F (R_APC_FB)
(Sign + Body [MSB 7 bits])
Write data via Digital I/F （R_APC_FBIV）
(Body 8 bits, Negative value cannot be written
< MS0290-E-01>
-42-
2004/8
ASAHI KASEI
[AK2572]
Table 9-7 Register Map
Address
D7
00h
D6
D5
D4
D3
D2
VREFTRIM
D1
D0
TEMP_OFFSET
01h
PWR_SEL
BURST_ALM
BURST
_SET
PWR_LVL2
_SET
SFP_SET
PWR_LVL1
_SET
02h
APC_FF_SET
APC_FB_SET
APC_INIT
_SET
DAC3
_GAIN
DAC2
_GAIN
DAC1
_GAIN
03h
0
EXTALM2 EXTALM1
_POL
_POL
TEMP
_DET
04h
TIMER_
OPTALM
OPTALM
PDGAIN
05h
0
0
06h
TEMPALM
_SET
0
EXTALM2 EXTALM1
_SET
_SET
0
CURRALM
_SET
OPTALM
_SET
TIMER_
EXTALM2
TIMER_
EXTALM1
0
0
0
0
0
07h
TEMP_WIN
08h
MODV
_SEL
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
~13ｈ
14h
15h
~ 18ｈ
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
~ 27ｈ
－
－
MOD_FBRT
BIAS_FBRT
APC_FBIV
－
APC_TRGT
－
MOD_FF
BIAS_FF
EXTRA
CURRALM_BIAS
CURRALM_MOD
TEMP
－
－
－
－
－
－
－
－
－
－
－
TEMP_STDW
－
－
－
－
－
TXFLT_ST
－
－
－
STATUS
DAC1
DAC2
DAC3
R_APC_FB [8:1]
－
－
－
－
－
－
28h
~ 2Bh
2Ch
2Dh
2Eh
2Fh
DAC_SET
－
MODE
－
－
－
－
－
－
Reserved (For AKM test)
－
－
－
－
－
－
－
－
Reserved (For AKM test)
< MS0290-E-01>
－
-43-
－
－
PWR_SEL
2004/8
ASAHI KASEI
[AK2572]
10. Operation Modes
The AK2572 has the following 3 operation modes － Self-Operation Mode where temperature compensation
operation is automatically executed in accordance with EEPROM setting, Adjustment Mode where each LD
adjustment is made and EEPROM Access Mode where adjusting data is written into EEPROM.
10.1 Self-Operation Mode
With the On-chip oscillator, those functions as temperature detection, read out of temperature compensation
data from EEPROM and LD drive current setting by APC control, are automatically executed. At the
Power-on, the AK2572 is put into Self-Operation Mode.
10.2 Adjustment Mode
This is a mode to adjust each LD characteristic. When the device is put into this mode, the temperature
compensation operation stops and various setting data can be written via Digital I/F. Adjustment is made by
accessing the internal Register via Digital I/F.
10.3 EEPROM Access Mode
This is a mode to write LD adjusting data and various set-up data into EEPROM.
10.4 Mode Control
In Figure 10-1, “Mode Transition Flow Chart” is shown. Transition to each mode is controlled by some
commands (Refer to Section 10.5) via Digital I/F. Access to Digital I/F is prohibited for 2 msec [Typ.] after the
transition to Self-Operation Mode is made (After the Power-on and after issuing Operation mode change
command). Accessible EEPROM / Register via Digital I/F in each operation mode is listed in Table 10-1.
Figure 10-1 Mode Transition Flow Chart
Adjustment
Mode
Hold data
in Register
Start-up
Power
ON
Self-Operation
Mode
Shutdown
Start-up
Shutdown
EEPROM
Access Mode
Table 10-1 Operational Conditions in Each Mode
R_WP_CTRL
EEPROM
Register
Operation mode
WP-pin
[*1]
Read
Write
Read
Write
－
○
[*2]
×
×
×
L
Fixed at Self-Operation Mode
×
×
× [*1]
1
Fixed at Self-Operation Mode ○ [*2]
○
×
○
× [*1][*3][*5]
Self-Operation Mode
H
0 [*4]
○
×
○
○ [*5] [*6]
Adjustment Mode
○
○
×
× [*5]
EEPROM Access Mode
[*1] If WP-pin＝“H”, writing into R_PASSWD is always possible in Self-Operation Mode. When R_PASSWD
and E_PASSWD agree, writing into R_WP_CTRL becomes possible.
[*2] When Write Protect is enabled (WP-pin＝“L” or R_WP_CTRL＝“1”), Self-Operation Mode is set as the
operating mode and Read Only operation is possible at Device Address＝“A0h”.
[*3] When Write Protect is released, writing into R_PWR_SEL[1:0] at Address＝”A8h / 2Fh” in Self-Operation
Mode is possible. Power Leveling[2] is enabled at R_PWR_LVL1_SET＝”0”、R_PWR_LVL2_SET＝”1”.
[*4] Full access is possible when Write Protect is released (WP-pin＝”H” and R_WP_CTRL＝”0”).
[*5] “Operation Mode Change command “ can be executed.
[*6] In Adjustment Mode, when R_SFP_SET is modified, the access via Digital I/F cannot be made for 80 msec
[Typ.] from the data modification.
< MS0290-E-01>
-44-
2004/8
ASAHI KASEI
[AK2572]
10.5 Operation Mode Change Commands
Transition to each mode is made by Operation Mode Change command via Digital I/F.
In Table 10-2, a list of Operation Mode Change commands is shown.
Table 10-2 Operation Mode Change Commands
Device Address
R/W
Address
Data
1010 100
W
1111 1111
1010 0000
1010 100
W
1111 1111
1010 0111
1010 100
W
1111 1111
1010 1110
Operation mode set by command
Self-Operation Mode
Adjustment Mode
EEPROM Access Mode
10.6 Mode Protection
In order to protect from shifting into Adjustment Mode or EEPROM Access Mode due to un-expected external
hazard such as noise during Self-Operation Mode, WP-pin = “L” or R_WP_CTRL＝“1” should be set to inhibit
the above erroneous operation.
< MS0290-E-01>
-45-
2004/8
ASAHI KASEI
[AK2572]
11. Example of Adjusting Sequence
Adjusting sequence example is shown in Table 11-1.
Table 11-1 Example of Adjusting Sequence (for Continuous mode)
Item
Contents
1
Transition to
After releasing the Write Protection, issue a command to make a transition
Adjustment Mode
into Adjustment Mode via Digital I/F.
2
Set APC_FB in
Set R_APC_FB_SET=”0” 、 R_APC_FF_SET=”3”, and Bias current and
open-loop operation
Modulation current are set to open-loop operation. Output current range of
I-DAC1 (or V-DAC3) for Modulation current and I-DAC2 for Bias current is
set by R_DAC1_GAIN (or R_DAC3_GAIN) and R_DAC2_GAIN respectively.
3
LD power adjustment Set R_MOD_FF (Modulation current) and R_BIAS_FF (Bias current) so that
designated LD power is available.
4-A PDGAIN adjustment
Adjust PDMON-pin voltage when the designated LD power is output.
(When to monitor
Adjust PDMON-pin output voltage to be 1 [V] by R_PDGAIN.
PDMON-pin voltage)
Set R_APC_TRGT (APC target)＝”1 0000” (its center value), and after
making APC setting (R_APC_FB_SET, R_APC_FF_SET, R_MOD_FBRT
and R_BIAS_FBRT when both Bias and Modulation currents are used for
APC_FB setting), jump to “Step 5” in this table.
4-B PDGAIN adjustment
Set R_APC_TRGT (APC target)＝”1 0000” (its center value) and R_PDGAIN
(When to monitor
＝ ”00 0000” (23.5dB, Maximum gain), then make APC setting
PDMON-pin voltage is (R_APC_FB_SET, R_APC_FF_SET, R_MOD_FBRT and R_BIAS_FBRT
impossible)
when both Bias and Modulation currents are used for APC_FB setting),
Then APC_FB function is activated and LD power is lowered. Adjust
R_PDGAIN so that LD power reaches a closest amount to the designated
power level, and jump to “Step 5” in this table.
5
APC_FB
Adjust DAC_APC setting value (R_APC_TRGT) so that LD optical power
target adjustment
reaches its designated power level.
6
Read-out of sensed
Read out the LSI chip-surface temperature equivalent value (R_TEMP).
temperature data
7
Calculation of
In order to adjust the temperature characteristic of LD, vary temperature
temperature
and repeat “Steps 2 ~ 6” above when adjustment is made at 2 different
characteristic
temperature points or more and make the look-up table of I-DAC1 (or
V-DAC3) and I-DAC2 with referring the measured data
If the adjustment is executed at single temperature point, make the look-up
table with the measured data and On-chip temperature sensor gain (1.5 ℃
/LSB [Typ.]).
8
Write the adjustment
(1) Prepare the data to be written into EEPROM based on LD adjusting data.
(2) Issue a command to make a transition into EEPROM Access Mode via
data into EEPROM
Digital I/F.
(3) Write adjusting data into EEPROM.
(4) Verify that correct data is written, by reading out the written data.
9
Transition to
After writing data into EEPROM, issue a command to make a transition to
Self-Operation Mode
Self-Operation Mode via Digital I/F. Then the AK2572 automatically initiates
its operation in accordance with the setting data retained in EEPROM.
< MS0290-E-01>
-46-
2004/8
ASAHI KASEI
[AK2572]
Ⅵ. EXTERNAL CIRCUIT EXAMPLE
Recommended External Circuit
LDD
LD
Voltage Output
(VDAC3)
Cvout
Current
Output
(IDAC1)
Rvout
Current
Output
(IDAC2)
C13
VDD=3.3V[typ]
PDMON
VSSBI
IOUT2
Monitor PD
VSSBI
VDDBI
IOUT1
C24
VOUT3
C14
VDDMD
C23
Cpd
Rpd
BIASMON
TEMPMON
PDIN
BIAS
AVSS
LDD
Current Output
(BIASMON)
R11
AK2572
EXTALM1
Extalm1
C22
AVDD
EXTALM2/MOD_CTRL
R23
TXDIS
Extalm2/Mod_ctrl
Open
C12
Tx_disable
TEST4
BURST
Burst
WP
Mod_def1
SDA
TXFAULT
DVSS
DVDD
TEST3
TEST2
TEST1
SCL
R21
* When Write Protect is Released :
WP-pin is left Open or connected
to DVDD (Set R_WP_CTRL='0')
* When Write Protect is Established :
WP-pin is left Open (Set R_WP_CTRL='1')
or connected to DVSS
C11
Mod_def2
Tx_fault
VSS=0V
R11=12kΩ±1%
fpd=1/(2π*Rpd*Cpd)=5kHz～10kHz
Rvout=1kΩ
R21=R22=R23=4.7kΩ～10kΩ
C11=C12=C13=C14=0.1μF
Cvout=0.01μF
C21=C22=C23=C24=0.01μF or 0.001μF
< MS0290-E-01>
R22
C21
-47-
Connection of Unused pins :
BURST=VSS EXTALM1=VSS
TXDIS=VSS EXTALM2/MOD_CTRL=VSS
PDIN=VSS
2004/8
ASAHI KASEI
[AK2572]
[A] Example of the connection to the LDD controlled by AK2572 voltage output for CW LD
Current
Control
LD
IMODN
IMOD
DATA
FF
CLK
Selector
LDD (CW)
DUTY
_ADJ
DATAALM
Voltage
Control
AK2572
(E_MOD_TC)
EXTALMx
(E_EXTRA_TC)
Monitor
PD
V-DAC3
Vdac3
Vmod
Rv
Cv
Idac1
I-DAC1
Vextra
Ri
BIASMON
Ci
(x0.012)
PDIN
Cpd
Voltage
Control
Rpd (E_BIAS_TC)
Idac2
I-DAC2
Ibias
[B] Example of the connection to the LDD controlled by AK2572 current output for CW LD
LD
IMODN
Current
Control
IMOD
DATA
FF
CLK
Selector
LDD (CW)
DUTY_
ADJ
DATAALM
Voltage
Control
AK2572
(E_EXTRA_TC)
V-DAC3
Idac1
(E_MOD_TC)
< MS0290-E-01>
Imod
Cv
I-DAC1
BIASMON
(x0.012)
PDIN
Cpd
Vextra
Rv
EXTALMx
Monitor
PD
Vdac3
Current
Control
Rpd (E_BIAS_TC)
I-DAC2
Idac2
-48-
Ibias
2004/8
ASAHI KASEI
[AK2572]
[C] Example of the connection to the LDD controlled by AK2572 current output for Burst transmission
LD
IMODN
IMOD
IBIAS
IBIASN
LDD (Burst)
FF
CLK
DUTY_
ADJ
Selector
DATA
BURST_
CONTROL
Voltage
Control
AK2572
(E_EXTRA_TC)
V-DAC3
Vdac3
Vextra
Rv
BURST_
CONTROL BURST
(E_MOD_TC)
I-DAC1
Idac1
BIASMON
Current
Control
Current
Control
Imod
Ibias
Cv
Ibiasmon
(x0.012)
(E_BIAS_TC)
< MS0290-E-01>
I-DAC2
-49-
2004/8
ASAHI KASEI
[AK2572]
IMPORTANT NOTICE
l These products and their specifications are subject to change without notice.
Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales
office or authorized distributor concerning their current status.
l AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
l Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
l AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function
or perform may reasonably be expected to result in loss of life or in significant injury or damage to
person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
l It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
< MS0290-E-01>
-50-
2004/8