HITACHI HD155121F

HD155121F
RF Transceiver IC for GSM and PCN Dual band cellular systems
ADE-207-265A (Z)
2nd Edition
May 1999
Description
The HD155121F is a RF transceiver IC for GSM and PCN dual band cellular systems, and integrates most
of the low power silicon functions of a transceiver. The HD155121F incorporates two bias circuits for RF
LNAs, two first mixers, a second mixer, a programmable gain amplifier, and an IQ demodulator for the
receiver, and an IQ modulator and offset PLL for the transmitter. Also, on chip are dividers for the phase
splitter. Moreover the HD155121F includes control circuits to implement power saving modes. These
functions can operate down to 2.7 V and are housed in a 48-pin LQFP SMD package.
Hence the HD155121F can form a small size transceiver handset for dual band by adding a dual PLL
frequency synthesizer IC, power amplifiers and some external components.
The HD155121F is fabricated using a 0.6 µm double-polysilicon Bi-CMOS process.
Functions
Receiver(Rx)
•
•
•
•
•
Low Noise Amplifier (LNA) bias circuit
First mixer
IF amplifier and second mixer
Programmable Gain Amplifier (PGA)
IQ demodulator with 90 degree phase splitter
Transmitter(Tx)
• IQ modulator with 90 degree phase splitter
• Offset PLL
 Down converter
 Phase comparator
 TXVCO driver
Others
• IF dividers
• Power saving control circuit
• IFVCO
HD155121F
Features
• Highly integrated RF processing for hand-portables
• Operating supply voltage
 VCC : 2.7 to 3.6 V
 Phase comparator and TXVCO driver circuit : 2.7 to 5.25 V
• Current consumption
 Rx mode (GSM) : 53 mA + LNA current
 Rx mode (PCN) : 52 mA + LNA current
 Tx mode (GSM) : 36 mA
 Tx mode (PCN) : 37 mA
 Idle mode :1 µA
• Operating temperature : –20 to +75 degree
• LQFP 48pin SMD (Low Profile Quad Flat Package)
• Wide operating frequencies
 Rx
RF
GSM : 925 - 960 MHz
PCN : 1805 - 1880 MHz
1st IF
: 225 MHz
2nd IF
: 45 MHz
 Tx
RF
GSM : 880 - 915 MHz
PCN : 1710 - 1785 MHz
IF
GSM : 270 MHz
PCN : 135 MHz
• Offset PLL architecture for Transmitter
• High dynamic range Programmable Gain Amplifier (PGA)
2
HD155121F
MIX1IN2
MIX1INB2
POONTX
POONRX2
POONRX1
MIX1OUTB
MIX1OUT
VCCMIX1
GNDMIX1
RFLOIN
VCCDIV
GNDDIV
Pin Arrangement
48
47
46
45
44
43
42
41
40
39
38
37
36
4
33
IFVCOI
RFIN2
5
32
VCCIF
VCCPLL
6
31
GNDIF
GNDPLL
7
30
IFIN
VCOIN2
8
29
IFINB
VCOIN1
9
28
LE
VCCCOMP
10
27
SDATA
PLLOUT
11
26
CLK
ICURAD
12
13
15
16
17
18
19
20
21
22
23
25
24
IFLO
MIX2O
MIX2OB
14
IOUT
RFIN1
IOUTB
IFVCOO
QOUT
34
QOUTB
3
GNDIQ
RFOUT
VCCIQ
BAND
MODLB
35
IIN
2
IINB
MIX1IN1
QIN
1
QINB
MIX1INB1
(Top View)
3
HD155121F
Pin Description
Pin No.
Pin Name
Description
1
MIX1INB1
Negative input for Mixer1 (GSM)
2
MIX1IN1
Positive input for Mixer1 (GSM)
3
RFOUT
Bias for the collector of LNA transistor
4
RFIN1
Bias for the base of LNA transistor (GSM)
5
RFIN2
Bias for the base of LNA transistor (PCN)
6
VCCPLL
VCC for OPLL
7
GNDPLL
GND for OPLL
8
VCOIN2
TxVCO signal input (PCN)
9
VCOIN1
TxVCO signal input (GSM)
10
VCCCOMP
VCC for phase comparator
11
PLLOUT
Current output to control and modulate the TxVCO
12
ICURAD
Phase comparator output current setting
13
QINB
Negative input of Q signal for modulator
14
QIN
Positive input of Q signal for modulator
15
IINB
Negative input of I signal for modulator
16
IIN
Positive input of I signal for modulator
17
MODLB
VCC for modulator load bias
18
VCCIQ
VCC for IQ modulator and demodulator
19
GNDIQ
GND for IQ modulator and demodulator
20
QOUTB
Negative output of Q signal for modulator
21
QOUT
Positive output of Q signal for modulator
22
IOUTB
Negative output of I signal for modulator
23
IOUT
Positive output of I signal for modulator
24
MIX2OB
Negative output for Mixer2
25
MIX2O
Positive output for Mixer2
26
CLK
Clock for serial data
27
SDATA
Serial data for Gain control
28
LE
Load enable for serial data
29
IFINB
Negative input for Mixer2
30
IFIN
Positive input for Mixer2
31
GNDIF
GND for Mixer2 and PGA
32
VCCIF
VCC for Mixer2 and PGA
33
IFVCOI
Base of IFVCO transistor
34
IFVCOO
Emitter of IFVCO transistor
4
HD155121F
Pin Description (cont)
Pin No.
Pin Name
Description
35
BAND
Band control (Low: GSM, High: PCN)
36
IFLO
Output of IFVCO or Input of IF Local
37
GNDDIV
GND for Divider and IFVCO
38
VCCDIV
VCC for Divider and IFVCO
39
RFLOIN
Input for RF Local
40
GNDMIX1
GND for Mixer1
41
VCCMIX1
VCC for Mixer1
42
MIX1OUT
Positive output for Mixer1 (GSM/PCN)
43
MIX1OUTB
Negative output for Mixer1 (GSM/PCN)
44
POONRX1
Power save control for LNA and Mixer1
45
POONRX2
Power save control for Mixer2, PGA and demodulator
46
POONTX
Power save control for modulator and OPLL
47
MIX1INB2
Negative input for Mixer1 (PCN)
48
MIX1IN2
Positive input for Mixer1 (PCN)
5
6
from Antenna
ICURAD
PLLOUT
VCCCOMP
VCOIN1
RICURAD
Tx.VCO2 Tx.VCO1
902MHz
VCOIN2
12
11
10
9
8
7
6
5
13
Current
mode
driver
270MHz
(135MHz)
Vref
(PLL)
14
15
1172MHz
(1580/
1575MHz)
Vref
(LNA)
16
17
Vref
(Mod)
GSM: 270MHz
PCN: 135MHz
270MHz
(135MHz)
18
19
Vref
(Demod)
45MHz
(45MHz)
20
39
21
Vref
(PGA)
22
1/2
(90deg)
from
Band
SW
Vref
(Div.Rx)
(Div.Tx)
40
Vref
(IF)
45MHz
(45MHz)
41
QOUT
IINB
QIN
QINB
1/2
to Base band
IOUTB
from Base band
42
(1580/1575MHz) 1172MHz
Vref
(Mix1)
43
540
MHz
37
23
24
Serial
interface
1/2
(90deg)
1/6
Vref
(IFVCO)
38
25
26
27
28
29
30
31
32
33
34
35
36
45MHz
MIX2O
CLK
SDATA
LE
IFINB
IFIN
GNDIF
VCCIF
IFVCOI
IFVCOO
BAND
IFLO
225MHz
(225MHz)
from
System controller
(1710MHz)
GNDPLL
VCCPLL
RFIN2
4
MIX1IN2
RFIN1
MIX1INB2
LNA
Bias
circuit
POONTX
3
POONRX2
RFOUT
POONRX1
44
MIX1OUTB
45
MIX1OUT
46
VCCMIX1
47
GNDMIX1
48
RFLOIN
2
1
VCCDIV
1172MHz
(Rx: 1580MHz, Tx: 1575MHz)
MIX1IN1
MIX1INB1
from VCO
225MHz
(225MHz)
GNDDIV
(1805MHz)
947MHz
947MHz
(1805MHz)
from System controller
Tune
HD155121F
Block Diagram
from System controller
MIX2OB
IOUT
QOUTB
GNDIQ
VCCIQ
MODB
IIN
RF
filter
PLL2
880 to 915 MHz
PA Module
HD155017T
1710 to 1785 MHz
LPF
LPF
RF
SAW
filter
RF
SAW
filter
RF VCO
PLL1
bias
circuit
LNA
bias
circuit
LNA
Dual
synth.
1805 to
1880 MHz
S/W
RF
filter
925 to 960 MHz
1710 to 1785 MHz
Loop
filter
GSM: 540 MHz
PCN: 540 MHz
IFVCO
÷6
GSM: 540 MHz
PCN: 270 MHz
Phase
Detector
I&Q
Demo.
I&Q
Mod
GSM: 270 MHz
PCN: 135 MHz
90 deg
Shift
÷2
90 deg
Shift
÷2
45 MHz
Serial data
interface
PGA
HD155121F
45 MHz
LC
GSM: 270 MHz
PCN: 135 MHz
÷2
270 MHz
Mixer2
GSM: 1150 to 1185 MHz
PCN : Rx. 1580 to 1655 MHz
/Tx. 1575 to 1650 MHz
IF
SAW
filter
225 MHz
880 to 915 MHz
Mixer1
Mixer1
I
I
Q
B.B.
Block
Q
HD155121F
Configuration
7
HD155121F
Functional Operation
The HD155121F has been designed from system stand point and incorporated a large number of the circuit
blocks necessary in the design of a digital cellular handset.
Receiver Operation
The HD155121F incorporates two LNA bias circuits for external RF transistors, whose NF and power gain
can be better selected.
This circuit amplifies the RF signal after selection by the antenna filter before the signal enters the first
mixer section. The RF signal is combined with a local oscillator (LO) signal to generate a wanted first IF
signal in the 130 - 300 MHz range. The first mixer circuit uses a double-balanced Gilbert cell architecture,
which has open collector differential outputs. If, at 225 MHz, a 800 Ω LC load is connected to the mixer’s
outputs then a SSB NF of 9.0 dB (GSM), 9.1 dB (PCN) with a gain of 9.5 dB (GSM), 8.5 dB (PCN) is
realizable. The corresponding input compression point is –10.5 dBm (GSM), –12.5 dBm (PCN), which
allows the device to be used within a GSM and EGSM and PCN system.
A filter is used after the first mixer to provide image rejection and the conditioned signal is then passed
through an intermediate amplifier, before being down converted to a second IF in the range of 26 - 60
MHz.
The second mixer can generate a 45 MHz second IF, if a 270 MHz second local signal is used. The second
mixer also uses the Gilbert cell architecture, but with internal resistive differential outputs of 300 Ω. If
amplifier and second mixer has a SSB NF of 6.0 dB, a power gain of 13 dB and a input compression point
of –22 dBm. In order to improve the blocking characteristics of the device an external LC resonator across
the differential outputs of the second mixer is recommended.
First mixer and second mixer can switch the power gain. Switching gain step of first mixer is 12 dB, and
such step of second mixer is 16 dB.
The signal is then passed to the PGA circuit, which has a dynamic range of more than 80 dB (–42 dB - +56
dB typ.) and is controlled by digital serial data, which is generated by the microprocessor. This gain step is
2 dB.
The signal is then down converted by a demodulator to I and Q. Internal divider circuits convert the IFLO
signal to the same frequency as the second IF before passing this local signal through a phase splitter /
shifter in order to generate the in phase and quadrature phase IQ components. The phase accuracy of the
IQ demodulator is less than +/–1 degree and the amplitude mismatch is less than +/–0.5 dB. In order to
accommodate different baseband interfaces the HD155121F IQ differential outputs have a voltage swing of
1.6 Vpp and DC offset of less than +/–60 mV. Within each output stage a second order Butterworth filter
(fc = 210 kHz) is used to improve the blocking performance of the device.
In order to allow flexibility in circuit implementation the HD155121F can configured to use either a singleended or balanced external circuitry and components.
8
HD155121F
Transmitter Operation
The transmitter chain converts differential IQ baseband signals to a suitable format for transmission by a
power amplifier.
The common mode voltage range of the modulator inputs is 0.8 V to 1.2 V and they have 2.0 Vpp
differential swing. The modulator circuit uses double-balanced mixers for the I and Q paths. The Local
signals are generated by dividing the IFLO signals by 2, and then passed to the modulator through a phase
splitter / shifter. The IF signals generated are then summed to produce a single modulated IF signal which
is amplified and fed into the offset PLL block. Carrier suppression due to the mixer circuit is better than 31
dBc. If the common mode DC voltage of the I and Q inputs is adjusted, carrier suppression is better than
40 dBc easily. Side band suppression is better than 35 dBc without adjustment.
Within the offset PLL block there are a down converter, a phase comparator and a VCO driver. The down
converter mixes the first local signal and the TXVCO signal to create a reference local signal for use in the
offset PLL circuit. The phase comparator and the VCO driver generate an error current, which is
proportional to the phase differential between the reference IF and the modulated IF signals. This current is
used in a second order loop filter to generate a voltage, which in turn modulates the TXVCO. In order to
optimize the PLL loop gain, the error current value can be modified by changing the value of an external
resistor - ICURAD. In order to accommodate various control range of TXVCOs, the offset PLL circuit has
been designed to operate with a supply voltage up to 5.25 V.
9
HD155121F
Operation Modes
The HD155121F has necessary control circuitry to implement the necessary states within the dual band
system. Also provided is a power saving mode which reduces the current consumption of the device by
powering down unnecessary function blocks. Three pins are assigned for power saving mode control,
POONRX1, POONRX2 and POONTX. Also one pin is assigned for switching operational band, BAND.
Table 1 shows the relationship between the pins and the required operating mode. These pins are
controlled by the system controller.
As per GSM requirements the Tx and Rx sections do not operate simultaneously. For the receiver there is a
calibration mode in which the LNA bias circuit and first mixer are switched off. During this period the
gain of the PGA can be adjusted. Also the DC offsets of the IQ demodulator are measured and
subsequently canceled.
In order to change between the Rx and Tx modes a state called “warm-up” is used to ensure that the local
signals are not unduly affected. This method of switching between Tx and Rx ensures that lock is achieved
first time.
Power saving is implemented through use of the idle mode. All function blocks of the HD155121F are
switched off until such time as the system controller commands the device to power up again.
Table 1
Operating Modes with Power Saving
Mode
Receive
Calibrate
Warm-up
Transmit
Band
GSM
PCN
—
—
GSM
PCN
—
POONRX1 (44)
H
H
L
L
L
L
H
POONRX2 (45)
H
H
H
L
L
L
L
POONTX (46)
L
L
L
L
H
H
Don’t care
BAND (35)
L
H
Don’t care
Don’t care
L
H
Don’t care
LNA bias (GSM)
ON
OFF
OFF
OFF
OFF
OFF
OFF
LNA bias (PCN)
OFF
ON
OFF
OFF
OFF
OFF
OFF
1st Mixer (GSM)
ON
OFF
OFF
OFF
OFF
OFF
OFF
1st Mixer (PCN)
OFF
ON
OFF
OFF
OFF
OFF
OFF
2nd Mixer
ON
ON
ON
OFF
OFF
OFF
OFF
PGA
ON
ON
ON
OFF
OFF
OFF
OFF
I/Q demodulator
ON
ON
ON
OFF
OFF
OFF
OFF
Offset PLL
OFF
OFF
OFF
OFF
ON
ON
OFF
Rx block
Tx block
Idle
I/Q modulator
OFF
OFF
OFF
OFF
ON
ON
OFF
Oscillator
IF VCO
ON
ON
ON
ON
ON
ON
OFF
block
Divider (Rx)
ON
ON
ON
OFF
OFF
OFF
OFF
Divider (Tx)
OFF
OFF
OFF
OFF
ON
ON
OFF
1st local buffer
ON
ON
ON
ON
ON
ON
OFF
IF local buffer
ON
ON
ON
ON
ON
ON
OFF
53 mA
52 mA
34 mA
9.0 mA
36 mA
37 mA
1 µA
Total current
10
HD155121F
Absolute Maximum Ratings
Any stress in excess of the absolute maximum ratings can cause permanent damage to the HD155121F.
Item
Symbol
Rating
Unit
Power supply voltage (VCC)
VCC
–0.3 to +4.0
V
Power supply voltage (VCCCOMP)
VCCCOMP
–0.3 to +5.5
V
Pin voltage
VT
–0.3 to VCC+0.3 (4.0 Max)
V
Maximum power dissipation
PT
400
mW
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
11
HD155121F
Electrical Characteristics
DC Specifications (VCC = 3 V, Ta = 25°C unless otherwise specified.)
Item
Mode
Min
Typ
Max
Unit
Test Condition
Note
Power supply voltage (VCC)
2.7
3.0
3.6
V
Power supply voltage (VCCCOMP)
2.7
3.0
5.25
V
GSM
—
53.0
74.0
mA
VCC = 3.0V, VCCCOMP = 3.0V,
2
PCN
—
52.0
73.0
mA
Mixer1, 2 = Gain1,
PGA = bitNo26
GSM
—
36.0
50.0
mA
VCC = 3.0V, VCCCOMP = 3.0V
2
PCN
—
37.0
52.0
mA
Power supply current (Warm-up)
—
9.0
12.5
mA
VCC = 3.0V, VCCCOMP = 3.0V
2
Power saving mode supply current
—
1.0
10.0
µA
VCC = 3.0V, VCCCOMP = 3.0V
High level = VCC, Low level = 0V
at mode control pin and serial
data pin (POONRX1, RX2, TX,
BAND, CLK (no clock signal),
SDATA, LE)
2
Power up time (Rx.)
—
1.5
5.0
µsec
from PS mode
1
Power up time (Tx.)
—
0.2
0.5
µsec
from PS mode
1
Power on control voltage range
(POONRX1, POONRX2, POONTX)
2.3
—
—
V
Power off control voltage range
(POONRX1, POONRX2, POONTX)
—
—
0.8
V
I/Q common-mode output voltage
1.15
1.35
1.55
V
I/Q maximum output swing
(Single ended)
0.8
1.06
—
Vp-p
VIOUT, VIOUTB,
VQOUT, VQOUTB
I/Q output DC offset voltage
–60
0
60
mV
VIOUTDC – VIOUTBDC,
VQOUTDC, VQOUTBDC
I/Q common-mode input voltage
0.8
1.0
1.2
V
I/Q input swing (Single ended)
0.8
1.0
1.2
Vp-p
Serial data VH (CLK, SDATA, LE)
2.3
—
—
V
Serial data VL (CLK, SDATA, LE)
—
—
0.8
V
Band control VH (BAND)
2.3
—
—
V
Band control VL (BAND)
—
—
0.8
V
Input current
(POONRX1, POONRX2, POONTX,
BAND, CLK, SDATA, LE)
–10
0
10
µA
Power supply current (Rx.)
Power supply current (Tx.)
Note:
12
1
VIIN, VIINB, VQIN, VQINB
1. These values are not tested in mass production.
2. Power supply current does not include the LNA bias current.
1
HD155121F
AC Specifications (VCC = 3 V, Ta = 25°C unless otherwise specified.)
• LNA Bias circuit specifications
Item
Mode
Min
Typ
Max
Unit
LNA transistor bias current
GSM
4.7
5.6
—
mA
PCN
4.7
5.6
—
mA
GSM
925
—
960
MHz
PCN
1805
1880
MHz
GSM
—
19.4
—
dB
RF = 940 MHz
PCN
—
13.4
—
dB
RF = 1842 MHz
GSM
—
1.6
—
dB
RF = 940 MHz
PCN
—
1.6
—
dB
RF = 1842 MHz
GSM
—
–6.0
—
dBm
PCN
—
–2.0
—
dBm
GSM
—
13
—
dBm
PCN
—
11
—
dBm
GSM
—
–14.5
—
dBm
PCN
—
–9.5
—
dBm
GSM
—
3.9
—
dBm
PCN
—
2.9
—
dBm
GSM
—
50
—
Ω
Output (GSM RF)
PCN
—
50
—
Ω
Output (PCN RF)
GSM
—
50
—
Ω
Input (GSM RF)
PCN
—
50
—
Ω
Input (PCN RF)
Frequency
Power gain
Noise figure
3rd order input intercept point
3rd order output intercept point
1dB input compression point
1dB output compression point
Output (RF) Z
Input (RF) Z
Note:
Test Condition
Note
1
1
1
1
1
1
1
1
1
1. These AC characteristics are shown for reference only and do not form part of the HD155121F
component specification.
13
HD155121F
• Mixer1 specifications (Differential output load between pin42 and pin43 = 800 Ω)
Item
Mode
Min
Typ
Max
Unit
Frequency (RF)
GSM
925
—
960
MHz
PCN
1805
—
1880
MHz
GSM
1125
—
1260
MHz
PCN
1505
—
1680
MHz
Frequency (IF)
—
200
225
300
MHz
RFLO input level
—
–8.0
—
—
dBm
Frequency (LO)
Conversion gain 1
Conversion gain 2
Test Condition
1
1
1
GSM
6.5
9.5
12.5
dB
RF = 940MHz, LO = 1165MHz, IF = 225MHz
PCN
5.5
8.5
11.5
dB
RF = 1842MHz, LO = 1617MHz, IF = 225MHz
GSM
–5.5
–2.5
0.5
dB
RF = 940MHz, LO = 1165MHz, IF = 225MHz
PCN
–6.5
–3.5
–0.5
dB
RF = 1842MHz, LO = 1617MHz, IF = 225MHz
GSM
—
9.0
10.5
dB
RF = 940MHz, LO = 1165MHz, IF = 225MHz
PCN
—
9.1
10.6
dB
RF = 1842MHz, LO = 1617MHz, IF = 225MHz
GSM
—
15.0
16.5
dB
RF = 940MHz, LO = 1165MHz, IF = 225MHz
PCN
—
16.0
17.5
dB
RF = 1842MHz, LO = 1617MHz, IF = 225MHz
GSM
–3.0
–1.0
—
dBm
RF1 = 940.8MHz, RF2 = 941.6MHz,
LO = 1165MHz, IF = 225MHz
PCN
–6.0
–4.0
—
dBm
RF1 = 1842.8MHz, RF2 = 1843.6MHz,
LO = 1617MHz, IF = 225MHz
GSM
1.0
3.0
—
dBm
RF1 = 940.8MHz, RF2 = 941.6MHz,
LO = 1165MHz, IF = 225MHz
PCN
–3.0
–1.0
—
dBm
RF1 = 1842.8MHz, RF2 = 1843.6MHz,
LO = 1617MHz, IF = 225MHz
GSM
6.5
8.5
—
dBm
RF1 = 940.8MHz, RF2 = 941.6MHz,
LO = 1165MHz, IF = 225MHz
PCN
2.5
4.5
—
dBm
RF1 = 1842.8MHz, RF2 = 1843.6MHz,
LO = 1617MHz, IF = 225MHz
GSM
–1.5
0.5
—
dBm
RF1 = 940.8MHz, RF2 = 941.6MHz,
LO = 1165MHz, IF = 225MHz
PCN
–6.5
–4.5
—
dBm
RF1 = 1842.8MHz, RF2 = 1843.6MHz,
LO = 1617MHz, IF = 225MHz
1dB input
GSM
–12.5
–10.5
—
dBm
RF = 940MHz, LO = 1165MHz, IF = 225MHz
compression point 1
PCN
–14.5
–12.5
—
dBm
RF = 1842MHz, LO = 1617MHz, IF = 225MHz
1dB input
GSM
–8.5
–6.5
—
dBm
RF = 940MHz, LO = 1165MHz, IF = 225MHz
compression point 2
PCN
–10.5
–8.5
—
dBm
RF = 1842MHz, LO = 1617MHz, IF = 225MHz
1dB output
GSM
–4.0
–2.0
—
dBm
RF = 940MHz, LO = 1165MHz, IF = 225MHz
compression point 1
PCN
–7.0
–5.0
—
dBm
RF = 1842MHz, LO = 1617MHz, IF = 225MHz
1dB output
GSM
–12.0
–10.0
—
dBm
RF = 940MHz, LO = 1165MHz, IF = 225MHz
compression point 2
PCN
–15.0
–13.0
—
dBm
RF = 1842MHz, LO = 1617MHz, IF = 225MHz
Noise figure 1
Noise figure 2
3rd order input
intercept point 1
3rd order input
intercept point 2
3rd order output
intercept point 1
3rd order output
intercept point 2
Note:
14
Note
1. These values are not tested in mass production.
2. The loss (2.2 dB) of test circuit at Mixer1 output is calculated.
2
2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
2
2
1, 2
1, 2
HD155121F
• Mixer2 specifications
Item
Min
Typ
Max
Unit
Frequency (IF1)
200
225
300
MHz
Frequency (LO2)
240
270
360
MHz
Frequency (IF2)
40
45
60
MHz
IFLO input level
–10
—
—
dBm
Conversion gain 1
10.5
13.0
15.5
dB
IF1 = 225MHz, IFLO = 540MHz, IF2 = 45MHz
2
Conversion gain 2
–5.5
–3.0
–0.5
dB
IF1 = 225MHz, IFLO = 540MHz, IF2 = 45MHz
2
Noise figure 1
—
6.0
7.5
dB
IF1 = 225MHz, IFLO = 540MHz, IF2 = 45MHz
1, 2
Noise figure 2
—
12.0
13.5
dB
IF1 = 225MHz, IFLO = 540MHz, IF2 = 45MHz
1, 2
3rd order input
intercept point 1
–15.0
–13.0
—
dBm
IF1 = 225.8MHz, IF2 = 226.6MHz,
LO = 540MHz, 2ndIF = 45MHz
1, 2
3rd order input
intercept point 2
–11.0
–9.0
—
dBm
IF1 = 225.8MHz, IF2 = 226.6MHz,
LO = 540MHz, 2ndIF = 45MHz
1, 2
3rd order output
intercept point 1
–2.0
0.0
—
dBm
IF1 = 225.8MHz, IF2 = 226.6MHz,
LO = 540MHz, 2ndIF = 45MHz
1, 2
3rd order output
intercept point 2
–14.0
–12.0
—
dBm
IF1 = 225.8MHz, IF2 = 226.6MHz,
LO = 540MHz, 2ndIF = 45MHz
1, 2
1dB input
compression point 1
–24.0
–22.0
—
dBm
IF1 = 225MHz, IFLO = 540MHz, IF2 = 45MHz
2
1dB input
compression point 2
–21.0
–19.0
—
dBm
IF1 = 225MHz, IFLO = 540MHz, IF2 = 45MHz
2
1dB output
compression point 1
–12.0
–10.0
—
dBm
IF1 = 225MHz, IFLO = 540MHz, IF2 = 45MHz
1, 2
1dB output
compression point 2
–24.0
–22.0
—
dBm
IF1 = 225MHz, IFLO = 540MHz, IF2 = 45MHz
1, 2
Isolation
50
—
—
dB
between Mixer1 output and Mixer2 input
1, 2
Note:
Mode
Test Condition
Note
LO2 = IFLO/2
1
1
1
1. These values are not tested in mass production.
2. The loss (3.6 dB) of test circuit at Mixer2 output is calculated.
15
HD155121F
• PGA and IQ Demodulator specifications (terminated by 10 kΩ at IQ demodulator output)
Item
Min
Typ
Max
Unit
Input frequency
40
45
60
MHz
1
Gain range
—
98
—
dB
1
Gain linearity
–0.8
—
0.8
dB
Gain step
—
2
—
dB
Noise figure 1
—
10.9
14
dB
IF2 = 45MHz, bitNo46
1, 2
Noise figure 2
—
21.2
24
dB
IF2 = 45MHz, bitNo26
1, 2
Noise figure 3
—
53.4
60
dB
IF2 = 45MHz, bitNo6
1, 2
Gain 1
47.0
51.5
56.0
dB
IF2 = 45MHz, bitNo46
2
Gain 2
7.0
11.5
16.0
dB
IF2 = 45MHz, bitNo26
2
Gain 3
–33.0
–28.5
–24.0
dB
IF2 = 45MHz, bitNo6
2
i/p CP 1
–70.5
–66
—
dBm
IF2 = 45MHz, bitNo46
2
i/p CP 2
–37
–34
—
dBm
IF2 = 45MHz, bitNo26
2
i/p CP 3
–14
–11
—
dBm
IF2 = 45MHz, bitNo6
2
IQ phase accuracy
—
0.2
1.0
deg.
Baseband = 67.7kHz
IQ amplitude mismatch
—
0.1
0.5
dB
Baseband = 67.7kHz
Output DC offset voltage
0
—
| 60 |
mV
| IOUT–IOUTB | and
| QOUT–QOUTB |
Load out = 10kΩ
IQ maximum output swing
(Single ended)
0.8
1.06
—
Vp-p
Baseband = 67.7kHz
IOUT, IOUTB,
QOUT, QOUTB
Load out = 10kΩ
I/Q common mode
output voltage
1.15
1.35
1.55
V
Note:
16
Mode
1. These values are not tested in mass production.
2. The loss (3.6 dB) of test circuit at PGA input is calculated.
Test Condition
(in any 20dB window)
Note
1
1
2
HD155121F
• IQ Modulator and Offset PLL specifications (IFLO is supplied by signal generator equipment)
Item
Mode
Min
Typ
Max
Unit
Frequency (RF)
GSM
880
—
915
MHz
PCN
1710
—
1785
MHz
GSM
1150
—
1185
MHz
PCN
1530
—
1665
MHz
GSM
—
270
—
MHz
PCN
—
135
—
MHz
RFLO input level
–8
—
—
dBm
IFLO input level
–20
–10
—
dBm
VCOIN1 & VCOIN2 input level
–25
–15
–10
dBm
Carrier suppression ratio
31
40
—
dBc
All ‘1’ GMSK (Differential encode: off)
(Baseband = 67.7kHz)
Side-band suppression ratio
35
40
—
dBc
I/Q input swing = 1.0Vp-p,
I/Q common mode
input voltage = 1.0Vdc
GSM
—
1.0
2.5
RMS
200kHz BW
GSM
—
3.0
7.5
peak
200kHz BW
PCN
—
1.0
2.4
RMS
200kHz BW
PCN
—
3.0
7.0
peak
200kHz BW
GSM
—
–34.0
—
dB
200kHz offset
PCN
—
–34.5
—
dB
30kHz bandwidth
Frequency (LO)
Frequency (IF)
Phase accuracy
Modulation spectrum
Test Condition
1
1
1
Spectrum analyzer condition
GSM
—
–68.0
—
dB
400kHz offset
Detector mode: positive peak
PCN
—
–67.0
—
dB
30kHz bandwidth
GSM
—
–71.0
—
dB
600kHz to 1.8MHz offset
PCN
—
–70.0
—
dB
30kHz bandwidth
GSM
—
–71.5
—
dB
1.8MHz to 3MHz offset
PCN
—
–72.0
—
dB
100kHz bandwidth
GSM
—
–74.0
—
dB
3MHz to 6MHz offset
PCN
—
–74.0
—
dB
100kHz bandwidth
GSM
—
–76.0
—
dB
6MHz upward offset
PCN
—
–76.0
—
dB
100kHz bandwidth
—
43
—
dB
Isolation of the 1st local input to
TxVCO input
Note
1
1
1
1
1
1
1
1
IQ input swing (Single ended)
0.8
1.0
1.2
Vp-p
IIN, IINB, QIN, QINB
1
I/Q common mode input voltage
0.8
1.0
1.2
V
IIN, IINB, QIN, QINB
1
PLLOUT output current ratio
—
1:0.5
—
IPLLOUT GSM : IPLLOUT PCN
1
Phase detector
offset current ratio
0.30
0.35
0.45
offset current / output current
IIN = 1.5V (DC), IINB = 0.5V (DC)
QIN = 1.5V (DC), QINB = 0.5V (DC)
1
Note:
1. These values are not tested in mass production.
17
HD155121F
• IQ Modulator and Offset PLL specifications (IFLO is supplied by signal generator equipment) (cont)
Item
Mode
Min
Typ
Max
Unit
Test Condition
Note
Tx noise
in Rx band
GSM
—
–155.1
—
dBc/Hz
925MHz to 935MHz
- 10MHz up from Txband
1
GSM
—
–164.1
—
dBc/Hz
935MHz to 960MHz
- 20MHz up from Txband
PCN
—
–156
—
dBc/Hz
1805MHz - 20MHz up from Txband
PCN
—
–162
—
dBc/Hz
1850MHz - 65MHz up from Txband
GSM
—
35
80
µsec
PCN
—
65
80
µsec
Lock up time
Note:
1
1. These values are not tested in mass production.
• IFVCO specifications
Item
Bias current
18
Mode
Min
Typ
Max
Unit
0.9
2.0
2.5
mA
Test Condition
HD155121F
Rx Gain Control Stage
The PGA amplifier of the HD155121F is the main Rx gain control stage. However, Mixer1 and Mixer2
gain level can switched as an optional function in order to optimize system performance.
Mixer1
LNA
Mixer2
bias
circuit
I&Q
Demo.
PGA
Mixer1
I
Q
LNA
bias
circuit
Decoder
CLK (26)
SDATA (27)
LE (28)
X7 X6 X5 X4 X3 X2 X1 X0
Serial data
X7 : for Mixer1 gain
X6 : for Mixer2 gain
X5 :
Bit allocation X4 :
X3 :
for PGA gain
X2 :
X1 :
X0 :
Figure 1
Table 2
First Mixer Gain Control Table (as optional function)
Item
Band
Gain (typ)
X7
Gain 1 (normal gain)
GSM
9.5 dB
0
PCN
8.5 dB
0
GSM
–2.5 dB
1
PCN
–3.5 dB
1
Gain 2 (low gain)
Table 3
Second Mixer Gain Control Table (as optional function)
Item
Gain (Typ)
X6
Gain 1 (normal gain)
13.0 dB
0
Gain 2 (low gain)
–3.0 dB
1
19
HD155121F
Table 4
bitNo
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
20
PGA and IQ Demodulator Block Gain Control
Gain (dB)
(Typ)
57.5
55.5
53.5
51.5
49.5
47.5
45.5
43.5
41.5
39.5
37.5
35.5
33.5
31.5
29.5
27.5
25.5
23.5
21.5
19.5
17.5
15.5
13.5
11.5
9.5
7.5
5.5
3.5
1.5
−0.5
−2.5
−4.5
−6.5
−8.5
−10.5
−12.5
−14.5
−16.5
−18.5
−20.5
−22.5
−24.5
−26.5
−28.5
−30.5
−32.5
−34.5
−36.5
−38.5
−40.5
X5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X4
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Allocation
X3
X2
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
X1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
HD155121F
Serial Data Interface
tcyc
tsule
CLK
MSB
SDATA
tstup thld
X7
LSB
X6
X5
X4
X3
X2
X1
X0
LE
twle
Figure 2 Three-Wire Bus Timing Diagram
Serial Data Interface Specifications (VCC = 3 V, Ta = 25°C unless otherwise specified)
Item
Symbol
Min
Typ
Max
Unit
Cycle time
tcyc
50
—
—
nsec
1
Setup time
tstup
10
—
—
nsec
1
Hold time
thld
10
—
—
nsec
1
LE setup time
tsule
25
—
—
nsec
1
LE width
twle
25
—
—
nsec
1
Note:
Test Condition
Note
1. These values are not tested in mass production.
2. User can program the data for the PGA, while in any state.
21
22
390
33 6800p
QIN
TX VCO1
560p
QINB
1000p
MIX1INB2
MURATA
MQE9P7-897
Kv=30MHz/V
4
3
OUT VCC
5
2
GND GND
6 MOD CON 1
IIN
10
IINB
VCCVCO1
POONTX
100
VCCIQ
68
POONRX2
QIN IIN
QINB IINB
0 0 0 0
VCC
0 0 0 0
QOUT IOUT
QOUTB IOUTB
1000p
36
35
34
33
32
31
30
29
28
27
26
25
1000p
47
1000p
10k
10k
10k
10k
1000p
1000p
UHF LO
VCC INPUT(J10)
MIX2 OUTPUT
/PGA INPUT(J1)
1000p
MIX2O
CLK
SDATA
LE
IFINB
IFIN
GNDIF
VCCIF
IFVCOI
IFVCOO
BAND
IFLO
1000p
VCC
TOKO
617DB-1018
4
3
2
1
5
100
GNDIQ
TX_VCO1
OUTPUT
(J12)
MODLB
33p
IOUTB
TX VCO2
QOUTB
1p
QOUT
VCCMIX1
33p
GNDMIX1
24
23
22
21
20
19
18
17
16
15
14
13
390
1000p
IOUT
MURATA
MQE9P7-1747
Kv=47MHz/V
4
3
OUT VCC
5
2
GND GND
6 MOD CON 1
22k
HD155121F
100
ICURAD
MIX2OB
VCCDIV
10
68
33p
RFLOIN
100
1p
PLLOUT
VCCCOMP
VCOIN1
VCOIN2
GNDPLL
VCCPLL
RFIN2
RFIN1
0.5p
220n
(Q>40)
GNDDIV
VCCVCO2
33p
1000p
no fit
10p
RFOUT
MIX1IN1
MIX1INB1
POONRX1
TX_VCO2
OUTPUT
(J14)
VCCCOMP
1000p
no fit
1
2
3
4
5
6
7
8
9
10
11
12
1000p
MIX1OUTB
1p
2.7n
47p
10p
4.7n 2p
0.1µ
MIX1OUT
VCC
0 10p
10k
3.3n
no fit
10k
47p
6p
MIX1IN2
DCS LNA
RFIN(J9)
1p
2p
6.8n
Siemens: BFP420
0 22p
12n
MIX1 IF
OUTPUT(J6)
37
38
39
40
41
42
43
44
45
46
47
48
DCS LNA
RFOUT(J8)
GSM LNA
RFIN(J4)
10n
820
Siemens: BFP420
2p
2p
POONRX2
POONTX POONRX1
TOKO
617PT-1206
5
3
2
4
1
GSM LNA
RFOUT(J2)
GSM MIX1
RFIN(J3)
3p
DCS MIX1
RFIN(J7)
8p
100n
8p
no fit
15n
no fit
no fit
no fit
0
0
0
1000p
no fit no fit no fit no fit
4p
1000p
IOUT
IOUTB
QOUT
MIX2 IF
INPUT(J5)
BAND
VCC
VTUNE
VHS LO
IN/OUT(J11)
HD155121F
Test Circuit
HD155121F
Typical Performance
Power Supply Current Typical Performance
ICC [mA]
A
VCC = 3.0V
6 10 17 18 32 38 41 42 43
LNA bias current [mA]
= (Vb − Va) / 10Ω
no fit 10p
b
3
10
a
+ −
Rx
Tx
POONRX1 44
High
Low
POONRX2 45
High
Low
POONTX 46
Low
High
4
4.7k
for GSM
no fit
b
Active bias
circuit
10p
+ −
SDATA 27
a
Bit number 26
CLK 26
5
4.7k
TRS: Siemens
BFP420
High for PCN
Low for GSM
LE 28
10
for PCN
BAND 35
7 19 31 37 40
10p
Unit: R : Ω
C:F
Figure 3
Power supply current does not include the LNA bias current calculated by below formula.
Power supply current [mA] = ICC [mA] – LNA Bias current [mA]
23
HD155121F
Power Supply Current Typical Performance (cont)
Receive mode
Power supply current vs. VCC and Temperature
GSM mode, Gain1 (Normal gain), Bit No.26
Receive mode
Power supply current vs. VCC and Temperature
PCN mode, Gain1 (Normal gain), Bit No.26
70
70
65
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
Operating voltage range
Power supply current (mA)
Power supply current (mA)
Operating voltage range
60
55
50
45
40
2
2.5
3
3.5
4
VCC (V)
4.5
65
60
55
50
45
40
2
5
Transmit mode
Power supply current vs. VCC and Temperature
GSM mode
50
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
3.5
4
VCC (V)
Operating voltage range
Power supply current (mA)
Power supply current (mA)
3
4.5
5
55
Operating voltage range
24
2.5
Transmit mode
Power supply current vs. VCC and Temperature
PCN mode
55
45
40
35
30
25
2
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
2.5
3
3.5
4
VCC (V)
4.5
5
50
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
45
40
35
30
25
2
2.5
3
3.5
4
VCC (V)
4.5
5
HD155121F
LNA Bias Circuit Typical Performance
VCC = 3.0V
6 17 18 32 38 41 42 43
Bias current [mA]
= (Vb − Va) / 10Ω
no fit 10p
b
3
+ −
10
a
POONRX1 44
High
POONRX2 45
High
POONTX 46
Low
4
4.7k
for GSM
no fit
b
Active bias
circuit
10p
+ −
High for PCN
Low for GSM
LE 28
10
SDATA 27
a
4.7k
all bit = 0 (no care)
CLK 26
5
7 19 31 37 40
TRS: Siemens
BFP420
10p
Unit: R : Ω
C:F
Figure 4
Bias current vs. VCC and Temperature
6.4
Operating voltage range
Bias current (mA) @Ext. TRS
for PCN
BAND 35
6.2
6.0
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
5.8
5.6
5.4
5.2
5.0
2
2.5
3.5
3
VCC (V)
4
4.5
25
HD155121F
Mixer1 Typical Performance
TOKO 617PT-1206, insertion loss ≅ 2.2dB
800Ω : 50Ω
VCC = 3.0V
VCC = 3.0V
1000p
Input (GSM_RF)
940MHz: −30dBm
(50Ω)
2p
42
1
43
6p
1000p
Mixer1
220n
(Q>40)
Output (IF)
225MHz
(50Ω)
1000p
48
4.7n
1.5p
Input (Lo)
GSM: 1165MHz, −8dBm
PCN: 1617MHz, −8dBm
2
1000p
*2
0.5p
12n
2.5p
Input (PCN_RF)
1842MHz: −30dBm
(50Ω)
6 10 17 18 32 38 41 44 45
Mixer1 *1
BAND 35
47
GSM: "Low"
PCN: "High"
CLK 26
1000p 1000p
39
47
SDATA 27
LE 28
Gain1: X7 = 0 for High gain
Gain2: X7 = 1 for Low gain
other bit is no care
7 46 31 37 40
Unit: R : Ω
C:F
Note: 1. Mixer1 is open collector type.
2. Please tune this LC resonant circuit to get the maximum conversion gain at 225MHz.
Figure 5
Item
Mode
Min
Typ
Max
Unit
Test Condition
Note
Input (RF) Z
GSM
—
50
—
Ω
RF = 940MHz
1
PCN
—
50
—
Ω
RF = 1842MHz
Differential output load
between pin42 and pin43
—
—
800
—
Ω
IF = 225MHz
1
Output (IF) Z
—
—
50
—
Ω
IF = 225MHz
1
Input (LO) Z
—
—
50
—
Ω
LO = 1165, 1617MHz
1
Input (RF) VSWR
GSM
—
—
2
RF = 940MHz
1
PCN
—
—
2
RF = 1842MHz
GSM
—
—
2
LO = 1150 to 1185MHz
PCN
—
—
4
LO = 1580 to 1655MHz
Input (LO) VSWR
Note:
26
1. These values are not tested in mass production.
1
HD155121F
Mixer1 Typical Performance (cont)
• Mixer1 S parameters
Frequency
(MHz)
895
900
905
910
915
920
925
930
935
940
945
950
955
960
965
970
975
980
985
990
Port2: pin1 (MIX1INB1)
S11
S21
S12
S22
Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree)
754.62
−82.557
109.41
91.89
107.94
90.73
739.46
−79.502
752.44
−82.957
111.75
91.71
110.03
90.71
737.07
−79.884
752.00
−83.314
114.04
91.39
112.02
90.57
735.32
−80.164
750.32
−83.658
116.14
90.76
113.69
90.19
733.45
−80.543
749.06
−84.053
117.73
90.14
115.37
89.68
732.38
−80.877
748.42
−84.440
119.37
89.31
116.73
89.03
731.16
−81.223
748.51
−84.849
120.64
88.41
118.02
88.48
730.91
−81.544
747.39
−85.213
121.21
87.64
118.93
87.72
729.92
−81.910
747.02
−85.626
121.81
86.90
119.54
87.08
729.54
−82.283
747.44
−86.053
121.93
85.90
119.78
86.27
729.38
−82.668
747.37
−86.488
121.22
85.11
119.74
85.56
730.05
−83.100
747.45
−87.054
119.98
84.55
119.01
85.13
730.63
−83.532
747.73
−87.535
118.34
84.32
117.70
84.95
730.78
−84.137
746.74
−88.119
116.90
84.63
116.32
85.38
730.02
−84.752
745.30
−88.735
116.23
85.41
116.29
86.13
728.56
−85.411
743.28
−89.301
116.77
86.34
116.94
87.04
724.68
−86.052
740.18
−89.825
118.14
87.31
119.06
87.75
721.14
−86.574
737.01
−90.247
120.72
87.54
121.81
87.96
717.34
−86.974
734.02
−90.646
123.00
87.15
124.35
87.64
713.39
−87.278
732.70
−90.928
124.32
86.51
125.87
86.67
711.49
−87.564
• Mixer1 S parameters
Frequency
(MHz)
1795
1800
1805
1810
1815
1820
1825
1830
1835
1840
1845
1850
1855
1860
1865
1870
1875
1880
1885
1890
Port1: pin2 (MIX1IN1)
Port1: pin48 (MIX1IN2)
Port2: pin47 (MIX1INB2)
S11
S21
S12
S22
Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree)
522.87
−137.31
173.99
54.38
179.98
56.40
601.94
−158.40
523.98
−137.67
174.59
54.42
178.85
56.36
601.55
−158.76
525.39
−138.01
174.84
54.36
178.30
56.29
600.91
−159.11
526.77
−138.39
175.19
54.40
177.57
56.30
600.89
−159.53
527.49
−138.68
175.11
54.23
176.49
56.34
599.30
−159.93
528.26
−139.03
175.97
54.08
176.09
56.40
599.71
−160.34
529.92
−139.36
175.84
53.85
175.23
56.38
598.92
−160.88
531.15
−139.75
175.93
53.54
174.88
56.61
598.29
−161.22
532.28
−140.13
176.03
53.25
174.18
56.57
597.93
−161.63
533.43
−140.54
175.87
52.85
173.91
56.55
597.23
−162.11
534.27
−140.93
175.65
52.50
172.74
56.68
596.37
−162.53
535.62
−141.23
175.01
52.14
172.61
56.61
596.30
−163.01
536.47
−141.66
174.36
51.65
171.73
56.67
594.72
−163.49
537.71
−142.01
173.43
51.37
171.48
56.79
594.24
−163.88
538.84
−142.45
172.32
51.08
170.72
56.84
592.85
−164.40
539.18
−142.85
170.91
50.76
170.10
56.93
592.38
−164.88
540.41
−143.27
169.63
50.55
169.55
56.99
591.02
−165.30
541.22
−143.76
167.87
50.28
168.56
56.99
590.16
−165.77
541.78
−144.18
166.42
50.26
168.32
57.05
589.17
−166.18
542.05
−144.59
164.56
50.29
167.81
57.13
588.64
−166.65
27
HD155121F
Mixer1 Typical Performance (cont)
• Mixer1 S parameters
Frequency
(MHz)
200
205
210
215
220
225
230
235
240
245
250
255
260
265
270
275
280
285
290
295
28
Port2: pin43 (MIX1OUTB)
S11
S21
S12
S22
Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree)
979.93
−21.27
39.05
71.100
39.14
71.494
979.20
−21.64
979.30
−21.81
39.96
70.994
40.15
71.345
978.83
−22.17
978.24
−22.34
40.89
70.756
41.05
71.132
977.99
−22.73
977.43
−22.87
41.69
70.563
41.89
70.953
977.11
−23.29
976.58
−23.40
42.67
70.378
42.91
70.816
977.38
−23.85
976.18
−23.92
43.57
70.299
43.78
70.541
975.97
−24.42
975.31
−24.52
44.53
70.052
44.63
70.304
974.84
−25.00
975.16
−25.09
45.42
69.956
45.54
70.236
974.52
−25.58
974.11
−25.63
46.28
69.759
46.48
69.980
974.24
−26.15
973.55
−26.17
47.20
69.519
47.37
69.706
972.84
−26.77
972.26
−26.73
48.11
69.336
48.19
69.524
972.50
−27.34
972.06
−27.26
49.00
69.190
49.14
69.408
971.62
−27.92
970.73
−27.84
49.94
68.994
50.02
69.103
971.00
−28.50
970.76
−28.39
50.80
68.729
50.89
68.995
970.58
−29.05
970.42
−28.96
51.86
68.590
51.76
68.833
969.11
−29.65
969.30
−29.53
52.79
68.259
52.69
68.558
968.29
−30.23
968.44
−30.07
53.69
68.041
53.58
68.427
967.22
−30.82
967.83
−30.62
54.68
67.840
54.51
68.220
966.67
−31.40
967.14
−31.22
55.62
67.524
55.43
67.966
965.98
−32.00
966.09
−31.81
56.58
67.183
56.32
67.699
965.50
−32.63
• Mixer1 S parameters
Frequency
(MHz)
1120
1125
1130
1135
1140
1145
1150
1155
1160
1165
1170
1175
1180
1185
1190
1195
1200
1205
1210
1215
Port1: pin42 (MIX1OUT)
Port1: pin39 (RFLOIN)
S11
Frequency
Mag.(mU) Ang.(degree)
(MHz)
831.05
−71.478
1570
829.47
−71.805
1575
827.93
−72.134
1580
827.36
−72.485
1585
825.87
−72.816
1590
825.65
−73.101
1595
823.25
−73.414
1600
823.08
−73.701
1605
821.69
−74.035
1610
820.33
−74.371
1615
820.23
−74.659
1620
818.66
−75.064
1625
817.64
−75.335
1630
816.39
−75.674
1635
815.89
−76.100
1640
813.73
−76.425
1645
813.55
−76.784
1650
812.42
−77.127
1655
811.32
−77.471
1660
810.04
−77.885
1665
S11
Mag.(mU) Ang.(degree)
690.53
−101.924
689.12
−102.299
686.98
−102.703
685.49
−103.040
683.72
−103.392
682.04
−103.758
679.93
−104.098
677.68
−104.415
675.71
−104.781
674.24
−105.128
671.69
−105.454
669.77
−105.790
667.97
−106.114
664.89
−106.415
663.02
−106.713
661.31
−107.018
658.60
−107.243
656.49
−107.590
653.78
−107.769
651.73
−108.016
HD155121F
Mixer1 Typical Performance (cont)
14
Operating voltage range
12
11
10
9
8
0
−2
−3
−4
−6
15
4
−7
2
4.5
Conversion gain vs. VCC and Temperature
PCN mode. Gain1 (Normal gain)
14
Operating voltage range
13
12
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
11
10
9
8
3
4.5
4
4.5
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
−1
−2
−3
−4
−6
4
Operating voltage range
0
6
3
3.5
VCC (V)
3.5
3
VCC (V)
1
−5
2.5
2.5
Conversion gain vs. VCC and Temperature
PCN mode. Gain2 (Low gain)
2
7
5
2
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
−1
6
3.5
3
VCC (V)
Operating voltage range
1
−5
2.5
Conversion gain vs. VCC and Temperature
GSM mode. Gain2 (Low gain)
2
7
5
2
Conversion gain (dB)
3
Conversion gain (dB)
Conversion gain (dB)
13
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
Conversion gain (dB)
15
Conversion gain vs. VCC and Temperature
GSM mode. Gain1 (Normal gain)
−7
2
2.5
3.5
3
VCC (V)
4
4.5
29
HD155121F
Mixer1 Typical Performance (cont)
15
Noise figure(SSB) vs. VCC and Temperature
GSM mode. Gain1 (Normal gain)
14
Operating voltage range
13
11
10
9
15
14
12
6
11
3.5
3
VCC (V)
4
10
2
4.5
Noise figure(SSB) vs. VCC and Temperature
PCN mode. Gain1 (Normal gain)
14
Operating voltage range
13
11
10
9
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
14
6
11
4.5
4.5
15
12
4
4
16
7
3
3.5
VCC (V)
Operating voltage range
17
13
2.5
3.5
3
VCC (V)
18
8
5
2
2.5
Noise figure(SSB) vs. VCC and Temperature
PCN mode. Gain2 (Low gain)
19
NF SSB (dB)
12
20
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
16
7
15
NF SSB (dB)
17
13
2.5
Operating voltage range
18
8
5
2
30
19
NF SSB (dB)
NF SSB (dB)
12
20
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
Noise figure(SSB) vs. VCC and Temperature
GSM mode. Gain2 (Low gain)
10
2
2.5
3.5
3
VCC (V)
4
4.5
HD155121F
Mixer1 Typical Performance (cont)
Operating voltage range
−7
−8
−9
−10
−11
−12
−13
−14
−15
2
−10
1dB Input compression point (dBm)
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
2.5
3.5
3
VCC (V)
4
1dB Input compression point (dBm)
−6
0
1dB Input compression point vs.
VCC and Temperature
PCN mode. Gain1 (Normal gain)
−11
−12
−13
−14
−15
−16
−17
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
−18
−19
−20
2
2.5
3
3.5
VCC (V)
4
−1
4.5
Operating voltage range
−2
−3
−4
−5
−6
−7
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
−8
−9
−5
Operating voltage range
1dB Input compression point vs.
VCC and Temperature
GSM mode. Gain2 (Low gain)
−10
2
4.5
1dB Input compression point (dBm)
1dB Input compression point (dBm)
−5
1dB Input compression point vs.
VCC and Temperature
GSM mode. Gain1 (Normal gain)
2.5
3.5
3
VCC (V)
4
4.5
1dB Input compression point vs.
VCC and Temperature
PCN mode. Gain2 (Low gain)
−6
Operating voltage range
−7
−8
−9
−10
−11
−12
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
−13
−14
−15
2
2.5
3.5
3
VCC (V)
4
4.5
31
HD155121F
Mixer1 Typical Performance (cont)
14
13
12
11
10
9
8
32
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
7
6
5
2
15
Operating voltage range
2.5
3.5
3
VCC (V)
4
4.5
Delta (Gain1−Gain2) gain (dB)
Delta (Gain1−Gain2) gain (dB)
15
Delta (Gain1−Gain2) vs. VCC and Temperature
GSM mode.
Delta (Gain1−Gain2) vs. VCC and Temperature
PCN mode.
14
Operating voltage range
13
12
11
10
9
8
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
7
6
5
2
2.5
3.5
3
VCC (V)
4
4.5
HD155121F
Mixer2 Typical Performance
VCC = 3.0V
6 17 18 32 38 41 42 43
High
44 POONRX1
High
45 POONRX2
Low
50Ω
8p
Input (IF1)
225MHz
−50dBm
100n
8p
Input2 (IFLO) 50Ω 4p
540MHz
−10dBm
15n
46 POONTX
TOKO 617DB1018
(200Ω: 50Ω)
Test circuit insertion loss = 3.6dB
1000p 50ΩOutput (IF2)
25
45MHz
NC
24
1000p
300
IF Amp MIX2
30
300
29
BAND 35
PGA
÷2
36
LE 28
DEM SDATA 27
DIV
1000p
CLK 26
Low
X6 = 0 for High gain
X6 = 1 for Low gain
other bit is no care
7 19 31 37 40
Unit: R : Ω
C:F
Figure 6
Item
Min
Typ
Max
Unit
Test Condition
Note
Input (IF) Z
—
50
—
Ω
IF1 = 225MHz
1
LO Z
—
50
—
Ω
IFLO = 540MHz
1
i/p VSWR
—
—
2
IF1 = 225MHz
1
LO VSWR
—
—
2
IFLO = 540MHz
1
Note:
Mode
1. These values are not tested in mass production.
33
HD155121F
Mixer2 Typical Performance (cont)
• Mixer2 S parameters
Frequency
(MHz)
200
205
210
215
220
225
230
235
240
245
250
255
260
265
270
275
280
285
290
295
34
Port1: pin30 (IFIN)
Port2: pin29 (IFINB)
S11
S21
S12
S22
Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree) Mag.(mU) Ang.(degree)
941.92
−20.936
47.84
12.570
47.77
12.517
941.65
−20.558
940.46
−21.513
47.91
12.808
47.89
12.829
941.18
−21.073
940.85
−22.040
47.97
13.024
47.92
13.065
939.92
−21.628
940.32
−22.592
47.99
13.297
47.92
13.257
939.52
−22.145
938.32
−23.094
48.03
13.499
47.89
13.489
938.70
−22.689
938.11
−23.735
48.05
13.659
47.91
13.702
937.66
−23.198
936.93
−24.288
48.02
14.001
48.00
13.969
937.61
−23.777
936.23
−24.863
48.10
14.233
47.98
14.257
936.56
−24.355
935.61
−25.424
48.15
14.539
48.09
14.500
936.05
−24.928
934.29
−26.032
48.20
14.795
48.04
14.759
934.73
−25.481
933.31
−26.599
48.26
15.017
48.12
15.039
934.55
−26.039
933.20
−27.186
48.29
15.299
48.21
15.309
933.47
−26.606
932.03
−27.743
48.38
15.529
48.26
15.529
933.28
−27.110
931.63
−28.351
48.56
15.749
48.30
15.751
931.86
−27.702
930.97
−28.923
48.57
15.992
48.40
16.056
931.63
−28.224
929.68
−29.513
48.66
16.216
48.50
16.351
930.13
−28.763
928.75
−30.038
48.77
16.482
48.58
16.598
929.21
−29.315
927.72
−30.634
48.92
16.685
48.71
16.773
928.79
−29.899
927.06
−31.230
49.03
16.858
48.84
17.000
927.41
−30.498
925.35
−31.837
49.12
17.022
48.94
17.193
926.34
−31.043
HD155121F
Mixer2 Typical Performance (cont)
17
Conversion gain vs. VCC and Temperature
Gain1 (Normal gain)
1
Conversion gain vs. VCC and Temperature
Gain2 (Low gain)
Operating voltage range
16
0
15
−1
14
13
12
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
11
10
9
2
10
2.5
3.5
3
VCC (V)
4
Conversion gain (dB)
Conversion gain (dB)
Operating voltage range
−2
−3
−4
−5
−6
−7
2
4.5
Noise figure vs. VCC and Temperature
Gain1 (Normal gain)
16
8
14
Noise figure (dB)
Noise figure (dB)
15
7
6
5
2
2
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
2.5
3
3.5
VCC (V)
3.5
3
VCC (V)
4
4.5
Operating voltage range
9
3
2.5
Noise figure vs. VCC and Temperature
Gain2 (Low gain)
Operating voltage range
4
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
4
4.5
13
12
11
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
10
9
8
2
2.5
3.5
3
VCC (V)
4
4.5
35
HD155121F
Mixer2 Typical Performance (cont)
−5
Operating voltage range
−15
−20
−25
−30
2
18.0
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
2.5
3.5
3
VCC (V)
4
4.5
Delta(Gain1−Gain2) vs. VCC and Temperature
Delta(Gain1−Gain2) gain (dB)
Operating voltage range
17.5
17.0
16.5
16.0
15.5
14.5
14.0
2
36
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
15.0
2.5
3.5
3
VCC (V)
4
4.5
1dB Input compression point (dBm)
1dB Input compression point (dBm)
−10
1dB Input compression point vs.
VCC and Temperature
Gain1 (Normal gain)
1dB Input compression point vs.
VCC and Temperature
Gain2 (Low gain)
Operating voltage range
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
−10
−15
−20
−25
2
2.5
3
3.5
VCC (V)
4
4.5
HD155121F
PGA and Demodulator Typical Performance
Serial data
VCC = 3.0V
36
IFLO
MIX2
IF
DIV
POONRX1 44
POONRX2 45
23
300Ω
MIX2OB 300Ω
IOUTB
IQ
Demo.
22
10k
QOUT
Measurement
equipment
21
10k
QOUTB
BAND
TOKO
617DB-1018
Insertion loss = 3.6dB
PGA
IF
24
MIX2O
DIV
1000p
10k
IQ
25
RX mode
POONTX 46
IOUT
GMSK modulated wave
Carrier: 45MHz
1000p
0,90,180,270
degree
(45MHz)
IQ
OPLL
LE
DIV
4p
MODLB
15n
6 17 18 38 32
OPLL
fin: 540MHz
−10dBm
SDATA
CLK
26 27 28
20
10k
7 19 37 31 35
Unit: R : Ω
C:F
Figure 7
37
HD155121F
PGA and Demodulator Typical Performance (cont)
60
Power gain vs. VCC and Temperature
Power gain vs. Bit number with Temperature
VCC = 3V
60
0
−20
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
−40
−60
0
40
−20
−30
−40
−50
−60
10
20
30
Bit number
40
50
−20
Bit number 6
−40
Operating voltage range
50
−10
Bit number 26
0
−80
2
0
1dB Input compression point (dBm)
1dB Input compression point (dBm)
20
30
Bit number
20
−60
1dB Input compression point vs. Bit number
VCC = 3V, Ta = 25°C
−70
0
38
10
Power gain (dB)
Power gain (dB)
20
0
Bit number 46
40
40
2.5
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
3.5
3
VCC (V)
4
4.5
1dB Input compression point vs.
VCC and Temperature
Operating voltage range
−10
−20
−30
−40
Ta=−40°C
Ta=−25°C
Ta=27°C
Ta=85°C
Ta=100°C
−50
−60
−70
2
2.5
3.5
3
VCC (V)
4
4.5
HD155121F
PGA and Demodulator Typical Performance (cont)
Frequency response of LPF in Demodulator
20
sim.(typical)
sim.(worst)
Frequency (kHz) sim.(typ) sim.(worst)
Rejection (dB)
0
−20
−40
−60
−80
10
60
100
1000
10000
Frequency (kHz)
10
0.0
0.0
120
−1.2
−0.5
200
−4.0
−1.6
400
−14.0
−7.9
600
−22.3
−14.7
800
−29.2
−20.3
1600
−49.8
−37.6
3000
−47.3
−46.3
20000
−62.3
−58.7
100000
IQ offset voltage vs. VCC and Temperature
GSM mode
60
IQ offset voltage vs. VCC and Temperature
PCN mode
Operating voltage range
Operating voltage range
40
20
0
−20
I Ta=−40°C
I Ta=−25°C
I Ta=27°C
I Ta=85°C
I Ta=100°C
−40
−60
2
2.5
3
3.5
VCC (V)
Q Ta=−40°C
Q Ta=−25°C
Q Ta=27°C
Q Ta=85°C
Q Ta=100°C
4
4.5
IQ offset voltage (mV)
IQ offset voltage (mV)
40
20
0
−20
I Ta=−40°C
I Ta=−25°C
I Ta=27°C
I Ta=85°C
I Ta=100°C
−40
−60
2
2.5
3.5
3
VCC (V)
Q Ta=−40°C
Q Ta=−25°C
Q Ta=27°C
Q Ta=85°C
Q Ta=100°C
4
4.5
39
HD155121F
IQ Modulator and OffsetPLL Typical Performance
3V
36
16
IF
POONRX1 44
TX mode
POONRX2 45
0,90,180,270
POONTX 46
degree
(270MHz)
560p
PLLOUT
11
DIV
4p
I
IQ
OPLL
IFLO
DIV
6 17 18 38 32
MODLB
15n
10
COMP
fin: 540MHz
−10dBm
VCC = 3.0V
IIN
33 390
6800p
I
Ibar
IINB
15
Digital
I, Ibar,
modulation
Q, Qbar
signal Q generator Q
QIN
14
generator
IQ
Mod.
Offset
PLL
33p 68
VCOIN1
1p
TxVCO
MURATA
MQE9P7-897
33p
9
100
100
390
7 19 37 31
39
100
12
Spectrum
analyzer
1p
8
100 TxVCO
MURATA
MQE9P7-1747
33p
BAND
IF
DIV
IQ
OPLL
Differential encode: off
35
GSM "Low"
PCN "High"
22k
fin: 1167MHz
−8dBm
33p 68
VCOIN2
ICURAD
13
QINB
RFLOIN
Qbar
1000p 1000p
Detector mode:
positive peak
Unit: R : Ω
C:F
47
Figure 8
• Phase detector offset current ratio evaluation circuit
1000p 1000p
Signal generator
47
39
RFLOIN
GSM: VCOIN1 = 901MHz, −20dBm
PCN: VCOIN2 = 1746MHz, −20dBm
Signal generator
8 VCOIN2
GSM: 1172MHz, −8dBm
PCN: 1612MHz, −8dBm
IFLO: 540MHz, −10dBm
1000p
IFLO 36
1000p
Signal generator
47
9 VCOIN1
1000p
Oscillo scope
IIN 16
11 PLLOUT
47
2.5V
QIN 14
12 ICURAD
22k
Figure 9
40
IINB 15
QINB 13
1.5V
0.5V
1.5V
0.5V
Unit: R : Ω
C:F
HD155121F
IQ Modulator and OffsetPLL Typical Performance (cont)
100
Tx spectrum vs. Temperature
PCN mode (1747MHz)
Carrier suppression ratio
Carrier suppression ratio
Side-band suppression ratio
Side-band suppression ratio
80
Suppression ratio (dBc)
Suppression ratio (dBc)
100
Tx spectrum vs. Temperature
GSM mode (902MHz)
60
40
20
80
60
40
20
Operating voltage range
Operating voltage range
0
−60 −40 −20 0 20 40 60 80 100 120
Temperature (°C)
0
−60 −40 −20 0 20 40 60 80 100 120
Temperature (°C)
100
Tx spectrum vs. VCC
PCN mode (1747MHz)
Carrier suppression ratio
Carrier suppression ratio
Side-band suppression ratio
Side-band suppression ratio
80
Suppression ratio (dBc)
Suppression ratio (dBc)
100
Tx spectrum vs. VCC
GSM mode (902MHz)
60
40
20
80
60
40
20
Operating voltage range
0
2
2.5
3.5
3
VCC (V)
Operating voltage range
4
4.5
0
2
2.5
3.5
3
VCC (V)
4
4.5
41
HD155121F
IQ Modulator and OffsetPLL Typical Performance (cont)
10
Phase error vs. Temperature
GSM mode (902MHz)
10
Phase error vs. Temperature
PCN mode (1747MHz)
RMS
9
8
peak
8
Operating voltage range
Phase error (degree)
Phase error (degree)
RMS
9
peak
7
6
5
4
3
Operating voltage range
7
6
5
4
3
2
2
1
1
0
−60 −40 −20 0 20 40 60 80 100 120
Temperature (°C)
0
−60 −40 −20 0 20 40 60 80 100 120
Temperature (°C)
10
Phase error vs. VCC
GSM mode (902MHz)
10
Phase error vs. VCC
PCN mode (1747MHz)
RMS
9
7
6
5
4
3
5
4
3
1
1
3.5
3
VCC (V)
4
4.5
Operating voltage range
6
2
2.5
peak
7
2
0
2
42
8
Operating voltage range
Phase error (degree)
Phase error (degree)
8
RMS
9
peak
0
2
2.5
3.5
3
VCC (V)
4
4.5
HD155121F
IQ Modulator and OffsetPLL Typical Performance (cont)
200kHz offset
400kHz offset
600kHz to 1800kHz
1.8MHz to 3MHz
3MHz to 6MHz
6MHz upward offset
−20
−40
−60
−80
0
Suppression ratio (dB)
Suppression ratio (dB)
0
Modulation spectrum vs. Temperature
GSM mode (902MHz)
Modulation spectrum vs. Temperature
PCN mode (1747MHz)
200kHz offset
400kHz offset
600kHz to 1800kHz
1.8MHz to 3MHz
3MHz to 6MHz
6MHz upward offset
−20
−40
−60
−80
Operating voltage range
Operating voltage range
−100
−60 −40 −20 0 20 40 60 80 100 120
Temperature (°C)
Modulation spectrum vs. VCC
GSM mode (902MHz)
200kHz offset
400kHz offset
600kHz to 1800kHz
1.8MHz to 3MHz
3MHz to 6MHz
6MHz upward offset
−20
−40
−60
−80
0
Suppression ratio (dB)
Suppression ratio (dB)
0
−100
−60 −40 −20 0 20 40 60 80 100 120
Temperature (°C)
Modulation spectrum vs. VCC
PCN mode (1747MHz)
−20
−40
−60
−80
Operating voltage range
−100
2
2.5
3.5
3
VCC (V)
200kHz offset
400kHz offset
600kHz to 1800kHz
1.8MHz to 3MHz
3MHz to 6MHz
6MHz upward offset
Operating voltage range
4
4.5
−100
2
2.5
3.5
3
VCC (V)
4
4.5
43
HD155121F
IQ Modulator and OffsetPLL Typical Performance (cont)
100
Lock up time vs. Temperature
GSM mode (902MHz)
100
80
Lock up time (µsec)
80
Lock up time (µsec)
Lock up time vs. Temperature
PCN mode (1747MHz)
60
40
60
40
20
20
Operating voltage range
Operating voltage range
0
−60 −40 −20 0 20 40 60 80 100 120
Temperature (°C)
0
−60 −40 −20 0 20 40 60 80 100 120
Temperature (°C)
100
Lock up time vs. VCC
GSM mode (902MHz)
100
80
Lock up time (µsec)
Lock up time (µsec)
80
Lock up time vs. VCC
PCN mode (1747MHz)
60
40
20
60
40
20
Operating voltage range
0
2
44
2.5
3.5
3
VCC (V)
Operating voltage range
4
4.5
0
2
2.5
3.5
3
VCC (V)
4
4.5
HD155121F
IQ Modulator and OffsetPLL Typical Performance (cont)
• Modulation spectrum wave form vs. Temperature
GSM mode (880 MHz)
ATTEN 20dB VAVG 100
10dB/
RL 10.3dBm
ATTEN 20dB VAVG 100
10dB/
RL 10.7dBm
MKR 9.77dBm
880.000MHz
ATTEN 20dB VAVG 100
RL 10.2dBm
10dB/
MKR 10.20dBm
880.000MHz
Specification
Specification
Specification
D
D
D
R
R
R
CENTER 880.000MHz
*RBW 30kHz
VBW 30kHz
SPAN 1.000MHz
SWP 50.0ms
CENTER 880.000MHz
*RBW 30kHz
VBW 30kHz
Ta = −40°C
ATTEN 20dB VAVG 100
10dB/
RL 12.4dBm
SPAN 1.000MHz
SWP 50.0ms
ATTEN 20dB VAVG 100
RL 12.7dBm
10dB/
Specification
CENTER 880.00MHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
SPAN 1.000MHz
SWP 50.0ms
Ta = 100°C
ATTEN 20dB VAVG 100
RL 12.2dBm
10dB/
MKR 12.53dBm
880.00MHz
MKR 12.03dBm
880.00MHz
D
D
R
CENTER 880.000MHz
*RBW 30kHz
VBW 30kHz
Ta = 27°C
MKR 12.27dBm
880.00MHz
D
MKR 10.03dBm
880.000MHz
Specification
R
CENTER 880.00MHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
Specification
R
CENTER 880.00MHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
• Modulation spectrum wave form vs. Temperature
GSM mode (902 MHz)
ATTEN 20dB VAVG 100
10dB/
RL 10.0dBm
MKR 9.62dBm
902.000MHz
ATTEN 20dB VAVG 100
10dB/
RL 10.2dBm
MKR 10.50dBm
902.000MHz
Specification
ATTEN 20dB VAVG 100
RL 9.7dBm
10dB/
Specification
Specification
D
D
D
R
R
R
CENTER 902.000MHz
*RBW 30kHz
VBW 30kHz
SPAN 1.000MHz
SWP 50.0ms
CENTER 902.000MHz
*RBW 30kHz
VBW 30kHz
Ta = −40°C
ATTEN 20dB VAVG 100
RL 12.3dBm
10dB/
R
SPAN 1.000MHz
SWP 50.0ms
ATTEN 20dB VAVG 100
RL 12.7dBm
10dB/
CENTER 902.00MHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
R
SPAN 1.000MHz
SWP 50.0ms
Ta = 100°C
MKR 12.50dBm
902.00MHz
D
Specification
CENTER 902.000MHz
*RBW 30kHz
VBW 30kHz
Ta = 27°C
MKR 12.12dBm
902.00MHz
D
MKR 9.37dBm
902.000MHz
ATTEN 20dB VAVG 100
RL 11.8dBm
10dB/
MKR 12.00dBm
902.00MHz
D
Specification
CENTER 902.00MHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
R
Specification
CENTER 902.00MHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
45
HD155121F
IQ Modulator and OffsetPLL Typical Performance (cont)
• Modulation spectrum wave form vs. Temperature
GSM mode (915 MHz)
ATTEN 20dB VAVG 100
RL 9.9dBm
10dB/
MKR 9.61dBm
915.000MHz
ATTEN 20dB VAVG 100
RL 10.4dBm
10dB/
MKR 9.73dBm
915.000MHz
Specification
ATTEN 20dB VAVG 100
RL 9.5dBm
10dB/
Specification
Specification
D
D
D
R
R
R
CENTER 915.000MHz
*RBW 30kHz
VBW 30kHz
SPAN 1.000MHz
SWP 50.0ms
CENTER 915.000MHz
*RBW 30kHz
VBW 30kHz
Ta = −40°C
ATTEN 20dB VAVG 100
10dB/
RL 12.1dBm
R
ATTEN 20dB VAVG 100
10dB/
RL 12.4dBm
Specification
CENTER 915.000MHz
*RBW 30kHz
VBW 30kHz
R
SPAN 1.000MHz
SWP 50.0ms
Ta = 100°C
MKR 12.40dBm
915.00MHz
D
CENTER 915.00MHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
46
SPAN 1.000MHz
SWP 50.0ms
Ta = 27°C
MKR 12.28dBm
915.00MHz
D
MKR 9.67dBm
915.000MHz
ATTEN 20dB VAVG 100
10dB/
RL 11.8dBm
MKR 11.83dBm
915.00MHz
D
Specification
CENTER 915.00MHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
R
Specification
CENTER 915.00MHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
HD155121F
IQ Modulator and OffsetPLL Typical Performance (cont)
• Modulation spectrum wave form vs. Temperature
PCN mode (1710 MHz)
ATTEN 20dB VAVG 100
10dB/
RL 8.5dBm
MKR 8.36dBm
1.710000GHz
ATTEN 20dB VAVG 100
RL 9.2dBm
10dB/
MKR 8.90dBm
1.710000GHz
Specification
ATTEN 20dB VAVG 100
RL 9.4dBm
10dB/
Specification
Specification
D
D
D
R
R
R
CENTER 1.710000GHz
*RBW 30kHz
VBW 30kHz
SPAN 1.000MHz
SWP 50.0ms
CENTER 1.710000GHz
*RBW 30kHz
VBW 30kHz
Ta = −40°C
ATTEN 20dB VAVG 100
RL 10.9dBm
10dB/
SPAN 1.000MHz
SWP 50.0ms
ATTEN 20dB VAVG 100
RL 11.2dBm
10dB/
Specification
CENTER 1.71000GHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
SPAN 1.000MHz
SWP 50.0ms
Ta = 100°C
MKR 11.23dBm
1.71000GHz
ATTEN 20dB VAVG 100
RL 11.5dBm
10dB/
MKR 11.20dBm
1.71000GHz
D
D
R
CENTER 1.710000GHz
*RBW 30kHz
VBW 30kHz
Ta = 27°C
MKR 11.03dBm
1.71000GHz
D
MKR 9.23dBm
1.710000GHz
Specification
R
CENTER 1.71000GHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
Specification
R
CENTER 1.71000GHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
• Modulation spectrum wave form vs. Temperature
PCN mode (1747 MHz)
ATTEN 20dB VAVG 100
10dB/
RL 9.4dBm
ATTEN 20dB VAVG 100
RL 9.4dBm
10dB/
MKR 8.76dBm
1.747000GHz
ATTEN 20dB VAVG 100
RL 9.5dBm
10dB/
MKR 9.58dBm
1.747000GHz
Specification
Specification
Specification
D
D
D
R
R
R
CENTER 1.747000GHz
*RBW 30kHz
VBW 30kHz
SPAN 1.000MHz
SWP 50.0ms
CENTER 1.747000GHz
*RBW 30kHz
VBW 30kHz
Ta = −40°C
ATTEN 20dB VAVG 100
10dB/
RL 11.3dBm
R
SPAN 1.000MHz
SWP 50.0ms
ATTEN 20dB VAVG 100
10dB/
RL 11.6dBm
CENTER 1.74700GHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
R
SPAN 1.000MHz
SWP 50.0ms
Ta = 100°C
ATTEN 20dB VAVG 100
10dB/
RL 11.9dBm
MKR 11.58dBm
1.74700GHz
MKR 11.87dBm
1.74700GHz
D
D
Specification
CENTER 1.747000GHz
*RBW 30kHz
VBW 30kHz
Ta = 27°C
MKR 11.44dBm
1.74700GHz
D
MKR 9.17dBm
1.747000GHz
Specification
CENTER 1.74700GHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
R
Specification
CENTER 1.74700GHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
47
HD155121F
IQ Modulator and OffsetPLL Typical Performance (cont)
• Modulation spectrum wave form vs. Temperature
PCN mode (1785 MHz)
ATTEN 20dB VAVG 100
RL 8.8dBm
10dB/
MKR 8.44dBm
1.785000GHz
ATTEN 20dB VAVG 100
RL 8.7dBm
10dB/
MKR 8.91dBm
1.785000GHz
Specification
ATTEN 20dB VAVG 100
RL 9.4dBm
10dB/
Specification
Specification
D
D
D
R
R
R
CENTER 1.785000GHz
*RBW 30kHz
VBW 30kHz
SPAN 1.000MHz
SWP 50.0ms
CENTER 1.785000GHz
*RBW 30kHz
VBW 30kHz
Ta = −40°C
ATTEN 20dB VAVG 100
RL 11.3dBm
10dB/
R
ATTEN 20dB VAVG 100
10dB/
RL 11.4dBm
Specification
CENTER 1.785000GHz
*RBW 30kHz
VBW 30kHz
R
SPAN 1.000MHz
SWP 50.0ms
Ta = 100°C
MKR 11.41dBm
1.78500GHz
D
CENTER 1.78500GHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
48
SPAN 1.000MHz
SWP 50.0ms
Ta = 27°C
MKR 10.94dBm
1.78500GHz
D
MKR 9.57dBm
1.785000GHz
ATTEN 20dB VAVG 100
10dB/
RL 11.8dBm
MKR 11.66dBm
1.78500GHz
D
Specification
CENTER 1.78500GHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
R
Specification
CENTER 1.78500GHz
SPAN 20.00MHz
*RBW 100kHz
VBW 100kHz SWP 50.0ms
HD155121F
IQ Modulator and OffsetPLL Typical Performance (cont)
0
Tx spectrum vs. Common mode voltage
GSM mode (902MHz)
−30
−40
−50
−60
−70
−80
−90
−40
−50
−60
−70
−80
−90
0.50 0.75 1.00 1.25 1.50
Common mode voltage (V)
1.75
0
Carrier suppression ratio
−30
−40
−50
−60
−70
−80
−90
−100
0.40
0.60 0.80 1.00 1.20 1.40
Input swing level (Vpp) (single)
1.60
1.75
Carrier suppression ratio
Side-band suppression ratio
−20
−30
−40
−50
−60
−70
−80
−90
Operating range
0.50 0.75 1.00 1.25 1.50
Common mode voltage (V)
Tx spectrum vs. Input swing level
PCN mode (1747MHz)
−10
Side-band suppression ratio
−20
Operating range
−100
0.25
Tx spectrum vs. Input swing level
GSM mode (902MHz)
−10
Suppression level (dBc)
−30
Operating range
−100
0.25
Side-band suppression ratio
−20
Suppression level (dBc)
−20
Carrier suppression ratio
−10
Side-band suppression ratio
Suppression level (dBc)
Suppression level (dBc)
−10
0
0
Carrier suppression ratio
Tx spectrum vs. Common mode voltage
PCN mode (1747MHz)
−100
0.40
Operating range
0.60 0.80 1.00 1.20 1.40
Input swing level (Vpp) (single)
1.60
49
HD155121F
IQ Modulator and OffsetPLL Typical Performance (cont)
Phase comparator output current (I1, I3) vs.
VCC and Temperature
0.45
1.5
RICURAD = 22kΩ at pin12
I1
I1,I3 Ta=−40°C
I1,I3 Ta=−25°C
0.4
1.2
I3/I1
0.35
0.9
I3/I1 (mA)
I1 or I3 (mA)
I1,I3 Ta=27°C
I1,I3 Ta=85°C
I1,I3 Ta=100°C
I3/I1 Ta=−40°C
I3/I1 Ta=−25°C
I3/I1 Ta=27°C
0.3
0.6
I3/I1 Ta=85°C
I3/I1 Ta=100°C
I3
Operating voltage range
0.3
2
2.5
3
3.5
4
VCC (V)
0.25
5
4.5
OPLL phase detector output current value is controlled by RICURAD(pin12).
Following figure is for determining phase detector output current.
6
IPLLOUT (GSM)
IPLLOUT (PCN)
IPLLOUT(Pin11) (mA)
5
4
3
2
1
0
1
50
10
RICURAD(Pin12) (kΩ)
100
HD155121F
Package Dimensions
Preliminary
Unit: mm
24
48
13
12
0.75
0.10
*Dimension including the plating thickness
Base material dimension
M
1.40
1.70 Max
0.08
*0.17 ± 0.05
0.15 ± 0.04
1
*0.21 ± 0.05
0.19 ± 0.04
0.5
37
0.13 +0.09
−0.05
9.0 ± 0.2
9.0 ± 0.2
7.0
36
25
1.00
0.75
0° − 8°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-48C

Conforms
0.2 g
51
HD155121F
Appendix A
Transmitter Architecture (offset PLL architecture)
The HD155121F generates a modulated signal at IF with a quadrature modulator and converts it to a final
frequency with an Offset Phase Locked Loop (OPLL).
The Offset Phase Locked Loop is simply a PLL with a down conversion mixer in the feedback path.
Using a down converter in the feed back path acts as an up converter in the forward path, which allows the
output frequency to be different from the comparison frequency without affecting the normal operation of
the loop. Phase / frequency changes in the reference signal are not scaled, as they would be if a divider
were used in the feed back path, and hence the modulation is faithfully reproduced at the final frequency.
The main advantage of the OPLL in this application is that it forms a tracking band pass filter around the
modulated signal. This is because the loop cannot respond to phase variations at the reference that are
outside its closed loop bandwidth. Thus the broad band phase noise from the quadrature modulator is
shaped by the frequency response of the closed loop allowing the TX noise specifications to be met without
further filtering.
A secondary advantage of the OPLL is that the output signal, coming from a VCO, is truly constant
envelope. This removes the problem of spectral spreading caused by AM to AM and AM to PM
conversion in the power amplifier.
The OPLL is formed from an on-chip Gilbert cell down converter, limitters and phase detector with an offchip passive loop filter and VCO. The phase detector is implemented as a Gilbert cell with a current source
output stage, which allows an integrator to be included in the passive loop filter. This is similar to the
technique commonly used in PLL synthesizers.
As is well known, when out of lock, a mixer type phase detector does not provide any frequency
discrimination. This means that the under normal circumstances, a loop of this type is not guaranteed to
lock. However in the HD155121F, a well defined offset current is added to the phase detector output, so
that when the loop is out of lock, this offset current linearly charges the capacitors in the loop filter. This
has the effect of sweeping the VCO across the band. When the down converted signal from the VCO
approaches the reference frequency, the Gilbert cell begins to operate as a phase detector and the loop
acquires in the normal way. The presence of the offset current in lock is unimportant, as it only results in a
static phase offset between the final signal and the reference signal.
At the end of the transmit burst, when the transmitter is disabled, a switch closes to discharge the loop filter
capacitors. This resets the acquisition process in preparation for the start of the next burst.
The closed loop bandwidth of the OPLL should be designed to be around 1.2 to 1.5 MHz, which should be
large enough to allow rapid locking and accurate tracking of the modulation. If the bandwidth is too large,
the OPLL will not reject the noise from the modulator sufficiently. The ideal bandwidth will be a
compromise dependant on the noise performance of the VCO and amplifier chain.
52
HD155121F
R3
Phase detector
VCO
C2
C3
C1
R2
Figure A-1 Loop Filter Circuit of OPLL
The following equations provide a good starting point for the design of the OPLL.
Let:
f0 = Closed loop unity gain frequency (Hz) (Closed loop bandwidth)
fn = f0 / 2 = Closed loop resonant frequency (Hz)
ω n = 2π ⋅ fn
k v = VCO gain (Hz / V)
k vr = 2 ⋅ π ⋅ k v (rad / V sec)
k d = Peak phase dotector current = 1.2 (mA) in GSM mod e (at RICURAD = 22 kΩ)
k dr = Phase det ector gain = ( 2 ⋅ k d ) / π = 1.7 / π (mA / rad) (at RICURAD = 22 kΩ)
ξ = DampingFactor ≅ 0.9
Then:
C2 = k vr ⋅ k dr / ω n 2
R 2 = 2 ⋅ ξ ⋅ 1 /( k v ⋅ k d ⋅ C2) = (2 ⋅ ξ) /(ω n ⋅ C2)
C1 = C2 / 15
R3 ⋅ C3 ≅ 1 /(10 ⋅ ω n )
Note that many VCO modules have up to 100 pF capacitance on the control line. This can be very
significant when designing high bandwidth loops.
The phase detector peak output current is centered around 1.2 mA which is set by an 22 kΩ resistor
RICURAD on pin 12.
For example, the f0 = 1.2 MHz loop filter using the VCO of k v = 30 MHz / V (GSM) should be designed in
the following method.
Let:
f0 = 1.2 (MHz) = 1.2 × 10 6
(Hz)
fn = f0 / 2 = 600 ( kHz) = 6 × 10 5
ω n = 2 π ⋅ fn = 2 π ⋅ 6 × 10
5
(Hz)
( rad / sec)
k v = 30 (MHz / V) = 30 × 10 6
(Hz / V)
k vr = 2 π ⋅ k v = 2 π × 30 × 10 ( rad / V sec)
k d = 1.2 ( mA) (at RICURAD = 22 kΩ))
6
k dr = 1.7 / π ( mA / rad ) = 1.7 × 10 −3 ) / π ( A / rad ) (at RICURAD = 22 kΩ)
ξ = Damping Factor ≅ 0.9
53
HD155121F
Then:
2 × 30 × 10 6 × 1.7 × 10 −3
= 7.2 × 10 −9 = 7.2 nF
(2π × 6 × 10 5 )2
2 × 0.9
R2 = (2 ⋅ ξ) / (ω n ⋅ C2) =
= 66 Ω
2π × 6 × 10 5 × 7.2 × 10 −9
C1 = C2 / 15 = (7.2 × 10 −9 ) / 15 = 480 pF
1
R3 ⋅ C3 ≅ 1/(10 ⋅ ω n ) =
2π × 6 × 10 6
C2 = k vr ⋅ k dr / ω n 2 =
When the VCO modules have 33 pF capacitance on the control line, C3 is 33 pF.
C3 = 33 pF
R3 = 804 Ω
The result of the calculations for the PLL loop characteristic,based on the following block diagram (figure
A-2), is showed in figure A-3 and figure A-4. The offset PLL will be stable if the component values shown
are used.
VCO module
kvr/S
kdr
Input phase
R3
Phase
+ detector
−
VCO
Output phase
804
C2
7.2n
C1
480p
R2
66
C3
33p
Unit: R : Ω
C:F
kvr = 2π ⋅ kv = 2π × 30 × 106
kdr = (1.7 × 10−3) / π
(rad / Vsec)
(A / rad)
VCO module example
GSM: MURATA MQE9P7-897
C3 = 33pF
kv = 30MHz/V
PCN: MURATA MQE9P7-1747
C3 = 22pF
kv = 47MHz/V
Figure A-2 Block Diagram for OPLL Simulation
54
HD155121F
The open loop transfer function, Hol(S), of OPLL as shown in figure A-2 is given below.
Hol(S) =
k vr ⋅ k dr ⋅ (S + ω z )
k vr ⋅ k dr ⋅ (S + ω z )
=
C1⋅ C3 ⋅ R3 ⋅ S 2 ⋅ (S 2 + 2S ⋅ ω p + ω p 2 ) C1⋅ C3 ⋅ R3 ⋅ S 2 ⋅ (S + ω p1) (S + ω p 2 )
C1 + C2 + C3
C1⋅ C2 ⋅ C3 ⋅ R2 ⋅ R3
ω p { C2 ⋅ R2 (C1 + C3) + C3 ⋅ R3 (C1 + C2) }
ωp =
ς=
2 (C1 + C2 + C3)
1
ωz =
C2 ⋅ R 2
ω p1 = ω p (ς − ς 2 − 1)
ω p 2 = ω p (ς + ς 2 − 1)
Let:
C1 = 480 pF
C2 = 7.2 nF
C3 = 33 pF (VCO input capci tan ce on the control line)
R2 = 66 Ω
R3 = 804 Ω
Then:
ω p = 35.70 × 10 6 = 2π × 5.68 (MHz)
ς = 1.036
ω z = 2.104 × 10 6 = 2π × 335 (kHz)
ω p1 = 27.32 × 10 6 = 2π × 4.348 (MHz)
ω p 2 = 46.65 × 10 6 = 2π × 7.425 (MHz)
k vr = 2π × 30 × 10 6
k dr = (1.7 × 10 −3 ) / π
(rad / V sec)
(A / rad)
The magnitude, | Hol(jω) |, and the phase, Φ(jω), of Hol(S) are as shown in the following equations. When
the above constants from ωp to kdr are substituted in the equations, then | Hol(jω) | and Φ(jω) in figure A-3
can be obtained.
Hol( jω ) =
k vr ⋅ k dr ⋅ ω 2 + ω p12
C1⋅ C3 ⋅ R3 ⋅ ω 2 ⋅ ω 2 + ω p12 ⋅ ω 2 + ω p 2 2
Φ( jω ) = tan −1 (ω / ω z ) − tan −1 (ω / ω p1) − tan −1 (ω / ω p 2 ) − 180 (deg)
55
HD155121F
designed for 1.2MHz bandwidth loop filter
100
PCN
0
designed for 1.2MHz bandwidth loop filter
−130
GSM
Φ (jω)
| Hol (jω) |
50
−80
−50
GSM, PCN
−180
−230
−100
104
105
106
107
Frequency (Hz)
108
−280
104
105
106
107
Frequency (Hz)
108
Figure A-3 The Magnitude, | Hol(jω) |, and the Phase, Φ(jω),
of Open Loop Transfer Function Hol(jω)
Moreover, the closed loop transfer function, Hcl(jw) is the following equation, and the magnitude
characteristic, Hcl(jω), of he closed loop is shown is figure A-4.
Hcl( jω ) =
Hol( jω )
1 + Hol( jω )
20
designed for 1.2MHz bandwidth loop filter
GSM
0
PCN
| Hcl (jω) |
−20
−40
−60
−80
−100
104
105
106
107
Frequency (Hz)
108
Figure A-4 The Magnitude, | Hcl(jω) | of Closed Loop Transfer Function Hcl(jω)
56
HD155121F
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
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57