Aero I A E R O ™ I TR A N S C E I V E R FOR GSM AND GPRS WIRELESS COMMUNICATIONS Features Applications Multi-band GSM/GPRS digital cellular handsets Multi-band GSM/GPRS wireless data modems Description The Aero I transceiver is a complete RF front end for multi-band GSM and GPRS wireless communications. The transmit section interfaces between the baseband processor and the power amplifier. The receive section interfaces between the RF band-select SAW filters and the baseband processor. All sensitive components, such as RF/IF VCOs, loop filters, and tuning inductors, are completely integrated into a single compact package. DIAG2 DIAG1 RFOG RFOD 28 27 26 25 24 23 22 31 RXQN 1 21 RFIGN RXIP 2 20 RFIGP RXIN 3 19 RFIDN TXIP 4 18 RFIDP TXIN 5 17 RFIPN TXQP 6 16 RFIPP TXQN 7 15 GND 29 30 GND GND GND GND 8 9 10 11 12 13 14 SDI 32 SCLK GPRS Class 12 compliant 3-wire serial interface 2.7 V to 3.0 V operation SEN z Si4205-BM (For pin description see page 33) XEN z GSM 850 Class 4, small MS E-GSM 900 Class 4, small MS DCS 1800 Class 1 PCS 1900 Class 1 SDO z RXQP z PDN Quad-band support: XOUT XIN Single 8 x 8 mm package CMOS process technology Integrated GSM/GPRS transceiver including: z Low-IF receiver z Universal baseband interface z Offset-PLL transmitter z Dual RF synthesizer Integrated VCOs, frequency synthesizers, and tuning inductors VDD Pin Assignments (Top View) Ordering Information: See page 34. Patents pending Functional Block Diagram PGA ADC PGA ADC LNA PCS LNA 0 / 90 GSM DCS PCS DAC I PGA DAC Q XOUT 100 kHz I DET PA I Q PA RF PLL Rev. 1.0 12/03 PGA BASEBAND DCS ANTENNA SWITCH Si4205 LNA CHANNEL FILTER GSM IF PLL VC-TCXO 13 or 26 MHz XIN AFC Copyright © 2003 by Silicon Laboratories Aero I Aero I 2 Rev. 1.0 Aero I TA B L E O F C O N T E N TS Section Page Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 XOUT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin Descriptions: Si4205-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Package Outline: Si4205-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Rev. 1.0 3 Aero I Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature DC Supply Voltage Symbol Test Condition Min Typ Max Unit TA –20 25 85 °C VDD 2.7 2.85 3.0 V Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at 2.85 V and an operating temperature of 25 °C unless otherwise stated. Parameters are tested in production unless otherwise stated. Table 2. Absolute Maximum Ratings1,2 Parameter Symbol Value Unit VDD –0.5 to 3.3 V Input Current3 IIN ±10 mA Input Voltage3 VIN –0.3 to (VDD + 0.3) V Operating Temperature Range TOP –40 to 95 °C Storage Temperature Range TSTG –55 to 150 °C 10 dBm DC Supply Voltage RF Input Level4 Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The Si4205 device is high-performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For signals SCLK, SDI, SEN, PDN, XEN, and XIN. 4. At SAW filter output for all bands. 4 Rev. 1.0 Aero I Table 3. DC Characteristics (VDD = 2.7 to 3.0 V, TA = –20 to 85 °C) Parameter Supply Current 1 Symbol Test Condition Min Typ Max Unit IRX Receive mode — 80 111 mA ITX Transmit mode — 82 107 mA IXOUT PDN = 0, XEN = 1 — 1 2 mA IPDN PDN = 0, XEN = 0, XBUF = 0, XPD1 = 1 — 5 80 µA High Level Input Voltage2 VIH 0.7 VDD — — V Voltage2 VIL — — 0.3 VDD V High Level Input Current2 IIH VIH = VDD = 3.0 V –10 — 10 µA Low Level Input Current2 IIL VIL = 0 V, VDD = 3.0 V –10 — 10 µA High Level Output Voltage3 VOH IOH = –500 µA VDD–0.4 — — V 3 VOL IOL = 500 µA — — 0.4 V High Level Output Voltage4 VOH IOH = –10 mA VDD–0.4 — — V Low Level Output Voltage4 VOL IOL = 10 mA — — 0.4 V Low Level Input Low Level Output Voltage Notes: 1. Measured with load on XOUT pin of 10 pF and fREF = 13 MHz. Limits with XEN = 1 guaranteed by characterization. 2. For pins SCLK, SDI, SEN, XEN, and PDN. 3. For pins SDO, XOUT. 4. For pins DIAG1, DIAG2. Rev. 1.0 5 Aero I Table 4. AC Characteristics (VDD = 2.7 to 3.0 V, TA = –20 to 85 °C) Symbol Test Condition Min Typ Max Unit SCLK Cycle Time tCLK Figures 1, 3 35 — — ns SCLK Rise Time tR Figures 1, 3 — — 50 ns SCLK Fall Time tF Figures 1, 3 — — 50 ns SCLK High Time tHI Figures 1, 3 10 — — ns SCLK Low Time tLO Figures 1, 3 10 — — ns PDN Rise Time tPR Figure 2 — — 10 ns PDN Fall Time tPF Figure 2 — — 10 ns SDI Setup Time to SCLK↑ tSU Figure 3 15 — — ns SDI Hold Time from SCLK↑ tHOLD Figure 3 10 — — ns SEN↓ to SCLK↑ Delay Time tEN1 Figure 3 10 — — ns SCLK↑ to SEN↑ Delay Time tEN2 Figures 3, 4 12 — — ns SEN↑ to SCLK↑ Delay Time tEN3 Figures 3, 4 12 — — ns tW1, tW3 Figures 3, 4 10 — — ns DGAIN bits only 130 — — µs tW2 Option 2 only 10 — — ns tCA Figure 4 — — 27 ns — — 5 pF Parameter SEN Pulse Width1 SCLK↓ to SDO Time Digital Input Pin Capacitance2 XIN Input Resistance3 RXIN 10 15 20 kΩ XIN Input Capacitance3 CXIN 7 10 14 pF VREF 0.5 — — VPP XSEL = 0, DIV2 = 0 — 13 — MHz XSEL = 1, DIV2 = 1 — 26 — MHz XIN Input Sensitivity3 XIN Input Frequency3,4 fREF Notes: 1. Two programming options are allowed for SEN. Either option may be used. In both cases, the SEN pulse width must be at least 10 ns after writing all registers except after DGAIN is written. After DGAIN is written, SEN must be held high for at least 130 µs. See “AN50: Aero Transceiver Programming Guide.” 2. For pins SCLK, SDI, SEN, XEN, and PDN. 3. For XIN pin. 4. The XSEL and DIV2 bits control internal divide-by-two circuits and do not effect the XOUT pin. 6 Rev. 1.0 Aero I tR SCLK tF 80% 50% 20% tHI tCLK tLO Figure 1. SCLK Timing Diagram tPR tPF 80% PDN 20% Figure 2. PDN Timing Diagram 80% D17 SDI 50% D16 A0 D17 20% tSU tHOLD 80% SCLK 50% 20% tR tEN 1 80% SEN 50% (option 1) 20% tL O tH I tF tEN 2 tEN 3 tCLK tW 1 80% SEN 50% (option 2) 20% tW 2 tW 3 Figure 3. Serial Interface Write Timing Diagram 80% SDI 50% A0 20% 80% OD17 SDO 50% OD16 OD0 20% tCA 80% SCLK 50% 20% tEN2 tEN3 80% SEN 50% 20% tW1 Figure 4. Serial Interface Read Timing Diagram Rev. 1.0 7 Aero I Table 5. Receiver Characteristics (VDD = 2.7 to 3.0 V, TA = –20 to 85 °C) Parameter 1 GSM Input Frequency DCS or PCS Input Frequency Noise Figure at 25 Noise Figure at 85 °C 3 MHz Input Test Condition Min Typ Max Unit fIN GSM 850 band 869 — 894 MHz E-GSM 900 band 925 — 960 MHz DCS 1800 band 1805 — 1880 MHz PCS 1900 band 1930 — 1990 MHz GSM 850 band — 2.9 3.8 dB E-GSM 900 band — 3.0 3.9 dB DCS 1800 band — 3.3 4.1 dB PCS 1900 band — 3.7 4.5 dB GSM 850 band — 3.6 4.5 dB E-GSM 900 band — 3.7 4.6 dB DCS 1800 band — 4.2 5.0 dB PCS 1900 band — 4.9 5.7 dB GSM 850 band — 3.7 4.6 dB E-GSM 900 band — 3.8 4.7 dB DCS 1800 band — 4.6 5.4 dB PCS 1900 band — 5.2 6.0 dB GSM input –25 –21 — dBm DCS/PCS inputs –28 –25 — dBm GSM input –21 –16 — dBm DCS/PCS inputs –19 –15 — dBm 1 °C2,3 Noise Figure at 75 °C Symbol NF25 2,3 NF75 2,3 NF85 Desensitization2,3,4 20 MHz Input Desensitization 2,3,4 DES3 DES20 2 Input IP2 IP2 |f1,2 – f0| ≥ 6 MHz, |f2 – f1| = 100 kHz 29 40 — dBm Input IP32 IP3 |f2 – f1| ≥ 800 kHz, f0 = 2f1 – f2 –18 –12 — dBm Image Rejection2,4 IR GSM Input 28 35 — dB DCS/PCS Inputs 28 40 — dB GSM Input –28 –23 — dBm DCS/PCS inputs –27 –22 — dBm GSM Input –23 –18 — dBm DCS/PCS inputs –23 –18 — dBm GSM input 3 8.5 12.5 dB DCS/PCS inputs 10 15.5 19.5 dB GSM input 100 104 109 dB DCS/PCS inputs 96 102 107 dB GSM input — 17 — dB DCS/PCS inputs — 15 — dB GSM input 13 17 21 dB DCS/PCS inputs 4 8 12 dB 2,5 1 dB Input Compression 1 dB Input Compression2,6 Minimum Voltage Gain 2,6,7 Maximum Voltage Gain LNA Voltage 2,7 Gain3,8 LNA Gain Control Range 8 CPMAX CPMIN GMIN GMAX GLNA ∆GLNA Rev. 1.0 Aero I Table 5. Receiver Characteristics (Continued) (VDD = 2.7 to 3.0 V, TA = –20 to 85 °C) Parameter Symbol Analog PGA Control Range ∆GAPGA Test Condition Min Typ Max Unit 13 16 19 dB 3.2 4.0 4.8 dB — 63 — dB — 1 — dB DACFS[1:0] = 00 0.7 1.0 1.3 VPPD DACFS[1:0] = 01 1.5 2.0 2.5 VPPD DACFS[1:0] = 10 2.6 3.5 4.4 VPPD DACCM[1:0] = 00 0.8 1.0 1.2 V DACCM[1:0] = 01 1.05 1.25 1.45 V DACCM[1:0] = 10 1.15 1.35 1.55 V Differential Output Offset Voltage — — 16 mV Differential Output Offset Voltage Drift9,10,11 — — 5 mV Baseband Gain Error9,11 — — 1 % — — 1 deg Analog PGA Step Size ∆GDPGA Digital PGA Control Range Digital PGA Step Size Maximum Differential Output Voltage Output Common Mode Voltage 9 9 9,10,11 Baseband Phase Error 9,11 9 Output Load Resistance RL Single-ended 10 — — kΩ Output Load Capacitance9 CL Single-ended — — 10 pF CSEL = 0 — — 22 µs CSEL = 1 — — 16 µs CSEL = 0 — — 1.5 µs CSEL = 1 — — 1 µs From powerdown — 200 220 µs Group Delay12 Differential Group Delay12 3,13 Powerup Settling Time Notes: 1. GSM input pins RFIGP and RFIGN. DCS input pins RFIDP and RFIDN. PCS input pins RFIPP and RFIPN. 2. Measurement is performed with a 2:1 balun (50 Ω input, 200 Ω balanced output) and includes matching network and PCB losses. Measured at max gain (AGAIN[2:0] =100b, LNAG[1:0] = 01b, LNAC[1:0] = 01b) unless otherwise noted. Noise figure measurements are referred to 290 °K. Insertion loss of the balun is removed. 3. Specifications guaranteed by characterization using LQW15AN series matching inductors. 4. Input signal at balun is –102 dBm. SNR at baseband output is 9 dB. 5. AGAIN[2:0]=min=000b, LNAG[1:0] = max=01b, LNAC[1:0] =max= 01b. 6. AGAIN[2:0]=min=000b, LNAG[1:0] = min=00b, LNAC[1:0] = min=00b. 7. Voltage gain is defined as the differential rms voltage at the RXIP/RXIN pins or RXQP/RXQN pins divided by the rms voltage at the balun input with DACFS[1:0] = 01 and CSEL = 1. Gain is 1.5 dB higher with CSEL = 0. Minimum and maximum values do not include the variation in the DAC full scale voltage (also see Maximum Differential Output Voltage specification). 8. Voltage gain is defined as the differential rms voltage at the LNA output divided by the rms voltage at the balun output. 9. Output pins RXIP, RXIN, RXQP, RXQN. 10. Specified as root sum square: 2 2 . Drift specification applies to dc offset ( RXIP – RXIN ) + ( RXQP – RXQN ) calibration and is guaranteed by characterization. See ZERODEL[2:0] in the register description. 11. The baseband signal path is entirely digital. Gain, phase, and offset errors at the baseband outputs are because of the D/A converters. Offsets can be measured and calibrated out. See ZERODEL[2:0] in the register description. 12. Group delay is measured from antenna input to baseband outputs. Differential group delay is measured in-band. 13. Includes settling time of the frequency synthesizer. Settling to 5 degrees phase error measured at RXIP, RXIN, RXQP, and RXQN pins. Rev. 1.0 9 Aero I Receive Path Magnitude Response (CSEL = 0) Receive Path Magnitude Response (CSEL = 1) 0 0 −20 −20 Magnitude (dB) Magnitude (dB) −40 −60 −40 −80 −60 −100 −120 0 50 100 150 200 Frequency (KHz) 250 300 350 −80 400 0 50 100 150 200 Frequency (KHz) 250 300 350 400 Figure 5. Receive Path Magnitude Response (CSEL = 0 and CSEL = 1) Receive Path Passband Magnitude Response (CSEL = 1) 2 0 0 −2 −2 −4 −4 Magnitude (dB) Magnitude (dB) Receive Path Passband Magnitude Response (CSEL = 0) 2 −6 −8 −6 −8 −10 −10 −12 −12 −14 −14 −16 0 10 20 30 40 50 Frequency (KHz) 60 70 80 90 100 −16 0 10 20 30 40 50 Frequency (KHz) 60 70 80 90 100 90 100 Figure 6. Receive Path Passband Magnitude Response (CSEL = 0 and CSEL = 1) Receive Path Passband Group Delay (CSEL = 1) 20 24 19 23 18 22 17 21 16 Group Delay (uSec) Group Delay (uSec) Receive Path Passband Group Delay (CSEL = 0) 25 20 19 15 14 18 13 17 12 16 11 15 0 10 20 30 40 50 Frequency (KHz) 60 70 80 90 10 100 0 10 20 30 40 50 Frequency (KHz) 60 70 Figure 7. Receive Path Passband Group Delay (CSEL = 0 and CSEL = 1) 10 Rev. 1.0 80 Aero I Table 6. Transmitter Characteristics (VDD = 2.7 to 3.0 V, TA = –20 to 85 °C) Parameter Test Condition Min Typ Max Unit GSM 850 band 824 — 849 MHz E-GSM 900 band 880 — 915 MHz DCS 1800 band 1710 — 1785 MHz PCS 1900 band 1850 — 1910 MHz I/Q Differential Input Swing3,4 0.88 — 2.2 VPPD I/Q Input Common-Mode3 1.1 — 1.4 V BBG[1:0] = 11b 26 30 35 kΩ BBG[1:0] = 00b 22 25 29 kΩ BBG[1:0] = 01b 17 20 23 kΩ Powered down — Hi-Z — kΩ I/Q Input Capacitance3,5 — — 5 pF I/Q Input Bias Current3 13 16 19 µA RFOG Output Frequency1 RFOD Output Frequency2 I/Q Differential Input Resistance3,4 Symbol Sideband Suppression 67.7 kHz sinusoid — –46 –34 dBc Carrier Suppression 67.7 kHz sinusoid — –48 –33 dBc IM3 Suppression 67.7 kHz sinusoid — –57 –50 dBc — 1.9 3.0 o — 5 10 o Open loop — 100 — kHz/V VSWR 2:1, all phases, open loop — 200 — kHzPP 400 kHz offset — –65 –63 dBc 1.8 MHz offset — –70 –68 dBc 400 kHz offset — –65 –63 dBc 1.8 MHz offset — –70 –65 dBc 10 MHz offset — –160 –155 dBc/Hz 20 MHz offset — –166 –164 dBc/Hz 20 MHz offset — –163 –157 dBc/Hz RFOG Output Power Level1 ZL = 50 Ω 7 9 11 dBm RFOD Output Power Level2 ZL = 50 Ω 6 8 10 dBm Phase Error5 TXVCO Pushing1,2 TXVCO Pulling1,2 RFOG Output Modulation Spectrum1,6 RFOD Output Modulation Spectrum2,6 RFOG Output Phase Noise1,5,7 RFOD Output Phase Noise2,5,7 Rev. 1.0 rms PEAK 11 Aero I Table 6. Transmitter Characteristics (Continued) (VDD = 2.7 to 3.0 V, TA = –20 to 85 °C) Parameter RF Output Harmonic Suppression1,2 Powerup Settling Time5,8 Symbol Test Condition Min Typ Max Unit 2nd harmonic — — –20 dBc 3rd harmonic — — –10 dBc From powerdown — — 150 µs Notes: 1. Measured at RFOG pin. 2. Measured at RFOD pin. 3. Input pins TXIP, TXIN, TXQP, and TXQN. 4. Differential Input Swing is programmable with the BBG[1:0] bits in register 04h. Program these bits to the closest appropriate value. The I/Q Input Resistance scales inversely with the BBG[1:0] setting. 5. Specifications guaranteed by characterization. 6. Measured with pseudo-random pattern. Carrier power and noise power < 1.8 MHz measured with 30 kHz RBW. Noise power ≥ 1.8 MHz measured with 100 kHz RBW. 7. Measured with all 1s pattern. 8. Including settling time of the frequency synthesizer. Settling time measured at the RFOD and RFOG pins to 0.1 ppm frequency error. 12 Rev. 1.0 Aero I Table 7. Frequency Synthesizer Characteristics (VDD = 2.7 to 3.0 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit fRF1 GSM 850 band 1737.8 — 1787.8 MHz E-GSM 900 band 1849.8 — 1919.8 MHz DCS 1800 band 1804.9 — 1879.9 MHz PCS 1900 band 1929.9 — 1989.9 MHz GSM 850 band 1272 — 1297 MHz E-GSM 900 1279 — 1314 MHz DCS 1800 band 1327 — 1402 MHz PCS 1900 band 1423 — 1483 MHz GSM 850 band — 896 — MHz E-GSM 900 band 880–895 MHz 900–915 MHz — 798 — MHz E-GSM 900 band 895–900 MHz — 790 — MHz DCS 1800 band — 766 — MHz PCS 1900 band — 854 — MHz GSM input, RFUP = 0 — 200 — kHz DCS/PCS inputs, RFUP = 1 — 100 — kHz — 200 — kHz — 500 — kHz/V — 400 — kHz/V — 300 — kHz/V — 400 — kHzPP — 100 — kHzPP — 100 — kHzPP 3 MHz offset — –144 –138 dBc/Hz RF2 PLL Phase Noise2 400 kHz offset — –126 –121 dBc/Hz IF PLL Phase Noise2 400 kHz offset — –128 –123 dBc/Hz 3 MHz offset — –95 –83 dBc 400 kHz offset — –80 –75 dBc 400 kHz offset — –80 –70 dBc RF1 VCO Frequency1 RF2 VCO Frequency1 fRF2 IF VCO Frequency1 fIF RF1 PLL Phase Detector Update Frequency IF and RF2 PLL Phase Detector Update Frequency RF1 VCO Pushing2 RF2 VCO fφ Open Loop Pushing2 IF VCO Pushing 2 RF1 VCO Pulling2 VSWR = 2:1, all phases, open loop RF2 VCO Pulling2 IF VCO Pulling 2 RF1 PLL Phase Noise RF1 PLL Spurious RF2 PLL fφ 2 Spurious2 IF PLL Spurious2 2 Notes: 1. For the GSM input, the RF1 VCO is divided by two. During transmit, the IF VCO is divided by two. 2. Specifications are guaranteed by characterization. Rev. 1.0 13 Aero I Typical Application Schematic RFOG DIAG1 DIAG2 XEN XOUT RFOD C1 L1 32 1 2 3 4 5 6 7 RXQN RXIP RXIN TXIP TXIN TXQP TXQN RXQN RXIP RXIN TXIP TXIN TXQP TXQN GND U1 Si4205 GND 31 RFIGN RFIGP RFIDN RFIDP RFIPN RFIPP GND 21 20 19 18 17 16 15 GND 30 OUT+ IN OUT- GND GSM900 IN C2 C3 L2 Z2 OUT+ IN OUT- GND DCS 1800 IN C4 8 9 10 11 12 13 14 29 VDD XIN VDD PDNB SDO SENB SCLK SDI VDD C8 RXQP XOUT XEN DIAG2 DIAG1 RFOG RFOD 28 27 26 25 24 23 22 RXQP Z1 R1 XIN VDD C7 C5 L3 SDI SCLK SENB PDNB SDO Z3 OUT+ IN OUT- GND PCS 1900 IN C6 Notes: 1. Connect pads on bottom of U1 to GND. 2. See “AN92: Aero™ I/Aero™ I+ Transceiver PCB Layout Guidelines” for details on the following: z LNA matching network (C1–C6, L1–L3). Values should be custom tuned for a specific PCB layout and SAW filter to optimize performance. z Differential traces between the SAW filters (Z1–Z3) and transceiver (U1) pins 16–21. z Detailed SAW filter requirements. 3. For the XIN input, no external ac coupling is required. 4. For optimum performance, connect pin 31 to ground plane of power amplifier through several vias close to pin. 14 Rev. 1.0 Aero I Bill of Materials Component Value/Description Supplier(s) C1–C2 1.2 pF, ±0.1 pF, C0G (GSM 850 and E-GSM 900) Murata GRM36C0G series Venkel C0402C0G500 series C3–C4 1.2 pF, ±0.1 pF, C0G (DCS 1800) Murata GRM36C0G series Venkel C0402C0G500 series C5–C6 1.5 pF, ±0.1 pF, C0G (PCS 1900) Murata GRM36C0G series Venkel C0402C0G500 series C7 22 nF, ±20%, Z5U C8 10 pF, ±20%, C0G L1 24 nH, ±2% Murata LQG15HN series (0402 size) Murata LQW15AN series (0402 size) L2 6.8 nH, ±0.2 nH Murata LQG15HN series (0402 size) Murata LQW15AN series (0402 size) L3 5.6 nH, ±0.2 nH Murata LQG15HN series (0402 size) Murata LQW15AN series (0402 size) R1 100 Ω, ±5% U1 GSM/GPRS Transceiver Silicon Laboratories Si4205 Z1 GSM 850 RX SAW Filter (150 Ω balanced output) Epcos B39881-B9001-C710 (5-pin, 1.4 x 2.0 mm) Epcos B39881-B9004-E710 (6-pin, 1.6 x 2.0 mm) Murata SAFEK881MFL0T00R00 (6-pin, 1.6 x 2.0 mm) E-GSM 900 RX SAW Filter (150 Ω balanced output) Epcos B39941-B7820-C710 (5-pin, 1.4 x 2.0 mm) Epcos B39941-B9017-K310 (6-pin, 1.6 x 2.0 mm) Murata SAFEK942MFM0T00R00 (6-pin, 1.6 x 2.0 mm) Z2 DCS 1800 RX SAW Filter (150 Ω balanced output) Epcos B39182-B7821-C710 (5-pin, 1.4 x 2.0 mm) Epcos B39182-B9013-K310 (6-pin, 1.6 x 2.0 mm) Murata SAFEK1G84FA0T00R00 (6-pin, 1.6 x 2.0 mm) Z3 PCS 1900 RX SAW Filter (150 Ω balanced output) Epcos B39202-B7825-C710 (5-pin, 1.4 x 2.0 mm) Epcos B39202-B9020-K310 (6-pin, 1.6 x 2.0 mm) Murata SAFEK1G96FA0T00R00 (6-pin, 1.6 x 2.0 mm) Rev. 1.0 15 Aero I Functional Description PGA ADC PGA ADC LNA PCS LNA 0 / 90 GSM DCS PCS PGA DAC I PGA DAC Q XOUT 100 kHz I DET PA I PA BASEBAND DCS ANTENNA SWITCH Si4205 LNA CHANNEL FILTER GSM Q RF PLL IF PLL VC-TCXO 13 or 26 MHz XIN AFC Figure 8. Aero I Transceiver Block Diagram The Aero I transceiver is the industry’s most integrated RF front end for multi-band GSM/GPRS digital cellular handsets and wireless data modems. The highly integrated solution eliminates the IF SAW filter, external low noise amplifiers (LNAs) for three bands, transmit and RF voltage controlled oscillator (VCO) modules, and more than 70 other discrete components found in conventional designs. compatible with any supplier’s baseband subsystem. The high level of integration obtained through highperformance packaging and fine line CMOS process technology results in a solution with 50% less area and 80% fewer components than competing solutions. A triple-band GSM transceiver using the Aero I transceiver can be implemented with 15 components in less than 1.2 cm2 of board area. This level of integration is an enabling force in lowering the cost, simplifying the design and manufacturing, and shrinking the form factor in next-generation GSM/GPRS voice and data terminals. The unique integer-N PLL architecture produces a transient response that is superior in speed to fractional-N architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. This fast transient response makes the Aero I transceiver well suited to GPRS multi-slot applications where channel switching and settling times are critical. The receive section uses a digital low-IF architecture that avoids the difficulties associated with direct conversion while delivering lower solution cost and reduced complexity. The baseband interface is 16 The transmit section is a complete up-conversion path from the baseband subsystem to the power amplifier, and uses an offset phase-locked loop (PLL) with a fully integrated transmit VCO. The frequency synthesizer uses Silicon Laboratories’ proven technology, which includes integrated RF and IF VCOs, varactors, and loop filters. While conventional solutions use BiCMOS or other bipolar process technologies, the Aero I transceiver employs 100% CMOS process. This brings the dramatic cost savings and extensive manufacturing capacity of CMOS to the GSM market. Rev. 1.0 Aero I Receiver LNA DCS LNA PCS LNA RXBAND[1:0] 0/90 LNAC[1:0] LNAG[1:0] RF PLL PGA ADC PGA ADC AGAIN[2:0] 100 kHz CSEL PGA DAC I PGA DAC Q BASEBAND GSM CHANNEL FILTER Si4205 DGAIN[5:0] DACCM[1:0] DACFS[1:0] ZERODEL[2:0] NRF1[15:0] RFUP Figure 9. Receiver Block Diagram The Aero I transceiver uses a low-IF receiver architecture which allows for the on-chip integration of the channel selection filters, eliminating the external RF image reject filters and the IF SAW filter required in conventional superheterodyne architectures. Compared to a direct-conversion architecture, the low-IF architecture has a much greater degree of immunity to dc offsets, which can arise from RF local oscillator (RFLO) self-mixing, 2nd-order distortion of blockers, and device 1/f noise. This relaxes the common-mode balance requirements on the input SAW filters, and simplifies PC board design and manufacturing. Three differential-input LNAs are integrated. The GSM input supports the GSM 850 (869–894 MHz) or EGSM 900 (925–960 MHz) bands. The DCS input supports the DCS 1800 (1805–1880 MHz) band. The PCS input supports the PCS 1900 (1930–1990 MHz) band. For quad-band designs, SAW filters for the GSM 850 and E-GSM 900 bands should be connected to a balanced combiner which drives the GSM input for both bands. The LNA inputs are matched to the 150 Ω balancedoutput SAW filters through external LC matching networks. The LNA gain is controlled with the LNAG[1:0] and LNAC[1:0] bits in register 05h. A quadrature image-reject mixer downconverts the RF signal to a 100 kHz intermediate frequency (IF) with the RFLO from the frequency synthesizer. The RFLO frequency is between 1737.8 to 1989.9 MHz, and is internally divided by 2 for GSM 850 and E-GSM 900 modes. The mixer output is amplified with an analog programmable gain amplifier (PGA), which is controlled with the AGAIN[2:0] bits in register 05h. The quadrature IF signal is digitized with high resolution A/D converters (ADCs). The ADC output is downconverted to baseband with a digital 100 kHz quadrature LO signal. Digital decimation and IIR filters perform channel selection to remove blocking and reference interference signals. The response of the IIR filter is programmable to a high selectivity setting (CSEL = 0) or a low selectivity setting (CSEL = 1). The low selectivity filter has a flatter group delay response which may be desirable where the final channelization filter is in the baseband chip. After channel selection, the digital output is scaled with a digital PGA, which is controlled with the DGAIN[5:0] bits in register 05h. The LNAG[1:0], LNAC[1:0], AGAIN[2:0] and DGAIN[5:0] bits must be set to provide a constant amplitude signal to the baseband receive inputs. See “AN51: Aero Transceiver AGC Strategy” for more details. DACs drive a differential analog signal onto the RXIP, RXIN, RXQP, and RXQN pins to interface to standard analog-input baseband ICs. No special processing is required in the baseband for offset compensation or extended dynamic range. The receive and transmit baseband I/Q pins can be multiplexed together into a 4wire interface. The common mode level at the receive I and Q outputs is programmable with the DACCM[1:0] bits, and the full scale level is programmable with the DACFS[1:0] bits in register 12h. Rev. 1.0 17 Aero I Transmitter NIF[15:0] PDIB RF PLL IF PLL y2 REG GSM DCS/PCS PA PA FIF[3:0] RFOG BBG[1:0] SWAP TXIP I REG RFOD Si4205 TXIN I DET y1, 2 TXQP BASEBAND NRF2[15:0] PDRB Q TXBAND[1:0] TXQN Figure 10. Transmitter Block Diagram The transmit (TX) section consists of an I/Q baseband upconverter, an offset phase-locked loop (OPLL) and two output buffers that can drive external power amplifiers (PA), one for the GSM 850 (824 to 849 MHz) and E-GSM 900 (880 to 915 MHz) bands and one for the DCS 1800 (1710 to 1785 MHz) and PCS 1900 (1850 to 1910 MHz) bands. The OPLL requires no external duplexer to attenuate transmitter noise or spurious signals in the receive band, saving both cost and power. Additionally, the output of the transmit VCO (TXVCO) is a constant-envelope signal that reduces the problem of spectral spreading caused by non-linearity in the PA. low-side injection is used for the DCS 1800 and PCS 1900 bands. The I and Q signals are automatically swapped when switching bands. Therefore, there is no need for the customer to externally swap the I and Q signals. However, for additional layout flexibility, the SWAP bit in register 03h can be used to manually exchange the I and Q signals. Low-pass filters before the OPLL phase detector reduce the harmonic content of the quadrature modulator and feedback mixer outputs. The cutoff frequency of the filters is programmable with the FIF[3:0] bits in register 04h, and should be set to the recommended settings detailed in the register description. A quadrature mixer upconverts the differential in-phase (TXIP, TXIN) and quadrature (TXQP, TXQN) signals with the IFLO to generate a SSB IF signal that is filtered and used as the reference input to the OPLL. The IFLO frequency is generated between 766 and 896 MHz and internally divided by 2 to generate the quadrature LO signals for the quadrature modulator, resulting in an IF between 383 and 448 MHz. For the E-GSM 900 band, two different IFLO frequencies are required for spur management. Therefore, the IF PLL must be programmed per channel in the E-GSM 900 band. The IFLO frequencies are defined in Table 7 on page 13. The OPLL consists of a feedback mixer, a phase detector, a loop filter, and a fully integrated TXVCO. The TXVCO is centered between the DCS 1800 and PCS 1900 bands, and its output is divided by 2 for the GSM 850 and E-GSM 900 bands. The RFLO frequency is generated between 1272 and 1483 MHz. To allow a single VCO to be used for the RFLO, high-side injection is used for the GSM 850 and E-GSM 900 bands, and 18 Rev. 1.0 Aero I Frequency Synthesizer Si4205 XIN y1, 2 y65, y130 XOUT DIV2 RFUP XEN PDN Power Control SCLK Serial I/O RF2 Self Tune RF PLL PDIB PDRB SDI SDO RF1 I DET IF PLL Self Tune SDOSEL[4:0] SEN To RX/TX NRF1[15:0] NRF2[15:0] yN yN NIF[15:0] I DET To TX Figure 11. Frequency Synthesizer Block Diagram The Aero I transceiver integrates two complete PLLs including VCOs, varactors, resonators, loop filters, reference and VCO dividers, and phase detectors. The RF PLL uses two multiplexed VCOs. The RF1 VCO is used for receive mode, and the RF2 VCO is used for transmit mode. The IF PLL is used only during transmit mode. All VCO tuning inductors are also integrated. The IF and RF output frequencies are set by programming the N-Divider registers, NRF1, NRF2 and NIF. Programming the N-Divider register for either RF1 or RF2 automatically selects the proper VCO. The output frequency of each PLL is as follows: f OUT = N × f φ The DIV2 bit in register 31h controls a programmable divider at the XIN pin to allow either a 13 or 26 MHz reference frequency. For receive mode, the RF1 PLL phase detector update rate (fφ) should be programmed fφ = 100 kHz for DCS 1800 or PCS 1900 bands, and fφ = 200 kHz for GSM 850 and E-GSM 900 bands. For transmit mode, the RF2 and IF PLL phase detector update rates are always fφ =200 kHz. Rev. 1.0 19 Aero I Serial Interface XOUT Buffer A three-wire serial interface is provided to allow an external system controller to write the control registers for dividers, receive path gain, powerdown settings, and other controls. The serial control word is 24 bits in length, comprised of an 18-bit data field and a 6-bit address field as shown in Figure 12. The Aero I transceiver contains a reference clock buffer to drive the baseband input. The clock signal from the VC-TCXO is capacitively coupled to the XIN pin. The clock signal is not divided with the XSEL control. Last bit clocked in D D D D D D D D D D D D D D D D D D A A A A A A 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 Data Field Address Field Figure 12. Serial Interface Format The XOUT buffer is a CMOS driver stage with approximately 250 Ω of series resistance. This buffer is enabled when the XEN hardware control (pin 26 on the Si4205) is set high, independent of the PDN control pin. To achieve complete powerdown during sleep, the XEN pin must be set low, the XBUF bit in Register 12 must be set to zero, and the XPD1 bit in Register 11 must be set to one. During normal operation, these bits should be set to their default values. All registers must be written when the PDN pin is asserted (low), except for register 22h. All serial interface pins should be held at a constant level during receive and transmit bursts to minimize spurious emissions. This includes stopping the SCLK clock. A timing diagram for the serial interface is shown in Figure 3 on page 7. When the serial interface is enabled (i.e., when SEN is low), data and address bits on the SDI pin are clocked into an internal shift register on the rising edge of SCLK. Data in the shift register is then transferred on the rising edge of SEN into the internal data register addressed in the address field. The internal shift register ignores any leading bits before the 24 required bits. The serial interface is disabled when SEN is high. Optionally, registers can be read as illustrated in Figure 4 on page 7. The serial output data appears on the SDO pin after writing the revision register with the address to be read. Writing to any of the registers causes the function of SDO to revert to its previously programmed function. 20 Rev. 1.0 Aero I Control Registers Table 8. Register Summary Master Registers Bit Reg Name 01h Reset 0 0 0 0 0 0 0 02h Mode 0 0 0 0 0 0 03h Config 0 0 0 0 DIAG[1:0] 04h Transmit 0 0 0 0 0 05h Receive 0 0 0 0 11h Config 0 0 0 0 12h DAC Config 0 0 0 0 0 0 19h Reserved 0 0 0 0 0 0 20h RX Master #1 21h RX Master #2 0 22h RX Master #3 0 23h TX Master #1 24h TX Master #2 31h Config 0 0 0 32h Powerdown 0 0 0 33h RF1 N Divider 0 0 NRF1[15:0] 34h RF2 N Divider 0 0 NRF2[15:0] 35h IF N Divider 0 0 NIF[15:0] 3Ah Reserved 0 0 0 0 0 0 0 0 0 0 3Eh Reserved 0 0 0 0 0 0 0 0 0 3Fh Reserved 0 0 0 0 0 0 0 0 0 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 RESET 0 0 0 0 0 0 0 0 0 AUTO SWAP 0 0 0 0 0 1 0 0 1 BBG[1:0] 0 0 0 0 0 DPDS[2:0] RXBAND[1:0] FIF[3:0] DGAIN[5:0] 0 XPD1 1 XSEL 0 0 1 XBUF 0 ZDBS 0 0 0 0 0 RXBAND[1:0] AGAIN[2:0] 1 0 1 ZERODEL[2:0] 0 0 LNAC[1:0] LNAG[1:0] 0 0 0 DACCM[1:0] 0 0 0 CSEL DACFS[1:0] 0 0 NRF1[15:0] DPDS[2:0] 0 TXBAND[1:0] MODE[1:0] 0 0 LNAC[1:0] LNAG[1:0] 0 0 0 0 AGAIN[2:0] 0 TXBAND[1:0] 0 0 0 DGAIN[5:0] 0 DGAIN[5:0] NRF2[15:0] FIF[3:0] NIF[13:0] SDOSEL[3:0] 0 0 0 0 0 0 0 0 0 0 RFUP DIV2 0 0 1 0 0 0 0 0 0 0 0 0 PDIB PDRB 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 Notes: 1. Any register not listed here is reserved and should not be written. Writing to reserved registers may result in unpredictable behavior. 2. Master registers 20h to 24h simplify programming the Aero I to support initiation of receive (RX) and transmit (TX) operations with only two register writes. 3. See “AN50: Aero Transceiver Programming Guide” for detailed instructions on register programming. Rev. 1.0 21 Aero I Register 01h. Reset Bit D17 D16 D15 D14 D13 D12 D11 D10 Name 0 0 0 0 Bit Name 17:1 Reserved 0 RESET 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 RESET Function Program to zero. Chip Reset. 0 = Normal operation (default). 1 = Reset all registers to default values. Note: See “Control Registers” on page 21 for more details. This register must be written to 0 twice after a reset operation. This bit does not reset registers 31h to 35h. Register 02h. Mode Control Bit D17 D16 D15 D14 D13 D12 D11 D10 Name 0 0 0 0 Bit Name 17:3 Reserved 2 AUTO 1:0 MODE[1:0] 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 0 0 0 0 0 0 0 AUTO 0 D0 MODE[1:0] Function Program to zero. Automatic Mode Select. 0 = Manual. Mode is controlled by MODE[1:0] bits (default). 1 = Automatic. Last register write to NRF1 implies RX mode; Last register write to NRF2 implies TX mode. MODE[1:0] bits are ignored. Transmit/Receive/Cal Mode Select. 00 = Receive mode (default). 01 = Transmit mode. 10 = Calibration mode. 11 = Reserved. Note: These bits are valid only when AUTO = 0. Note: Calibration must be performed each time the power supply is applied. To initiate the calibration mode, set MODE[1:0] = 10 and pulse the PDN pin high for at least 150 µs. 22 D1 Rev. 1.0 Aero I Register 03h. Configuration Bit D17 D16 D15 D14 D13 D12 D11 D10 Name 0 0 0 0 DIAG[1:0] SWAP D9 D8 0 0 0 D7 D6 TXBAND[1:0] D5 D4 RXBAND[1:0] Bit Name 17:14 Reserved Program to zero. 13:12 DIAG[1:0] DIAG1/DIAG2 Output Select. DIAG1 DIAG2 00 = LOW LOW (default) 01 = LOW HIGH 10 = HIGH LOW 11 = HIGH HIGH D3 D2 D1 D0 0 0 1 0 Function Note: These pins can be used to control antenna switch functions. These bits must be programmed with the PDN pin is zero. The DIAG1/DIAG2 pins are held at the desired value regardless of the state of the PDN pin. 11 SWAP Transmit I/Q Swap. 0 = Normal (default). 1 = Swap I and Q for TXIP, TXIN, TXQP and TXQN pins. 10:8 Reserved 7:6 TXBAND[1:0] Transmit Band Select. 00 = GSM 850 or E-GSM 900 (default). 01 = DCS 1800. 10 = PCS 1900. 11 = Reserved. 5:4 RXBAND[1:0] Receive Band Select. 00 = GSM input (default). 01 = DCS input. 10 = PCS input. 11 = Reserved. 3:2 Reserved Program to zero. 1 Reserved Program to one. 0 Reserved Program to zero. Program to zero. Rev. 1.0 23 Aero I Register 04h. Transmit Control Bit D17 D16 D15 D14 D13 D12 D11 D10 Name 0 0 0 0 0 0 0 D9 1 D8 BBG[1:0] D7 D6 D5 FIF[3:0] D4 D3 D2 D1 D0 0 0 0 0 Bit Name Function 17:11 Reserved Program to zero. 10 Reserved Program to one. 9:8 BBG[1:0] TX Baseband Input Full Scale Differential Input Voltage. 10 = Reserved. 11 = 2.0 VPPD. 00 = 1.6 VPPD (default). 01 = 1.2 VPPD. Note: Refer to Table 6 for minimum and maximum values. Set this register to the nearest value. 7:4 FIF[3:0] TX IF Filter Cutoff Frequency. 0111 = Use for GSM 850, E-GSM 900 and PCS 1900 bands. 0110 = Use for DCS 1800 band. Note: Use the recommended setting for each band. Other settings reserved. 3:0 24 Reserved Program to zero. Rev. 1.0 Aero I Register 05h. Receive Gain Bit D17 D16 D15 D14 D13 D12 D11 D10 Name 0 0 0 0 Bit Name 17:14 Reserved 13:8 DGAIN[5:0] D9 D8 D7 DGAIN[5:0] 0 D6 D5 AGAIN[2:0] D4 D3 D2 LNAC[1:0] D1 D0 LNAG[1:0] Function Program to zero. Digital PGA Gain Control. 00h = 0 dB (default). 01h = 1 dB. ... 3Fh = 63 dB. Note: See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain registers. 7 Reserved 6:4 AGAIN[2:0] Program to zero. Analog PGA Gain Control. 000 = 0 dB (default). 001 = 4 dB. 010 = 8 dB. 011 = 12 dB. 100 = 16 dB. 101 = Reserved. 110 = Reserved. 111 = Reserved. Note: See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain registers. 3:2 LNAC[1:0] LNA Bias Current Control. 00 = Minimum current (default). 01 = Maximum current. 10 = Reserved. 11 = Reserved. Note: Program these bits to the same value as LNAG[1:0]. 1:0 LNAG[1:0] LNA Gain Control. 00 = Minimum gain (default). 01 = Maximum gain. 10 = Reserved. 11 = Reserved. Notes: 1. Program these bits to the same value as LNAC[1:0]. 2. See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain registers. Rev. 1.0 25 Aero I Register 11h. Configuration Bit D17 D16 D15 D14 D13 D12 D11 D10 Name 0 0 0 0 DPDS[2:0] D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 XSEL 0 1 0 1 0 0 0 CSEL XPD1 Bit Name Function 17:14 Reserved Program to zero. 13:11 DPDS[2:0] Data Path Delayed Start. 111= Use for GSM 850 and GSM 900 bands. 011= Use for DCS 1800 and PCS 1900 bands (default). Note: Use the recommended setting for each band. Other settings reserved. 10 XPD1 Reference Buffer Powerdown. 0 = Reference buffer automatically enabled (default). 1 = Reference buffer disabled. Note: This bit should be set to 0 during normal operation. To achieve lowest powerdown current (IPDN), this bit should be set to 1. The XBUF bit in Register 12h must also be set appropriately. 9 Reserved 8 XSEL Program to one. Reference Frequency Select. 0 = No divider. XIN = 13 MHz (default). 1 = Divide XIN by 2. XIN = 26 MHz. Note: The internal clock should always be 13 MHz. 26 7 Reserved Program to zero. 6 Reserved Program to one. 5 Reserved Program to zero. 4 Reserved Program to one. 3:1 Reserved Program to zero. 0 CSEL Digital IIR Coefficient Select. 0 = High selectivity filter (default). 1 = Low selectivity filter. Rev. 1.0 Aero I Register 12h. DAC Configuration Bit D17 D16 D15 D14 D13 D12 D11 D10 Name 0 0 0 0 0 0 0 1 D9 D8 D7 XBUF 0 ZDBS Bit Name 17:11 Reserved Program to zero. 10 Reserved Program to one. 9 XBUF D6 D5 D4 ZERODEL[2:0] D3 D2 DACCM[1:0] D1 D0 DACFS[1:0] Function Reference Buffer Power Control. 0 = Reference buffer disabled. 1 = Reference buffer automatically enabled (default). Note: This bit should be set to 1 during normal operation. To achieve the lowest powerdown current (IPDN), this bit should be set to 0. The XPD1 bit in Register 11h must also be set appropriately. 8 Reserved 7 ZDBS 6:4 ZERODEL[2:0] Program to zero. ZERODEL Band Select. 0 = Use ZERODEL[2:0] settings corresponding to DCS/PCS column (default). 1 = Use RXBAND[1:0] to determine ZERODEL[2:0] delay setting (GSM or DCS/PCS). RX Output Zero Delay. Code GSM 000: 90 µs 001: 110 µs 010: 130 µs 011: 140 µs 100: 150 µs 101: 160 µs 110: 180 µs 111: Reserved DCS/PCS 130 µs 150 µs 170 µs 180 µs 190 µs 200 µs 220 µs (default) Note: DAC input is forced to zero after PDN is deasserted. This feature can be used by the baseband processor to cancel the Si4205 DAC dc offset. Offsets induced on channels due to 13 MHz harmonics will not be included in the calibrated value. 3:2 DACCM[1:0] RX Output Common Mode Voltage. 00 = 1.0 V. 01 = 1.25 V (default). 10 = 1.35 V. 11 = Reserved. 1:0 DACFS[1:0] RX Output Differential Full Scale Voltage. 00 = 1.0 VPPD 01 = 2.0 VPPD (default). 10 = 3.5 VPPD 11 = Reserved. Rev. 1.0 27 Aero I Register 19h. Reserved Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 0 Bit Name 17:0 Reserved 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 D4 D3 D2 D1 D0 0 Function Program to zero. Register 20h. RX Master #1 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 Name RXBAND[1:0] D7 D6 D5 NRF1[15:0] Notes: 1. See registers 03h and 33h for bit definitions. 2. When this register is written, the PDIB bit will be automatically set to 0, the PDRB bit will be set to 1 and the RFUP bit is set as a function of RXBAND[1:0]. Register 21h. RX Master #2 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 LNAC[1:0] DPDS[2:0] D9 LNAG[1:0] D8 D7 AGAIN[2:0] D6 D5 D4 0 D3 D2 D1 D0 D1 D0 DGAIN[5:0] Note: See registers 05h and 11h for bit definitions. Register 22h. RX Master #3 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 0 0 0 0 0 D9 D8 D7 D6 0 0 0 0 Notes: 1. See register 05h for bit definitions. 2. The DGAIN[5:0] in register 22h can be changed without powering down. 28 Rev. 1.0 D5 D4 D3 D2 DGAIN[5:0] Aero I Register 23h. TX Master #1 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name TXBAND[1:0] D8 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 NRF2[15:0] Notes: 1. See registers 03h and 34h for bit definitions. 2. When this register is written, the PDIB bit is automatically set to 1, and the PDRB bit is set to 1. Register 24h. TX Master #2 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 NIF[13:0] FIF[3:0] Note: See registers 04h and 35h for bit definitions. Rev. 1.0 29 Aero I Register 31h. Main Configuration Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 Bit Name 17:15 Reserved 14:11 SDOSEL[3:0] SDOSEL[3:0] D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 RFUP DIV2 0 0 1 0 Function Program to zero. SDO Output Control Register. The mux_output table is as follows: 0000 Connected to the Output Shift Register (default). 0001 Force the Output to Low. 0010 Reference Clock. 0011 Lock Detect (LDETB) Signal from Phase Detectors. 1111 High Impedance. Notes: 1. SDO is high-impedance when PDN = 0. 2. SDO is Serial Data Output when in register read mode. 10:5 Reserved 4 RFUP Program to zero. RF PLL Update Rate (RF1 VCO only). 0 = 200 kHz update rate (Receive GSM modes). 1 = 100 kHz update rate (Receive DCS and PCS modes). Note: This bit is set to 1 when register 20h D[17:16] = 01b or 10b (DCS 1800 or PCS 1900 receive modes) and is set to 0 when D[17:16] = 00b or 11b (GSM 850 or GSM 900 modes). 30 3 DIV2 Input Clock Frequency. 0 = No divider. XIN = 13 MHz. 1 = Divide XIN by 2. XIN = 26 MHz. 2:1 Reserved Program to zero. 0 Reserved Program to one. Rev. 1.0 Aero I Register 32h. Powerdown Bit D17 D16 D15 D14 D13 D12 D11 D10 Name 0 0 0 0 Bit Name 17:2 Reserved 1 PDIB 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 PDIB PDRB 0 Function Program to zero. Powerdown IF PLL. 0 = IF synthesizer powered down. 1 = IF synthesizer powered up when the PDN pin is high. Notes: 1. The IF PLL is only used in transmit mode. Powerdown for receive mode. 2. This bit is set to 0 when register 20h is written (receive mode). 3. This bit is set to 1 when register 23h is written (transmit mode). 0 PDRB Powerdown RF PLL. 0 = RF synthesizer powered down. 1 = RF synthesizer powered up when the PDN pin is high. Notes: 1. This bit is set to 1 when register 20h is written (receive mode). 2. This bit is set to 1 when register 23h is written (transmit mode). Register 33h. RF1 N Divider Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0 NRF1[15:0] 0 Bit Name 17:16 Reserved Program to zero. Function 15:0 NRF1[15:0] N Divider for RF PLL (RF1 VCO). Used for receive mode. Register 34h. RF2 N Divider Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 D9 D8 D7 D6 NRF2[15:0] 0 Bit Name Function 17:16 Reserved Program to zero. 15:0 NRF2[15:0] N Divider for RF PLL (RF2 VCO). Used for transmit mode. Rev. 1.0 31 Aero I Register 35h. IF N Divider Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NIF[15:0] 0 Bit Name Function 17:16 Reserved Program to zero. 15:0 NIF[15:0] N Divider for IF Synthesizer. Used for transmit mode. Register 3Ah. Reserved Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 0 0 0 Bit 17:4 Name Reserved Program to zero. 3 Reserved Program to one. 2:1 Reserved Program to zero. 0 Reserved Program to one. 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 0 0 1 Function Register 3Eh. Reserved Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 0 0 0 Bit 17:4 Name Reserved Program to zero. 3:0 Reserved Program to one. 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 1 1 1 Function Register 3Fh. Reserved Bit Name 32 D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 0 0 0 Bit 17:5 Name Reserved Program to zero. 4 Reserved Program to one. 3:0 Reserved Program to zero. 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 0 0 Function Rev. 1.0 Aero I RXQN 1 RXIP 2 XO U T XE N DI A G 2 DI A G 1 R F OG RFOD 32 R XQ P Pin Descriptions: Si4205-BM 28 27 26 25 24 23 22 GND GND 31 21 RFIGN 20 RFIGP RFIDN RXIN 3 19 TXIP 4 18 RFIDP 17 RFIPN 16 RFIPP 15 GND 9 10 11 12 13 14 SDI 8 SEN 29 SC L K 7 GND SD O TXQN GND PD N 6 XI N 5 VD D TXIN TXQP 30 Pin Number(s) Name Description 1, 28 RXQN, RXQP Receive Q output (differential). 2, 3 RXIP, RXIN Receive I output (differential). 4, 5 TXIP, TXIN Transmit I input (differential). 6, 7 TXQP, TXQN Transmit Q input (differential). 8 XIN Reference frequency input from crystal oscillator. 9, 32 VDD Supply voltage. 10 PDN Powerdown input (active low). 11 SDO Serial data output. 12 SEN Serial enable input (active low). 13 SCLK Serial clock input. 14 SDI Serial data input. 15, 29–31 GND Ground. Connect to ground plane on PCB. 16, 17 RFIPP, RFIPN PCS LNA input (differential). Use for PCS 1900 band. 18, 19 RFIDP, RFIDN DCS LNA input (differential). Use for DCS 1800 band. 20, 21 RFIGP, RFIGN GSM LNA input (differential). Used for GSM 850 or E-GSM 900 bands. 22 RFOD DCS and PCS transmit output to power amplifier. Used for DCS 1800 and PCS 1900 bands. 23 RFOG GSM transmit output to power amplifier. Used for GSM 850 and E-GSM 900 bands. 24, 25 DIAG1, DIAG2 Diagnostic output. Can be used as digital outputs to control antenna switch functions. 26 XEN XOUT pin enable. 27 XOUT Clock output to baseband. Rev. 1.0 33 Aero I Ordering Guide Part Number Si4205-BM Description Operating Temperature Tri-band Transceiver GSM 850 or E-GSM 900, DCS 1800, PCS 1900 –20 to 85 °C Note: Add an “R” at the end of the part number to denote tape and reel option; 2500 quantity per reel. 34 Rev. 1.0 Aero I Package Outline: Si4205-BM Figure 13. 32-Pin Land Grid Array (LGA) Notes: 1. Dimensions in mm. 2. Approximate device weight is 196 mg. Rev. 1.0 35 Aero I Document Change List Revision 0.9 to Revision 1.0 This document corresponds to Aero I (Si4205), revision F. Table 3 on page 5 updated. z Table 4 on page 6 updated. z z z Added Note 1. Clarified register writes for DGAIN bits. Figure 3 on page 7 updated. z Added SEN programming option. Table 5 on page 8 updated. z Updated Supply Current specification for powerdown mode. Updated 20 MHz GSM band desensitization specification. Updated Voltage Gain specification. "Bill of Materials‚" on page 15 updated. "Ordering Guide‚" on page 34 updated. "Package Outline: Si4205-BM‚" on page 35 updated. z Added Note 1. Rev. 1.0 36 Aero I Notes: Rev. 1.0 37 Aero I Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, Texas 78735 Tel:1+ (512) 416-8500 Fax:1+ (512) 416-9669 Toll Free:1+ (877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holder. 38 Rev. 1.0