DAC5681Z www.ti.com SLLS865 – AUGUST 2007 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC) DESCRIPTION • • • • • • • • • 16-Bit Digital-to-Analog Converter (DAC) 1.0 GSPS Update Rate 16-Bit, 1.0 GSPS Input LVDS Data Bus – 8 Sample Input FIFO – On-Chip Delay Lock Loop High Performance – 73 dBc ACLR WCDMA TM1 at 180 MHz 2x-32x Clock Multiplying PLL/VCO 2x or 4x Interpolation Filters – Stopband Transition 0.4–0.6 Fdata – Filters configurable in either Low-Pass or High-Pass mode–allows selection or higher order image On-Chip 1.2-V Reference Differential Scalable Output: 2 to 20 mA Package: 64-Pin 9 × 9 mm QFN APPLICATIONS • • • • • Cellular Base Stations Broadband Wireless Access (BWA) WiMAX 802.16 Fixed Wireless Backhaul Cable Modem Termination System (CMTS) The DAC5681Z is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x/4x interpolation filters, on-board clock multiplier, and internal voltage reference. The DAC5681Z offers superior linearity and noise performance. The DAC5681Z integrates a wideband LVDS port with on-chip termination, providing full 1.0 GSPS data transfer into the DAC, or half-rate data and 1/4-rate input data can be interpolated by on-board 2x or 4x FIR filters. Each interpolation FIR is configurable in either Low-Pass or High-Pass mode, allowing selection of a higher order output sectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock. The current-steering architecture of the DAC5681Z consists of a segmented array of current sinking switches directing up to 20mA of full-scale current to complementary output nodes. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used. The DAC5681Z is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin QFN package. The device is pin upgradeable to the dual-channel DAC5682Z as well as the single-channel, non-interpolating DAC5681. ORDERING INFORMATION TA –40°C to 85°C (1) (2) (3) ORDER CODE DAC5681ZIRGCT DAC5681ZIRGCR PACKAGE DRAWING/TYPE (1) (2) (3) RGC / 64QFN Quad Flatpack No-Lead TRANSPORT MEDIA QUANTITY Small Tape and Reel 250 Large Tape and Reel 2000 Thermal Pad Size: 7,4 mm × 7,4 mm MSL Peak Temperature: Level-3-260C-168 HR For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2007, Texas Instruments Incorporated PRODUCT PREVIEW FEATURES 1 DAC5681Z www.ti.com SLLS865 – AUGUST 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. (3.3V) AVDD (1.8V) VFUSE (1.8V) DVDD LPF (1.8V) CLKVDD FUNCTIONAL BLOCK DIAGRAM PLL Bypass CLKIN Clock Multiplying PLL 2x-32x CLKINC DCLKP DAC Delay (0-3) IOUTA1 IOUTA2 13 Delay Value Offset CM2 Mode FIR2 Enable 100 2 16bit DAC 2 TXEnable=’1' SYNCN 47t 76dB HBF 2 SYNC=’0->1' (transition) SYNCP x2 LP/HP 47t 76dB HBF LP/HP 8 Sample FIFO DDR De-interleave PRODUCT PREVIEW 16 16 x2 4 (x1 Bypass) CM1 Mode 100 (x2 Bypass) 16 DAC_gain FIR2 FIR1 D15N 100 Mode Control B A D0N EXTIO EXTLO Sync Disable DLL Control D15P D0P PLL Enable FIR1 Enable DCLKN 1.2V Reference FDAC/2 FDAC/4 BIASJ PLL Control Delay Lock Loop (DLL) FDAC Clock Distribution Sync & Control SW_Sync 2 Submit Documentation Feedback GND (3.3V) IOVDD RESETB SCLK SDENB SDO SDIO FIFO Sync Disable Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): DAC5681Z DAC5681Z www.ti.com SLLS865 – AUGUST 2007 EXTLO BIASJ EXTIO AVDD AVDD IOUTA2 IOUTA1 AVDD DVDD RESETB 58 57 56 55 54 53 52 51 50 49 CLKVDD 1 48 SDENB CLKIN 2 47 SCLK CLKINC 3 46 SDIO GND 4 45 SDO SYNCP 5 44 VFUSE SYNCN 6 DAC5681Z 43 D0N RGC Package, QFN64 9x9 (Top View) 42 D0P 41 D1N Modified 11-Apr-07 40 D1P 39 DVDD 38 D2N D15P 7 D15N 8 IOVDD 9 DVDD 10 D14P 11 D14N 12 37 D2P D13P 13 36 D3N D13N 14 35 D3P D12P 15 34 D4N D12N 16 33 D4P 31 32 D5N 26 DCLKN D5P 25 DCLKP 30 24 D8N D6N 23 D8P 29 22 D9N D6P 21 D9P 28 20 D10N D7N 19 D10P 27 18 D11N D7P 17 D11P Pins different from DAC5682Z highlighted in Blue text. PRODUCT PREVIEW AVDD AVDD 61 AVDD AVDD 62 59 DVDD 63 60 LPF 64 DAC5681Z RGC PACKAGE (TOP VIEW) TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. AVDD 51, 54, 55, 59, 62 I Analog supply voltage. (3.3V) BIASJ 57 O Full-scale output current bias CLKIN 2 I Positive external clock input. With the clock multiplier PLL enabled, CLKIN provides lower frequency reference clock. If the PLL is disabled, CLKIN directly provides clock for DAC up to 1GHz. CLKINC 3 I Complementary external clock input. CLKVDD 1 I Internal clock buffer supply voltage. (1.8 V) D[15..0]P 7, 11, 13, 15, 17, 19, 21, 23, 27, 29, 31, 33, 35, 37, 40, 42 I LVDS positive input data bits 0 through 15. Each positive/negative LVDS pair has an internal 100 Ω termination resistor. Order of bus can be reversed via rev_bus bit in CONFIG5 register. Data format relative to DCLKP/N clock is Double Data Rate (DDR) with two data samples input be DLCKP/N clock cycle. In dual-channel mode, data for the A-channel is input while DCLKP is high. D15P is most significant data bit (MSB) – pin 7 D0P is least significant data bit (LSB) – pin 42 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): DAC5681Z 3 DAC5681Z www.ti.com SLLS865 – AUGUST 2007 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. D[15..0]N I/O DESCRIPTION 8, 12, 14, 16, 18, 20, 22, 24, 28, 30, 32, 34, 36, 38, 41, 43 I 25 I LVDS positive input clock. Unlike the other LVDS inputs, the DCLKP/N pair is self-biased and does not have an internal termination resistor in order to optimize operation of the DLL circuit. See the “DLL Operation” section. For proper external termination, connect a 100 Ω resistor across LVDS clock source lines followed by series 0.01 μF capacitors connected to each of DCLKP and DCLKN pins (see Figure 2). For best performance, the resistor and capacitors should be placed as close as possible to these pins. DCLKN 26 I LVDS negative input clock. (See the DCLKP description) DVDD 10, 39, 50, 63 I Digital supply voltage. (1.8 V) EXTIO 56 I/O Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD). Used as internal reference output when EXTLO = GND, requires a 0.1 μF decoupling capacitor to AGND when used as reference output. DCLKP EXTLO LVDS negative input data bits 0 through 15. (See D[15:0]P description above) D15N is most significant data bit (MSB) – pin 8 D0N is least significant data bit (LSB) – pin 43 PRODUCT PREVIEW 58 O Internal reference ground. Connect to AVDD to disable the internal reference. 4, Thermal Pad I Pin 4 and the Thermal Pad located on the bottom of the QFN package is ground for AVDD, DVDD and IOVDD supplies. IOUTA1 52 O A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin. In single DAC mode, outputs appear on the IOUTA1/A2 pair only. IOUTA2 53 O A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1 described above. An input data value of 0x0000 results in a 0mA sink and the most positive voltage on the IOUTA2 pin. IOUTB1 61 O B-Channel DAC current output. See the IOUTA1 description above. IOUTB2 60 O B-Channel DAC complementary current output. See the IOUTA2 description above. IOVDD 9 I Digital I/O supply voltage (3.3V) for pins RESETB, SCLK, SDENB, SDIO, SDO. LPF 64 I PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin may be left open. Set both PLL_bypass and PLL_sleep control bits for reduced power dissipation. RESETB 49 I Resets the chip when low. Internal pull-up. SCLK 47 I Serial interface clock. Internal pull-down. SDENB 48 I Active low serial data enable, always an input to the DAC5681Z. Internal pull-up. SDIO 46 I/O Serial interface data, bi-directional. Default setting sets SDIO as an input. Internal pull-down. SDO 45 O Serial interface data, uni-directional data output, if SDIO is an input. SDO is 3-stated when the 3 pin interface mode is selected (register 0x08 bit 1). Internal pull-down. SYNCP 5 I LVDS SYNC positive input data. The SYNCP/N LVDS pair has an internal 100 Ω termination resistor. By default, the SYNCP/N input must be logic ‘1’ to enable a DAC analog output. See the LVDS SYNCP/N Operation paragraph for a detailed description. SYNCN 6 I LVDS SYNC negative input data. VFUSE 44 I Digital supply voltage. (1.8V) Connect to DVDD pins for normal operation. This supply pin is also used for factory fuse programming. GND DAC5682Z Data Sheet Reference Prior to market release, please refer to the DAC5682Z (dual channel) data sheet SLLS853 for relevant single-channel functional descriptions and performance characteristics on the DAC5681Z device. 4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): DAC5681Z IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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