CDCS501 www.ti.com..................................................................................................................................................................................................... SCAS874 – APRIL 2009 SSC Clock Generator/Buffer FEATURES APPLICATIONS • • 1 • • • • • • • Part of a Family of Easy to use Clock Generator Devices With Optional SSC SSC Capable Clock Generator / Buffer SSC Controllable via 3 External Pins – ±0% to ±1.5% Center Spread 1 External Control Pin for SSC ON / OFF Selection 40 MHz to 108 MHz Single-Ended LVCMOS Input Single 3.3V Device Power Supply Wide Temperature Range – 40°C to 85°C Low Space Consumption by 8 Pin TSSOP Package Consumer and Industrial Applications Requiring EMI Reduction through Spread Spectrum Clocking PACKAGE IN SSC_SEL 0 SSC_SEL 1 GND 1 2 3 4 CDCS501 8 7 6 5 VDD SSC_SEL 2 OUT SSC_ON BLOCK DIAGRAM V DD IN SSC_SEL 0 SSC_SEL 1 SSC_SEL 2 LVCMOS GND SSC Generator LV CMOS OUT SPREAD LOOK-UP TABLE SSC_ON DESCRIPTION The CDCS501 is a spread spectrum capable, LVCMOS Input Clock Buffer for EMI reduction. The device is designed to counter common EMI problems in modern electronic designs. It accepts a 3.3V LVCMOS signal at the input and spread this signal by a small amount, centered around the input frequency. The amount of spread can be selected via 3 control pins. The Functional Table contains detailed information on the amount of spread. A 4th control pin can be used to activate or deactivate the Spread Spectrum Clock Generator. Selecting SSC_ON = off will turn the Spread Spectrum Clock Generator off only. The device will still pass the LVCMOS signal that’s presented at its input trough to its output. This pin is low active. The wide operating frequency range covers most commonly used midrange Audio and Video frequencies. The CDCS501 operates in 3.3V environment. It is characterized for operation from –40°C to 85°C, and available in an 8-pin TSSOP package. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated CDCS501 SCAS874 – APRIL 2009..................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTION TABLE SSC_ON SSC_SEL 0 SSC_SEL 1 SSC_SEL 2 SPREAD AMOUNT 1 x x X 0.00% 0 0 0 0 1.00% 0 0 0 1 1.50% 0 0 1 0 1.00% 0 0 1 1 1.50% 0 1 0 0 0.50% 0 1 0 1 0.75% 0 1 1 0 0.00% 0 1 1 1 0.50% DEVICE INFORMATION PACKAGE IN SSC_SEL 0 SSC_SEL 1 GND 1 2 3 4 8 7 6 5 CDCS501 VDD SSC_SEL 2 OUT SSC_ON PIN FUNCTIONS PIN NAME IN OUT NO. Type 1 I Description LVCMOS Clock Input 6 O LVCMOS Clock Output 2, 3, 7 I Spread Selection Pins, internal Pull-up SSC_ON 5 I SSC on/off Pin, active low; internal Pull-down VDD 8 Power 3.3V Power Supply GND 4 Ground Ground SSC_SEL 0, 1, 2 PACKAGE THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE (1) THERMAL AIRFLOW (CFM) CDCS501PW 8-PIN TSSOP RθJA RθJc (1) 2 0 150 250 500 High K 149 142 138 132 Low K 230 185 170 150 High K 65 Low K 69 UNIT °C / W °C / W The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCS501 CDCS501 www.ti.com..................................................................................................................................................................................................... SCAS874 – APRIL 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT VDD Supply voltage range –0.5 to 4.6 V VIN Input voltage range –0.5 to 4.6 V Vout Output voltage range –0.5 to 4.6 V IIN Input current (VI < 0, VI > VDD) 20 mA Iout Continuous output current 50 mA TST Storage temperature range –65 to 150 °C TJ Maximum junction temperature 125 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VDD Supply voltage 3.0 3.6 V fIN Input Frequency 40 108 MHz VIL Low level input voltage LVCMOS VIH High level input voltage LVCMOS VI Input Voltage threshold LVCMOS CL Output Load Test LVCMOS 15 pF IOH/IOL Output Current 12 mA TA Operating free-air temperature 85 °C 0.3 VDD 0.7 VDD V 0.5 VDD –40 V Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCS501 V 3 CDCS501 SCAS874 – APRIL 2009..................................................................................................................................................................................................... www.ti.com DEVICE CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IDD Device supply current fOUT Output frequency IIH LVCMOS input current IIL LVCMOS input current VOH VOL TEST CONDITIONS MIN MAX UNIT 108 MHz VI = VDD; VDD = 3.6V 10 µA VI = 0 V; VDD = 3.6V –10 µA fIN = 80 MHz TYP 26 40 LVCMOS high-level output voltage LVCMOS low-level output voltage IOH = –0.1mA 2.9 IOH = –8mA 2.4 IOH = –12mA 2.2 mA V IOL = 0.1mA 0.1 IOL = 8mA 0.5 IOL = 12mA 0.8 V tJIT(C-C) Cycle to cycle jitter cycles fout = 80 MHz; SSC = 1%, 10000 cycles 110 ps tr/tf Rise and fall time 20%–80% 0.75 ns Odc Output duty cycle fMOD Modulation frequency 45% 55% 30 kHz 40 VDD = 3.3 V IDD - Supply Current - mA 35 30 25 20 15 10 20 30 40 50 60 70 80 90 100 110 120 f - Frequency - MHz Figure 1. IDD vs. Input Frequency, VDD = 3.3V 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCS501 CDCS501 www.ti.com..................................................................................................................................................................................................... SCAS874 – APRIL 2009 APPLICATION INFORMATION SSC MODULATION The exact implementation of the SSC modulation plays a vital role for the EMI reduction. The CDCS501 uses a triangular modulation scheme implemented in a way that the modulation frequency depends on the VCO frequency of the internal PLL and the spread amount is independent from the VCO frequency. The modulation frequency can be calculated by using the below formula. fmod = fIN / 2480 PARAMETER MEASUREMENT INFORMATION VDD CDCS501 1 kW LVCMOS 1 kW 10 pF Figure 2. Test Load CDCS501 LVCMOS LVCMOS Typical Driver Impedance ~32 W Series Termination ~18 W ZL = 50 W Figure 3. Test Load for 50-Ω Board Enviroment Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCS501 5 PACKAGE OPTION ADDENDUM www.ti.com 1-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CDCS501PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCS501PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 9-May-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDCS501PWR Package Package Pins Type Drawing TSSOP PW 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 7.0 3.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 9-May-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCS501PWR TSSOP PW 8 2000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. 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