SONY CXP81840A

CXP81840A/81848A
CMOS 8-bit Single Chip Microcomputer
Description
The CXP81840A/81848A is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, 32kHz
timer/event counter, remote control receiving circuit,
as well as basic configurations like 8-bit CPU, ROM,
RAM and I/O port. They are integrated into a single
chip.
Also CXP81840A/81848A provides sleep/stop
function which enables to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.
100 pin QFP (PIastic)
100 pin LQFP (PIastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction
• Minimum instruction cycle
During operation 333ns/12MHz (Supply voltage 3.0 to 5.5V)
During operation 250ns/16MHz (Supply voltage 4.5 to 5.5V)
During operation 122µs/32kHz
• Incorporated ROM capacity
40K bytes (CXP81840A)
48K bytes (CXP81848A)
• Incorporated RAM capacity
1344bytes
• Peripheral functions
— A/D converter
8-bit, 12-channel, successive approximation system
(Conversion time 20.0µs/16MHz)
— Serial interface
Incorporated 8-bit and 8-stage FIFO, 1-channel
(1 to 8 bytes auto transfer)
8-bit serial I/O, 1-channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer
32kHz timer/counter
— High precision timing pattern generator PPG 19 pins 32-stage programmable
RTG 5-pins 2-channel
— PWM/DA gate output
12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— PWM output
14-bit, 1-channel
— Remote control receiving circuit
8-bit pulse measuring counter, 6-stage FIFO
• Interruption
20 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP/LQFP
• Piggyback/evaluation chip
CXP81800 100-pin ceramic QFP/LQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94Z12-ST
AVDD
PI3/ADJ
FIFO
12 BIT PWM GENERATOR CH1
12 BIT PWM GENERATOR CH0
14 BIT PWM GENERATOR
PI2/PWM
PE2/PWM0
PE4/DAA0
PE6/DAB0
PE3/PWM1
PE5/DAA1
PE7/DAB1
REMOCON INPUT
PI1/RMC
PG6/EXI0
PG7/EXI1
8 BIT TIMER 1
PE1/EC
PI3/TO
8 BIT TIMER/COUNTER 0
FIFO
SERIAL INTERFACE UNIT
(CH1)
SERIAL
INTERFACE UNIT
(CH0)
2
4
2
2
2
PE0/INT0
NMI
PE1/INT2
PI4/INT1/NMI
CH0
CH1
REALTIME
PULSE
GENERATOR
5
RAM
PROGRAMMABLE
PATTERN
GENERATOR
2
32kHz
TIMER/COUNTER
PRESCALER/
TIME BASE TIMER
RAM
1344 BYTES
CLOCK
GENERATOR/
SYSTEM CONTROL
AAA
19
FIFO
PROM
40K/48K BYTES
SPC700
CPU CORE
FRC
CAPTURE UNIT
INTERRUPT CONTROLLER
AVREF
A/D CONVERTER
AVss
PI7/SI1
PI6/SO1
PI5/SCK1
CS0
SI0
SO0
SCK0
12
PA0/PPO0
to
PC2/PPO18
AN0 to AN3
PF0/AN4
to
PF7/AN11
TEX
TX
EXTAL
XTAL
RST
MP
VDD
Vss
PC3/RTO3
to
PC7/RTO7
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F
PORT G
PORT H
PORT I
–2–
PORT J
Block Diagram
PC0 to PC7
8
PF4 to PF7
PG0 to PG7
PH0 to PH7
4
8
8
8
PJ0 to PJ7
PI1 to PI7
PF0 to PF3
4
7
PE2 to PE7
PE0 to PE1
6
2
PD0 to PD7
PB0 to PB7
8
8
PA0 to PA7
8
CXP81840A/81848A
CXP81840A/81848A
PI5/SCK1
PI4/INT1/NMI
PI3/TO/ADJ
PI2/PWM
PI1/RMC
TEX
TX
VDD
VSS
NC
PA7/PPO7
PA6/PPO6
PA5/PPO5
PA4/PPO4
PA3/PPO3
PA2/PPO2
PA1/PPO1
PA0/PPO0
PB7/PPO15
PB6/PPO14
Pin Configuration 1 (Top View) 100 pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB5/PPO13
1
80
PI6/SO1
PB4/PPO12
2
79
PI7/SI1
PB3/PPO11
3
78
PE0/INT0
PB2/PPO10
4
77
PE1/EC/INT2
PB1/PPO9
5
76
PE2/PWM0
PB0/PPO8
6
75
PE3/PWM1
PC7/RTO7
7
74
PE4/DAA0
PC6/RTO6
8
73
PE5/DAA1
PC5/RTO5
9
72
PE6/DAB0
PC4/RTO4
10
71
PE7/DAB1
PC3/RTO3
11
70
PG0
PC2/PPO18
12
69
PG1
PC1/PPO17
13
68
PG2
PC0/PPO16
14
67
PG3
PJ7
15
66
PG4
PJ6
16
65
PG5
PJ5
17
64
PG6/EXI0
PJ4
18
63
PG7/EXI1
PJ3
19
62
AN0
PJ2
20
61
AN1
PJ1
21
60
AN2
PJ0
22
59
AN3
PD7
23
58
PF0/AN4
PD6
24
57
PF1/AN5
PD5
25
56
PF2/AN6
PD4
26
55
PF3/AN7
PD3
27
54
AVDD
PD2
28
53
AVREF
PD1
29
52
AVSS
PD0
30
51
PF4/AN8
Note)
PF5/AN9
PF6/AN10
SCK0
PF7/AN11
SO0
SI0
CS0
EXTAL
XTAL
VSS
RST
MP
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1. NC (Pin 90) is always connected to VDD.
2. Vss (Pins 41 and 88) are both connected to GND.
–3–
CXP81840A/81848A
PE0/INT0
PI7/SI1
PI6/SO1
PI5/SCK1
PI4/INT1/NMI
PI3/TO/ADJ
PI2/PWM
PI1/RMC
TEX
TX
VDD
VSS
NC
PA7/PPO7
PA6/PPO6
PA5/PPO5
PA4/PPO4
PA3/PPO3
PA2/PPO2
PA1/PPO1
PA0/PPO0
PB7/PPO15
PB6/PPO14
PB5/PPO13
PB4/PPO12
Pin Configuration 2 (Top View) 100 pin LQFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB3/PPO11
1
75
PE1/EC/INT2
PB2/PPO10
2
74
PE2/PWM0
PB1/PPO9
3
73
PE3/PWM1
PB0/PPO8
4
72
PE4/DAA0
PC7/RTO7
5
71
PE5/DAA1
PC6/RTO6
6
70
PE6/DAB0
PC5/RTO5
7
69
PE7/DAB1
PC4/RTO4
8
68
PG0
PC3/RTO3
9
67
PG1
PC2/PPO18
10
66
PG2
PC1/PPO17
11
65
PG3
PC0/PPO16
12
64
PG4
PJ7
13
63
PG5
PJ6
14
62
PG6/EXI0
PJ5
15
61
PG7/EXI1
PJ4
16
60
AN0
PJ3
17
59
AN1
PJ2
18
58
AN2
PJ1
19
57
AN3
PJ0
20
56
PF0/AN4
PD7
21
55
PF1/AN5
PD6
22
54
PF2/AN6
PD5
23
53
PF3/AN7
PD4
24
52
AVDD
PD3
25
51
AVREF
Note)
1. NC (Pin 88) is always connected to VDD.
2. Vss (Pins 39 and 86) are both connected to GND.
–4–
AVSS
PF4/AN8
PF5/AN9
PF6/AN10
SCK0
PF7/AN11
SO0
SI0
CS0
EXTAL
VSS
XTAL
RST
MP
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PD0
PD1
PD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP81840A/81848A
Pin Description
Symbol
I/O
Description
PA0/PPO0
to
PA7/PPO7
Output/
Real time
Output
(Port A)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
PB0/PPO8
to
PB7/PPO15
Output/
Real time
Output
(Port B)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
PC0/PPO16
to
PC2/PPO18
I/O/
Real time
Output
PC3/RTO3
to
PC7/RTO7
I/O/
Real time
Output
(Port C)
8-bit I/O port, enables to
specify I/O by bit unit.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)
Programmable pattern generator (PPG)
output.
Functions as high precision real time
pulse output port.
(19 pins)
Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)
(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current.
(8 pins)
PD0 to PD7
I/O
PE0/INT0
Input/input
Input pin to request external interruption.
Active when falling edge.
PE1/EC/INT2
Input/input/input
External event
input pin for
timer/counter.
(Port E)
8-bit port. Lower 2 bits are
input pins and upper 6 bits
are output pins.
(8 pins)
Input pin to request
external interruption.
Active when falling edge.
PE2/PWM0
Output/output
PE3/PWM1
Output/output
PE4/DAA0
Output/output
PE5/DAA1
Output/output
PE6/DAB0
Output/output
PE7/DAB1
Output/output
AN0 to AN3
Input
Analog input pins to A/D converter. (12 pins)
PF0/AN4
to
PF3/AN7
Input/input
PF4/AN8
to
PF7/AN11
Output/input
(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)
SCK0
I/O
Serial clock (CH0) I/O pin.
SO0
Ouput
Serial data (CH0) output pin.
SI0
Input
Serial data (CH0) input pin.
CS0
Input
Serial chip select (CH0) input pin.
PWM output pins.
(2 pins)
DA gate pulse output pins.
(4 pins)
–5–
CXP81840A/81848A
Symbol
I/O
PG0 to PG5
Input
PG6/EXI0
Input/input
PG7/EXI1
Input/input
Description
(Port G)
8-bit input port.
(8 pins)
External input pin to FRC capture unit.
(Port H)
N-ch open drain output of middle tension proof (12V) and high current
(12mA).
(8 pins)
PH0 to PH7
Output
PI1/RMC
I/O/input
Remote control receiving circuit input pin.
PI2/PWM
I/O/output
14-bit PWM output pin.
PI3/TO/ADJ
I/O/output/output
PI4/INT1/
NMI
I/O/input/input
PI5/SCK1
I/O/I/O
PI6/SO1
I/O/output
Serial data (CH1) output pin.
PI7/SI1
I/O/input
Serial data (CH1) input pin.
PJ0 to PJ7
I/O
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open.
(Feedback resistor is not removed.)
RST
Input
System reset pin of active "Low" level.
MP
Input
Microprocessor mode input pin. Always connect to GND.
Timer/counter, 32kHz oscillation adjustment output
pin.
Input pin to request external interruption and
non maskable interruption. Active when falling edge.
Serial clock (CH1) I/O pin.
(Port J)
8-bit I/O port. Function as standby release input can be specified by
the bit unit. I/O can be specified by the bit unit.
Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.
Positive power supply pin of A/D converter.
AVDD
AVREF
(Port I)
7-bit I/O port.
I/O port can be
specified by the
bit unit.
(7 pins)
Input
Reference voltage input pin of A/D converter.
AVss
GND pin of A/D converter.
VDD
Positive power supply pin.
Vss
GND pin. Connect both Vss pins to GND.
–6–
CXP81840A/81848A
Input/Output Circuit Formats for Pins
Pin
When reset
Circuit format
Port A
AA
AA
Port B
PA0/PPO0
to
PA7/PPO7
PB0/PPO8
to
PB7/PPO15
AAAA
AAAA
PPO data
Port A or Port B
Data bus
Hi-Z
Output becomes active from high
impedance by data writing to port register.
RD
16 pins
Port C
PC0/PPO16
to
PC2/PPO18
AAAA
AAAA
AAAA
PPO, RTO data
Input
protection
circuit
Port C data
PC3/RTO3
to
PC7/RTO7
AA
AA
AA
AA
Hi-Z
IP
Port C direction
(Every bit)
Data bus
RD (Port C)
8 pins
Port D
PD0
to
PD7
AAAA
AAAA
AAAA
High
current
12mA
Port D data
IP
Port D direction
(Every 4 bits)
PD0 to 3
PD4 to 7
Data bus
8 pins
AA
AA
AA
AA
RD (Port D)
–7–
Hi-Z
CXP81840A/81848A
Pin
Port E
AA
AAA
Circuit format
When reset
Schmitt input
PE0/INT0
PE1/EC/INT2
2 pins
IP
Hi-Z
Data bus
RD (Port E)
AA
AA
AAAA
AA
AAAA
AA
AAAA
Port E
DA gate output
or PWM output
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
MPX
Hi-Z control
Port E data
AA
AA
Hi-Z
AA
AA
H level
Port/DA output
select
Data bus
4 pins
RD (Port E)
AA
AA
AAAA
AA
AAAA
AA
AAAA
Port E
DA gate output
MPX
Hi-Z control
PE6/DAB0
PE7/DAB1
Port E data
Port/DA output
select
Data bus
2 pins
RD (Port E)
AN0
to
AN3
Input multiplexer
A/D converter
IP
4 pins
Port F
PF0/AN4
to
PF3/AN7
AA
AA
AAAA
AAAA
Input multiplexer
IP
A/D converter
Hi-Z
Data bus
4 pins
Hi-Z
RD (Port F)
–8–
CXP81840A/81848A
Pin
Circuit format
When reset
Port F
PF4/AN8
to
PF7/AN11
AAAA
AAAAAAAA
AAAA
AA
AA
AAAA
Data bus
RD (Port F)
4 pins
PG0
to
PG5
6 pins
AA
AA
AA
AA
Port F data
IP
Port F selection
Port G
Input multiplexer
Schmitt input
IP
Data bus
PG6/EXI0
PG7/EXI1
AA
AA
AAAA
IP
2 pins
FRC capture unit
Hi-Z
Data bus
RD (Port G)
AAA
AAA
Port H
AA
AA
Middle tension proof 12V
Port H data
Data bus
8 pins
Hi-Z
RD (Port G)
Note) For PG4 and PG5, CMOS schmitt input or TTL schmitt input can be
selected with the mask option.
Port G
PH0
to
PH7
Hi-Z
A/D converter
Hi-Z
High current
12mA
RD (Port H)
Port I
AAAAAAA
AAA
AAAA
AAA
AAAAAAA
Port I selection
PI2: From 14-bit PWM
PI3:
PI2/PWM
PI3/TO/ADJ
From timer/counter,
32kHz timer
MPX
Port I data
Port I I/O direction
Data bus
2 pins
RD (Port I)
–9–
AA
AA
AA
AA
IP
Hi-Z
CXP81840A/81848A
AAAA
AAAA
AAAA
AAAA
PIn
Circuit format
Port I
AA
AA
AA
AA
Port I data
PI1/RMC
PI4/INT1/NMI
PI7/SI1
Port I direction
IP
Data bus
RD (Port I)
3 pins
When reset
Hi-Z
Schmitt input
PI1: To remote control circuit
PI4: To interruption circuit
PI7: To serial CH1
AAAA
AAAA AA
AAAA
AA
AAA
AAAA
AA
AAA
AAAA AAA
AAA
AAAA
AAAA
AAAA
AAAA
AA
AA
AAAA
Port I
AA
AA
AA
AA
Port I function
select
PI5/SCK1
PI6/SO1
From serial CH1
MPX
Port I data
MPX
Port I direction
IP
Note)
PI5 is schmitt input
PI6 is inverter input
Data bus
2 pins
RD (Port I)
To serial CH1
AA
AA
AA
AA
Port J
Port J data
PJ0
to
PJ7
Port J direction
CS0
SI0
RD
(Port J)
Edge detection
Standby release
Schmitt input
IP
2 pins
SO0
1 pin
Hi-Z
IP
Data bus
8 pins
Hi-Z
Hi-Z
To SIO
AA
AA
SO0 from SIO
SO0 output enable
– 10 –
Hi-Z
CXP81840A/81848A
PIn
Circuit format
Internal serial clock
from SIO
SCK0
External serial clock to SIO
Schmitt input
1 pin
2 pins
TEX
TX
2 pins
RST
AA
A
AA
A
AA
AA
AA
A
AA
A
AA
AA
AA
A
AA A
AA
AAAA
EXTAL
AA
AA
AA
AA
IP
SCK0 output enable
EXTAL
XTAL
When reset
• Shows the circuit
composition during
oscillation.
IP
• Feedback resistor is
removed during stop.
XTAL becomes "H"
level.
XTAL
32kHz
timer counter
TEX
Hi-Z
IP
TX
• Shows the circuit
composition during
oscillation.
• Feedback resistor is
removed during 32kHz
oscillation circuit stop
by software.
At this time TEX pin
outputs "L" level and TX
pin outputs "H" level.
Oscillation
Oscillation
Pull-up resistor
Mask option
Schmitt input
OP
L level
IP
1 pin
MP
IP
1 pin
– 11 –
CPU mode
Hi-Z
CXP81840A/81848A
Absolute Maximum Ratings
Item
(Vss = 0V)
Symbol
VDD
Supply voltage
AVDD
Rating
Unit
–0.3 to +7.0
AVss to +7.0∗1
V
V
Remarks
V
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0∗2
Output voltage
VOUT
–0.3 to +7.0∗2
V
Medium withstand output voltage
VOUTP
–0.3 to +15.0
V
High level output current
IOH
–5
mA
High level total output current
∑IOH
–50
mA
Total of output pins
IOL
15
mA
IOLC
20
mA
Other than high current output
pins: per pin
High current port pin∗3: per pin
Low level total output current
∑IOL
130
mA
Total of output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
AVSS
Low level output current
V
600
380
mW
PH pin
QFP package type
LQFP package type
∗1 AVDD and VDD should be set to a same voltage.
∗2 VIN and VOUT should not exceed VDD + 0.3V.
∗3 The high current operation transistors are the N-CH transistors of the PD and PH ports.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
– 12 –
CXP81840A/81848A
Recommended Operating Conditions
Item
Symbol
(Vss = 0V)
Min.
Max.
Unit
Remarks
4.5
5.5
3.0
5.5
2.7
5.5
V
Guaranteed range during low speed mode
(1/16 dividing clock) operation
2.7
5.5
V
Guaranteed operation range by TEX clock
2.5
5.5
V
3.0
5.5
V
Guaranteed data hold operation range
during STOP
∗1
VIH
0.7VDD
VDD
V
∗2
VIHS
0.8VDD
VDD
V
VIHTS
2.2
VDD
V
CMOS schmitt input∗3
TTL schmitt input∗4, ∗7
VDD – 0.4 VDD + 0.3
V
EXTAL pin∗5, ∗7 TEX pin∗6, ∗7
VDD – 0.2 VDD + 0.2
V
fc = less than 16MHz
V
Supply voltage
Analog power supply
HIgh level
input voltage
VDD
AVDD
VIHEX
0
0.3VDD
V
EXTAL pin∗5, ∗8 TEX pin∗6, ∗8
∗2, ∗7
0
0.2VDD
V
∗2, ∗8
VILS
0
0.2VDD
V
VILTS
0
0.8
V
–0.3
0.4
V
–0.3
0.2
V
–20
+75
°C
VIL
Low level
input voltage
fc = less than 12MHz
Guaranteed range
during high speed
mode (1/2 dividing
clock) operation
VILEX
Operating temperature Topr
CMOS schmitt input∗3
TTL schmitt input∗4, ∗7
EXTAL pin∗5, ∗7 TEX pin∗6, ∗7
EXTAL pin∗5, ∗8 TEX pin∗6, ∗8
∗1 AVDD and VDD should be set to a same voltage.
∗2 Normal input port (each pin of PC, PD, PE0, PE1, PF0 to PF3, PG, PI and PJ), MP pin.
∗3 Each pin of CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PG (For PG4 and PG5, when CMOS schmitt
input is selected with mask option), PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1.
∗4 Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)
∗5 It specifies only when the external clock is input.
∗6 It specifies only when the event count clock is input.
∗7 This case applies to the range of 4.5 to 5.5V supply voltage (VDD).
∗8 This case applies to the range of 3.0 to 3.6V supply voltage (VDD).
– 13 –
CXP81840A/81848A
Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)
Item
High level
output voltage
Low level
output voltage
Symbol
VOH
VOL
Pins
Input current
Min.
Typ.
Max.
Unit
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
PD, PH
VDD = 4.5V, IOL = 12.0mA
1.5
V
EXTAL
IIHT
IILT
Conditions
PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0
IIHE
IILE
(Ta = –20 to +75°C, Vss = 0V)
TEX
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIH = 5.5V
0.1
10
µA
–0.1
–10
µA
–1.5
–400
µA
IILR
RST∗1
VDD = 5.5V,
VIL = 0.4V
I/O leakage
current
IIZ
PA to PG,
PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST∗1
VDD = 5.5V,
VI = 0, 5.5V
±10
µA
Open drain
output leakage
current (N-CH
Tr OFF in state)
ILOH
PH
VDD = 5.5V
VOH = 12V
50
µA
24
45
mA
1.3
8
mA
35
100
µA
6
30
µA
10
µA
20
pF
16MHz crystal oscillation (C1 = C2 = 15pF)
IDD1
VDD = 5V ± 0.5V∗3
SLEEP mode
IDDS1
VDD = 5V ± 0.5V
Supply
current∗2
IDD2
IDDS2
32kHz crystal oscillation (C1 = C2 = 47pF)
VDD
VDD = 3V ± 0.3V
SLEEP mode
VDD = 3V ± 0.3V
IDDS3
STOP mode
(EXTAL and TEX pins oscillation stop)
VDD = 5V ± 0.5V
Input capacity
CIN
Other than VDD,
Clock 1MHz
Vss, AVDD, and
0V other than the measured pins
AVss
10
∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗2 When entire output pins are open.
∗3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).
– 14 –
CXP81840A/81848A
DC Characteristics (VDD = 3.0 to 3.6V)
Item
High level
output voltage
Low level
output voltage
Symbol
VOH
VOL
Pins
Input current
Min.
Typ.
Max.
Unit
VDD = 3.0V, IOH = –0.15mA
2.7
V
VDD = 3.0V, IOH = –0.5mA
2.3
V
PD, PH
EXTAL
IIHT
IILT
Conditions
PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0
IIHE
IILE
(Ta = –20 to +75°C, Vss = 0V)
TEX
VDD = 3.0V, IOL = 1.2mA
0.3
V
VDD = 3.0V, IOL = 1.6mA
0.5
V
VDD = 3.0V, IOL = 5mA
1.0
V
VDD = 3.6V, VIH = 3.6V
0.3
20
µA
VDD = 3.6V, VIL = 0.3V
–0.3
–20
µA
VDD = 3.6V, VIH = 3.6V
0.1
10
µA
–0.1
–10
µA
–0.9
–200
µA
IILR
RST∗1
VDD = 3.6V,
VIL = 0.3V
I/O leakage
current
IIZ
PA to PG,
PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST∗1
VDD = 3.6V,
VI = 0, 3.6V
±10
µA
Open drain
output leakage
current
ILOH
PH
VDD = 3.6V,
VOH = 12V
50
µA
11
25
mA
0.5
2.5
mA
12MHz crystal oscillation (C1 = C2 = 15pF)
IDD1
Supply
current∗2
IDDS1
IDDS3
VDD = 3.3V ± 0.3V∗3
SLEEP mode
VDD
VDD = 3.3V ± 0.3V
STOP mode
(EXTAL and TEX pins oscillation stop)
10
µA
VDD = 3.3V ± 0.3V
Input capacity
CIN
Other than VDD,
Clock 1MHz
Vss, AVDD, and
0V other than the measured pins
AVss
10
20
pF
∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗2 When entire output pins are open.
∗3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).
– 15 –
CXP81840A/81848A
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Item
Symbol
Pins
Conditions
Min.
VDD = 4.5 to 5.5V
System clock frequency
fC
XTAL
EXTAL
Fig. 1,
Fig. 2
System clock input pulse width
tXL,
tXH
EXTAL
VDD = 4.5 to 5.5V
Fig. 1,
Fig. 2 (External clock drive)
EXTAL
Fig. 1, Fig. 2
(External clock drive)
EC
Fig. 3
EC
Fig. 3
TEX
TX
Fig. 2 VDD = 2.7 to 5.5V
(32kHz clock applied condition)
TEX
Fig. 3
TEX
Fig. 3
Event count clock input
rise and fall times
tCR,
tCF
tEH,
tEL
tER,
tEF
System clock frequency
fC
Event count clock input
pulse width
tTL,
tTH
tTR,
tTF
System clock input
rise and fall times
Event count clock input
pulse width
Event count clock input
rise and fall times
Max. Unit
1
16
1
12
28
MHz
ns
37.5
200
tsys × 4∗
ns
ns
20
ns
32.768
kHz
10
µs
20
ms
∗ tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2
bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
0.4V
tCF
tXH
tXL
tCR
Fig. 2. Clock applied condition
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA AAAA AAAA
Crystal oscillation
Ceramic oscillation
EXTAL
C1
XTAL
C2
External clock
EXTAL
32kHz clock applying condition
crystal oscillation
TEX
XTAL
74HC04
– 16 –
C1
TX
C2
CXP81840A/81848A
Fig. 3. Event count clock timing
0.8VDD
TEX
EC
0.2VDD
tEH
tEF
tEL
tER
tTH
tTF
tTL
tTR
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pin
Condition
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↑ → SCK0
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS0 ↑ → SO0
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS0
high level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK0
cycle time
Input mode
SCK0
2tsys + 200
ns
tKCY
16000/fc
ns
SCK0
high and low level widths
tKH
tKL
tsys + 100
ns
SCK0
8000/fc – 50
ns
SI0 input setup time
(against SCK0 ↑)
SCK0 input mode
100
ns
tSIK
SI0
SCK0 output mode
200
ns
SI0 input hold time
(against SCK0 ↑)
SI0
tsys + 200
ns
tKSI
100
ns
SCK0 ↓ → SO0 delay time
tKSO
SO0
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11")
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
– 17 –
CXP81840A/81848A
Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)
Symbol
Pin
Condition
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 250 ns
CS0 ↑ → SCK0
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200 ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 250 ns
CS0 ↑ → SO0
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200 ns
CS0
high level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK0
cycle time
Input mode
SCK0
2tsys + 200
ns
tKCY
16000/fc
ns
SCK0
high and low level widths
tKH
tKL
tsys + 100
ns
SCK0
8000/fc – 100
ns
SI0 input setup time
(against SCK0 ↑)
SCK0 input mode
100
ns
tSIK
SI0
SCK0 output mode
200
ns
SI0 input hold time
(against SCK0 ↑)
SI0
tsys + 200
ns
tKSI
100
ns
SCK0 ↓ → SO0 delay time
tKSO
SO0
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys + 250
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11")
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF.
– 18 –
CXP81840A/81848A
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tKSI
tSIK
0.8VDD
Input
data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output
data
0.2VDD
– 19 –
CXP81840A/81848A
Serial transfer (CH1)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pins
Conditions
Input mode
SCK1 cycle time
tKCY
SCK1
SCK1 high and low
level widths
tKH
tKL
SCK1
SI1 input setup time
(against SCK1 ↑)
tSIK
SI1
SI1 input hold time
(against SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Min.
Max.
Unit
1000
ns
16000/fc
ns
400
ns
8000/fc – 50
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
SCK1 input mode
200
ns
SCK1 output mode
100
ns
Output mode
Input mode
Output mode
SCK1 input mode
200
ns
SCK1 output mode
100
ns
Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Serial transfer (CH1)
Item
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)
Symbol
Pins
Conditions
Input mode
SCK1 cycle time
tKCY
SCK1
SCK1 high and low
level widths
tKH
tKL
SCK1
SI1 input setup time
(against SCK1 ↑)
tSIK
SI1
SI1 input hold time
(against SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Min.
Max.
Unit
1000
ns
16000/fc
ns
400
ns
8000/fc – 100
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
SCK1 input mode
200
ns
SCK1 output mode
100
ns
Output mode
Input mode
Output mode
SCK1 input mode
250
ns
SCK1 output mode
100
ns
Note) The load of SCK1 output mode and SO1 output delay time is 50pF.
– 20 –
CXP81840A/81848A
Fig. 5. Serial transfer CH1 timing
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI1
0.2VDD
tKSO
0.8VDD
Output data
SO1
0.2VDD
– 21 –
CXP81840A/81848A
(3) A/D converter characteristics
Item
(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V)
Symbol
Conditions
Pins
Min.
Typ.
Resolution
Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V
Linearity error
Absolute error
Conversion time
Sampling time
tCONV
tSAMP
Reference input voltage VREF
AVREF
Analog input voltage
AN0 to AN11
VIAN
AVREF current
Bits
±1
LSB
±2
LSB
12/fADC∗
µs
AVDD
V
V
0
0.6
SLEEP mode
STOP mode
32kHz operating mode
AVREF
8
µs
Operating mode
IREFS
Unit
160/fADC∗
VDD = AVDD = 4.5 to 5.5V AVDD – 0.5
IREF
Max.
1.0
mA
10
µA
(Ta = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V)
Item
Symbol
Conditions
Pins
Min.
Typ.
Resolution
Ta = 25°C
VDD = AVDD = AVREF = 3.3V
VSS = AVSS = 0V
Linearity error
Absolute error
Conversion time
Sampling time
Reference input voltage VREF
AVREF
Analog input voltage
AN0 to AN11
IREFS
8
Bits
±1
LSB
±2
LSB
µs
µs
VDD = AVDD = 3.0 to 3.6V AVDD – 0.3
IREF
AVREF current
Unit
160/fADC∗
12/fADC∗
tCONV
tSAMP
VIAN
Max.
SLEEP mode
STOP mode
32kHz operating mode
0.4
0.7
mA
10
µA
Fig. 6. Definitions of A/D converter terms
Digital conversion value
FFH
FEH
∗ The value of fADC is as follows by selecting ADC
operation clock (MSC: Address 01FFH bit 0).
When PS2 is selected, fADC = fc/2
When PS1 is selected, fADC = fc
Linearity error
01H
00H
VFT
VZT
Analog input
– 22 –
V
V
0
Operating mode
AVREF
AVDD
CXP81840A/81848A
(4) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Symbol
Pin
Condition
External interruption
high and low level widths
tIH
tIL
INT0
INT1
INT2
NMI
PJ0 to PJ7
Reset input low level width
tRSL
Min.
Max.
Unit
1
µs
RST
32/fc
µs
tIH
tIL
Fig. 7. Interruption input timing
INT0
INT1
INT2
NMI
PJ0 to PJ7
(During standby release input)
(Falling edge)
0.8VDD
0.2VDD
Fig. 8. Reset input timing
tRSL
RST
0.2VDD
(5) Others
Item
EXI input high
and low level width
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Symbol
tEIH
tEIL
Pin
EXI0
EXI1
Min.
Condition
tsys = 2000/fc
Max.
tsys + 200
Unit
ns
Note) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11")
tFRC [ns] = 1000/fc
Fig. 9. Other timings
tEIH
EXI0
EXI1
tEIL
0.8VDD
0.2VDD
– 23 –
CXP81840A/81848A
Supplement
Fig. 10. Recommended oscillation circuit
AAAAA
AAAAA
AAAAA
(i)
EXTAL
(ii)
XTAL
TEX
Rd
C1
Model
C2
C1
fc (MHz)
C1 (pF)
C2 (pF)
10
10
8.00
RIVER
ELETEC
CO., LTD.
HC-49/U03
10.00
12.00
5
5
8.00
16
12
10.00
16
12
12.00
12
12
16.00
12
12
32.768kHz
30
18
16.00
HC-49/U (-S)
KINSEKI LTD.
P3
TX
Rd
C2
Manufacturer
AAAA
AAAA
AAAA
Rd (Ω)
Circuit
example
0
(i)
0
(i)
470k
(ii)
Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).
Mask option table
Item
Reset pin pull-up resistor
Input circuit format∗
Content
Non-existent
Existent
CMOS schmitt
TTL schmitt
∗ The input circuit format can be selected each for PG4 pin and PG5 pin.
However, TTL schmitt can not be selected when the supply voltage (VDD) ranges from 3.0V to 5.5V.
– 24 –
CXP81840A/81848A
Characteristics Curve
IDD vs. VDD
IDD vs. fc
(fc = 16MHz, Ta = 25°C, Typical)
(VDD = 5V, Ta = 25°C, Typical)
1/4 dividing mode
10.0
20
1/16 dividing mode
5.0
SLEEP mode
1.0
0.5
32kHz mode
(instruction)
0.1
(100µA)
0.05
(50µA)
32kHz
SLEEP mode
IDD – Supply current [mA]
IDD – Supply current [mA]
1/2 dividing mode
1/2 dividing mode
20.0
15
1/4 dividing mode
10
5
1/16 dividing mode
0.01
(10µA)
SLEEP mode
2
3
4
5
6
0
7
VDD – Supply voltage [V]
IDD vs. VDD
IDD vs. fc
(fc = 12MHz, Ta = 25°C, Typical)
(VDD = 3.3V, Ta = 25°C, Typical)
16
1/2 dividing mode
20.0
1/4 dividing mode
10.0
5.0
20
1/16 dividing mode
SLEEP mode
1.0
0.5
0.1
(100µA)
0.05
(50µA)
IDD – Supply current [mA]
IDD – Supply current [mA]
10
5
fc – System clock [MHz]
15
1/2 dividing mode
10
1/4 dividing mode
5
0.01
(10µA)
1/16 dividing mode
SLEEP mode
2
3
4
5
6
7
0
VDD – Supply voltage [V]
– 25 –
5
10
fc – System clock [MHz]
16
CXP81840A/81848A
Unit: mm
100PIN QFP (PLASTIC)
+ 0.4
14.0 – 0.01
17.9 ± 0.4
15.8 ± 0.4
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
0° to 15°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
QFP-100P-L01
LEAD TREATMENT
EIAJ CODE
∗QFP100-P-1420-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g
JEDEC CODE
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗
14.0 ± 0.1
75
51
76
(15.0)
50
0.5 ± 0.2
A
26 (0.22)
100
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
25
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0.1 ± 0.1
0° to 10°
0.5 ± 0.2
Package Outline
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY/PHENOL RESIN
SONY CODE
LQFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP100-P-1414-A
LEAD MATERIAL
42 ALLOY
JEDEC CODE
PACKAGE WEIGHT
– 26 –