SONY CXP81120Q

CXP81120/81124
CMOS 8-bit Single Chip Microcomputer
Description
The CXP81120/81124 is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, PWM
output, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.
Also the CXP81120/81124 provides power-on reset
function, sleep/stop function which enables to lower
power consumption.
64 pin QFP (Plastic)
64 pin LQFP (Plastic)
Features
• A wide instruction set (213 instructions) which covers various types of data
— 16-bit operation/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation (4.5 to 5.5V)
333ns at 12MHz operation (3.0 to 5.5V)
• Incorporated ROM capacity
20K bytes (CXP81120)
24K bytes (CXP81124)
• Incorporated RAM capacity
832 bytes
• Peripheral functions
— A/D converter
8-bit, 8-channel, successive approximation system
(Conversion time: 20µs at 16MHz)
— Serial interface
Incorporated buffer RAM (1 to 32 bytes auto transfer), 1 channel
Incorporated 8-bit and 8-stage FIFO
(1 to 8 bytes auto transfer), 1 channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer
— PWM output
12 bits, 2 channels
• Interruption
10 factors, 10 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
64-pin plastic QFP/LQFP
• Piggyback/evaluator
CXP81100 64-pin ceramic PQFP
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94414A69-PS
AVDD
12BIT PWM GENERATOR CH0
12BIT PWM GENERATOR CH1
PWM0
PWM1
8BIT TIMER 1
FIFO
BUFFER
RAM
TO
SERIAL
INTERFACE UNIT
(CH1)
SERIAL
INTERFACE UNIT
(CH0)
A/D CONVERTER
2
INT1
INTERRUPT CONTROLLER
AVREF
8BIT TIMER/COUNTER 0
8
AVss
EC
SCK1
SI1
SO1
CS0
SI0
SO0
SCK0
AN0 to AN7
ROM
20K/24K BYTES
SPC700
CPU CORE
VDD
Vss
MP
RST
EXTAL
XTAL
PRESCALER/
TIME BASE TIMER
RAM
832 BYTES
CLOCK
GENERATOR/
SYSTEM CONTROL
PG3 to PG4
PG5 to PG7
2
3
PF4 to PF7
4
PE2 to PE3
2
PF0 to PF3
PE0 to PE1
2
4
PD0 to PD7
PC0 to PC7
8
8
PB0 to PB7
8
PA0 to PA7
8
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F
–2–
PORT G
Block Diagram
CXP81120/81124
INT2
INT0
CXP81120/81124
PG3/TO
PG4
PA7
PA6
PA5
PA4
NC
VDD
VSS
PA3
PA2
PA0
PA1
Pin Configuration (Top View) 64-pin QFP
64 63 62 61 60 59 58 57 56 55 54 53 52
PB7
1
51
PG5/SCK1
PB6
2
50
PG6/SO1
PB5
3
49
PG7/SI1/INT1
PB4
4
48
PE0/INT0
PB3
5
47
PE1/EC/INT2
PB2
6
46
PE2/PWM0
PB1
7
45
PE3/PWM1
PB0
8
44
PF0/AN0
PC7
9
43
PF1/AN1
PC6
10
42
PF2/AN2
PC5
11
41
PF3/AN3
PC4
12
40
PF4/AN4
PC3
13
39
PF5/AN5
PC2
14
38
PF6/AN6
PC1
15
37
PF7/AN7
PC0
16
36
AVDD
PD7
17
35
AVREF
PD6
18
34
AVSS
PD5
19
33
SCK0
Note) 1.
2.
3.
SO0
SI0
CS0
RST
VSS
EXTAL
XTAL
MP
PD0
PD1
PD2
PD3
PD4
20 21 22 23 24 25 26 27 28 29 30 31 32
NC (Pin 58) is always connected to VDD.
Vss (Pins 28 and 60) are both connected to GND.
MP (Pin 25) is always connected to GND.
–3–
CXP81120/81124
PG5/SCK1
PG4
PG3/TO
PA7
PA6
PA5
PA4
NC
VSS
VDD
PA3
PA2
PA1
PB7
PA0
PB6
Pin Configuration (Top View) 64-pin LQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PB5
1
48
PG6/SO1
PB4
2
47
PG7/SI1/INT1
PB3
3
46
PE0/INT0
PB2
4
45
PE1/EC/INT2
PB1
5
44
PE2/PWM0
PB0
6
43
PE3/PWM1
PC7
7
42
PF0/AN0
PC6
8
41
PF1/AN1
PC5
9
40
PF2/AN2
PC4
10
39
PF3/AN3
PC3
11
38
PF4/AN4
PC2
12
37
PF5/AN5
PC1
13
36
PF6/AN6
PC0
14
35
PF7/AN7
PD7
15
34
AVDD
PD6
16
33
AVREF
Note) 1.
2.
3.
AVSS
SCK0
SO0
SI0
CS0
RST
VSS
EXTAL
XTAL
MP
PD0
PD1
PD2
PD3
PD4
PD5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC (Pin 56) is always connected to VDD.
Vss (Pins 26 and 58) are both connected to GND.
MP (Pin 23) is always connected to GND.
–4–
CXP81120/81124
Pin Description
I/O
Symbol
Description
PA0 to PA7
Output
(Port A)
8-bit output port.
(8 pins)
PB0 to PB7
Output
(Port B)
8-bit output port.
(8 pins)
PC0 to PC7
I/O
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
PD0 to PD7
I/O
(Port D)
8-bit I/O port. I/O and function as standby release input can be set in a unit of
single bits.
(8 pins)
PE0/INT0
Input/Input
(Port E)
4-bit port. Lower 2 bits
are for input; upper 2 bits
are for output.
(4 pins)
Input to request external interruption.
Active at the falling edge. (2 pins)
External event
input for
timer/counter.
PE1/EC/INT2
Input/Input/
Input
PE2/PWM0
Output/Output
PE3/PWM1
Output/Output
PF0/AN0
to
PF3/AN3
Input/Input
PF4/AN4
to
PF7/AN7
Output/Input
SCK0
I/O
Serial clock (CH0) I/O.
SO0
Output
Serial data (CH0) output.
SI0
Input
Serial data (CH0) input.
CS0
Input
Serial interface (CH0) chip select input.
PG3/TO
Output/Output
PG4
Output
PG5/SCK1
I/O/I/O
PG6/SO1
I/O/Output
I/O/Input
PG7/SI1/INT1 Input
EXTAL
Input
XTAL
Output
RST
I/O
12-bit PWM output. (2 pins)
(Port F)
8-bit port. Lower 4 bits are for input; upper
4 bits are for output.
Lower 4 bits also serve as standby release
input.
(8 pins)
Analog input to A/D
converter.
(8 pins)
Timer/counter rectangular wave output.
(Port G)
5-bit port. Lower 2 bits
are for output; upper
3 bits are for I/O.
I/O can be set in a unit
of single bits.
(5 pins)
Serial clock (CH1) I/O.
Serial data (CH1) output.
Input to request external
Serial data (CH1)
interruption. Active at the
input.
falling edge.
Connects a crystal oscillator for system clock. When supplying the external
clock, input the external clock to EXTAL pin and input opposite phase
clock to XTAL pin.
System reset; active at Low level. RST pin is I/O pin, which outputs “Low”
level by incorporated power-on reset function when power turns on.
(Mask option)
–5–
CXP81120/81124
Symbol
I/O
NC pin.
Connect to VDD for normal operation.
NC
MP
Input
AVDD
AVREF
Description
Test mode pin.
Always connect to GND.
Positive power supply of A/D converter.
Input
Reference voltage input of A/D converter.
AVSS
GND of A/D converter.
VDD
Positive power supply.
VSS
GND. Connect both Vss pins to GND.
–6–
CXP81120/81124
Input/Output Circuit Formats for Pins
Pin
Circuit format
When reset
Port A
Port B
PA0 to PA7
PB0 to PB7
AA
AA
AAAA
Ports A, B data
Hi-Z
Data bus
Output becomes active from high impedance
by data writing to port register.
RD (Ports A, B)
16 pins
AA
AA
AA
AA
Port C
AAAA
AAAA
AAAA
Port C data
PC0 to PC7
Input
protection
circuit
Port C direction
“0” when reset
Data bus
8 pins
Hi-Z
IP
RD (Port C)
Port D
AAAA
AAAA
AAAA
AA
AA
AA
A
AAA
Port D data
Port D direction
PD0 to PD7
“0” when reset
Data bus
RD (Port D)
Edge detection
AA
AA
AA
AA
Hi-Z
IP
Standby release
8 pins
Port E
Schmitt input
PE0/INT0
IP
1 pin
1 pin
Hi-Z
Data bus
RD (Port E)
Port E
PE1/EC/INT2
EC/INT2
AA
A
AAA
Schmitt input
INT0
IP
Hi-Z
Data bus
RD (Port E)
–7–
CXP81120/81124
Pin
AAA
AAA
AAAA
AAA
AAAAA
AAAA
AAA
AAAAA
Circuit format
When reset
AA
AA
Port E
PWM
MPX
Hi-Z control
PE2/PWM0
PE3/PWM1
Port E data
Hi-Z
Port E function selecton
“0” when reset
Data bus
2 pins
RD (Port E)
AAAA
AA
Port F
input multiplexer
A/D converter
IP
PF0/AN0
to
PF3/AN3
Hi-Z
Data bus
AA
RD (Port F)
Edge detection
4 pins
AAA
AA
AAAAAAA AA
AA
AA
AAAA
AAAA
AAAAAA
AA
AA
AAAAAA
AA
Port F
PF4/AN4
to
PF7/AN7
Port F data
Data bus
IP
RD (Port F)
4 pins
Standby release
Port F function
selection
“0” when reset
Hi-Z
Input multiplexer
A/D converter
Port G
Port G function
selection
PG3/TO
“0” when reset
Timer/counter
MPX
Port G data
“1” when reset
1 pin
–8–
High level
CXP81120/81124
Pin
Circuit format
Port G
PG4
When reset
AAAA
AA
AA
Port G data
“1” when reset
1 pin
H level
AAAA
AAAAAAA
AA
AAA
AAA
AA
AA
AAA
AAA
AA
AA
AAA
AA
AA
AA
AAAA
AAAA
AA
AAAA
AA
AAAA
AA
AA
Port G
Port G function
selection
“0” when reset
SCK1 out, SO1
PG5/SCK1
PG6/SO1
Serial clock 1/data 1
output enable
MPX
Port G data
Port G direction
MPX
Hi-Z
IP
“0” when reset
Data bus
∗1
RD (Port G)
SCK1 in
2 pins
∗1 PG6 is not Schmitt input
Port G
Port G data
PG7/SI1/INT1
Port G direction
“0” when reset
Hi-Z
IP
Data bus
RD (Port G)
1 pin
CS0
SI0
2 pins
SO0
1 pin
Schmitt input
INT1
SI1
AA
AA
AAAA
Schmitt input
IP
Hi-Z
CS0
SI0
AA
AA
SO0
Serial data 0
output enable
–9–
Hi-Z
CXP81120/81124
Pin
Circuit format
SCK0 out
SCK0
Serial clock 0
output enable
SCK0 in
AA AA
AA
AA
AA
A
AA
AA
A
AAA
EXTAL
2 pins
XTAL
AA
AA
AA
AA
IP
1 pin
EXTAL
XTAL
When reset
Schmitt input
Hi-Z
• Diagram shows the
circuit composition
during oscillation.
IP
• Feedback resistor is
removed during stop.
XTAL becomes “High”
level.
Oscillation
Pull-up resistor
RST
Mask option
Schmitt input
OP
Low level
IP
1 pin
MP
IP
1 pin
– 10 –
From power-on reset circuit
(Mask option)
Test mode
Hi-Z
CXP81120/81124
Absolute Maximum Ratings
Item
Supply voltage
(Vss = 0V reference)
Symbol
Rating
Unit
VDD
–0.3 to +7.0
V
AVDD
AVSS to +7.0
V
AVSS
–0.3 to +0.3
V
AVREF
V
Remarks
Input voltage
VIN
AVSS to +7.0
–0.3 to +7.0∗1
Output voltage
VOUT
–0.3 to +7.0∗1
V
High level output current
IOH
–5
mA
High level total output current
∑IOH
–50
mA
Low level output current
IOL
15
mA
Low level total output current
∑IOL
130
mA
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
PD
600
mW
QFP-64P-L01
Allowable power dissipation
380
mW
LQFP-64P-L01
V
Total of output pins
Total of output pins
∗1 VIN and VOUT should not exceed VDD + 0.3V. (CS0 and SI0 excluded.)
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding those conditions may adversely
affect the reliability of the LSI.
– 11 –
CXP81120/81124
Recommended Operating Conditions
Item
Supply voltage
Analog voltage
High level
input voltage
Symbol
Min.
Max.
Unit
Remarks
3.0
5.5
V
Guaranteed operation range for 1/2 and 1/4
frequency dividing mode
2.7
5.5
V
Guaranteed operation range for 1/16
frequency dividing mode
2.5
5.5
V
3.0
5.5
V
Guaranteed data hold range during stop
mode
∗1
VIH
0.7VDD
VDD
V
∗2
VIHS
0.8VDD
VDD
V
5.5
V
VDD
AVDD
VIHEX
VIL
Low level
input voltage
(Vss = 0V reference)
0.3VDD
V
EXTAL pin∗5
∗2, ∗7
0.2VDD
V
∗2, ∗6
VDD – 0.4 VDD + 0.3
0
V
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Operating temperature Topr
–20
+75
°C
∗1
∗2
∗3
∗4
∗5
∗6
∗7
CMOS Schmitt input∗3
CMOS Schmitt input∗4
AVDD should be the same voltage as VDD.
Normal input port (PC, PD, PF0 to PF3 and PG6 pins), MP pin.
SCK0, RST, INT0, EC/INT2, SCK1 and SI1/INT1 pins.
CS0 and SI0 pins.
Specified only when the external clock is input.
In case of 3.0 to 3.6V supply voltage (VDD).
In case of 4.5 to 5.5V supply voltage (VDD).
– 12 –
CMOS Schmitt input∗3, ∗4
EXTAL pin∗5
CXP81120/81124
DC Characteristics
Supply voltage (VDD = 4.5 to 5.5V)
Item
High level
output voltage
Symbol
VOH
Low level
VOL
output voltage
IIHE
Input current
I/O leakage
current
IILE
(Ta = –20 to +75°C, Vss = 0V reference)
Pin
PA to PE,
PF4 to PF7,
SO0, SCK0,
RST∗1
(VOL only)
PG3 to PG7
EXTAL
Condition
Min.
Typ.
Max.
Unit
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 0.4V
–1.5
–400
µA
±10
µA
20
40
mA
1
5
mA
10
µA
20
pF
IILR
RST∗2
IIZ
PA to PG, MP,
VDD = 5.5V,
CS0, SI0, SO0,
VI = 0, 5.5V
SCK0, RST∗2
1/2 frequency dividing mode
VDD = 5V ± 0.5V,
16MHz crystal oscillation
(C1 = C2 = 15pF)
IDD1
Supply
current∗3
Sleep mode
IDDS1
VDD
VDD = 5V ± 0.5V,
16MHz crystal oscillation
(C1 = C2 = 15pF)
Stop mode
IDDS3
Input capacity
CIN
VDD = 5.5V,
termination of 16MHz oscillation
PC, PD,
PE0, PE1,
PF,
PG5 to PG7,
RST, CS0,
SI0, SCK0,
EXTAL
Clock 1MHz
0V other than the measured pins
10
∗1 RST pin is specified only when the power-on reset circuit is selected with mask option.
∗2 For RST pin, specifies the input current when the pull-up resistance is selected, and specifies leakage
current when non-resistance is selected.
∗3 When all output pins are open.
– 13 –
CXP81120/81124
DC Characteristics
Supply voltage (VDD = 3.0 to 3.6V)
Item
High level
output voltage
Symbol
VOH
Low level
VOL
output voltage
IIHE
Input current
I/O leakage
current
IILE
(Ta = –20 to +75°C, Vss = 0V reference)
Pin
PA to PE,
PF4 to PF7,
SO0, SCK0,
RST∗1
(VOL only)
PG3 to PG7
EXTAL
Condition
Min.
Typ.
Max.
Unit
VDD = 3.0V, IOH = –0.15mA
2.7
V
VDD = 3.0V, IOH = –0.5mA
2.3
V
VDD = 3.0V, IOL = 1.2mA
0.3
V
VDD = 3.0V, IOL = 1.6mA
0.5
V
VDD = 3.6V, VIH = 3.6V
0.3
20
µA
VDD = 3.6V, VIL = 0.3V
–0.3
–20
µA
VDD = 3.6V, VIL = 0.3V
–0.9
–200
µA
±10
µA
10
20
mA
0.5
2.5
mA
10
µA
20
pF
IILR
RST∗2
IIZ
PA to PG, MP,
VDD = 3.6V,
CS0, SI0, SO0,
VI = 0, 3.6V
SCK0, RST∗2
1/2 frequency dividing mode
VDD = 3.3V ± 0.3V,
12MHz crystal oscillation
(C1 = C2 = 15pF)
IDD2
Supply
current∗3
Sleep mode
IDDS2
VDD
VDD = 3.3V ± 0.3V,
12MHz crystal oscillation
(C1 = C2 = 15pF)
Stop mode
IDDS3
Input capacity
CIN
VDD = 5.5V,
termination of 12MHz oscillation
PC, PD,
PE0, PE1,
PF,
PG5 to PG7,
RST, CS0,
SI0, SCK0,
EXTAL
Clock 1MHz
0V other than the measured pins
10
∗1 RST pin is specified only when the power-on reset circuit is selected with mask option.
∗2 For RST pin, specifies the input current when the pull-up resistance is selected, and specifies leakage
current when non-resistance is selected.
∗3 When all output pins are open.
– 14 –
CXP81120/81124
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
VDD = 4.5 to 5.5V
System clock frequency
fC
XTAL
EXTAL
Fig. 1,
Fig. 2
System clock
input pulse width
tXL,
tXH
XTAL
EXTAL
VDD = 4.5 to 5.5V
Fig. 1,
Fig. 2 (External clock drive)
System clock input
rise and fall times
tCR,
tCF
tEL,
tEH
tER,
tEF
EXTAL
Fig. 1, Fig. 2
(External clock drive)
EC
Fig. 3
EC
Fig. 3
Event count input clock
pulse width
Event count input clock
rise and fall times
Min.
Max.
1
16
1
12
Unit
MHz
28
ns
37.5
ns
200
4tsys∗1
ns
20
ms
∗1 tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Fig. 1. Clock timing
1/fc
VDD – 0.4V (VDD = 4.5 to 5.5V)
VDD – 0.3V
EXTAL
0.4V (VDD = 4.5 to 5.5V)
0.3V
tXH
tCF
Fig. 2. Clock applied condition
AAAA
AAAA
AAAA
External clock
EXTAL
XTAL
C1
tCR
AAAA
AAAA
AAAA
Crystal oscillation
Ceramic oscillation
EXTAL
tXL
C2
XTAL
74HC04
Fig. 3. Event count clock timing
0.8VDD
EC
0.2VDD
tEH
tEF
– 15 –
tEL
tER
CXP81120/81124
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
Condition
Min.
Max.
Unit
CS ↓ → SCK
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↑ → SCK
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↓ → SO
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS ↓ → SO
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS
high level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK
cycle time
Input mode
SCK0
2tsys + 200
ns
tKCY
8000/fc
ns
SCK
high and low level widths
tKH
tKL
tsys + 100
ns
SCK0
Output mode
8000/fc – 100
ns
SI input setup time
(for SCK ↑)
SCK input mode
SI0
–tsys + 100
ns
tSIK
200
ns
SI input hold time
(for SCK ↑)
SI0
2tsys + 100
ns
tKSI
100
ns
SCK ↓ → SO delay time
tKSO
SO0
Output mode
Input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
2tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0, and SO0, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
– 16 –
CXP81120/81124
Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Symbol
Pin
Condition
Min.
Max.
Unit
CS ↓ → SCK
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 250
ns
CS ↑ → SCK
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↓ → SO
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 250
ns
CS ↓ → SO
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS
high level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK
cycle time
Input mode
SCK0
2tsys + 200
ns
tKCY
8000/fc
ns
SCK
high and low level widths
tKH
tKL
tsys + 100
ns
SCK0
Output mode
8000/fc – 150
ns
SI input setup time
(for SCK ↑)
SCK input mode
SI0
–tsys + 100
ns
tSIK
200
ns
SI input hold time
(for SCK ↑)
SI0
2tsys + 100
ns
tKSI
100
ns
SCK ↓ → SO delay time
tKSO
SO0
Output mode
Input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
2tsys + 250
ns
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0, and SO0, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.
– 17 –
CXP81120/81124
Fig. 4. Serial transfer timing (CH0)
tWHCS
CSO
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
– 18 –
CXP81120/81124
Serial transfer (CH1) (SIO mode)
Item
Symbol
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Pin
Condition
tKCY
SCK1
SCK1 high and low
level widths
tKH
tKL
SCK1
SI1 input setup time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Max.
Unit
2tsys + 200
ns
16000/fc
ns
tsys + 100
ns
8000/fc – 50
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
tsys + 200
ns
100
ns
Input mode
SCK1 cycle time
Min.
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Serial transfer (CH1) (SIO mode)
Item
Symbol
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Pin
SCK1 cycle time
tKCY
SCK1
SCK1 high and low
level widths
tKH
tKL
SCK1
SI1 input setup time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Condition
Min.
Max.
Unit
2tsys + 200
ns
16000/fc
ns
tsys + 100
ns
8000/fc – 150
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
tsys + 200
ns
100
ns
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
tsys + 250
ns
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.
– 19 –
CXP81120/81124
Fig. 5. Serial transfer CH1 timing (SIO mode)
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI1
0.2VDD
tKSO
0.8VDD
SO1
Output data
0.2VDD
– 20 –
CXP81120/81124
Serial transfer (CH1) (Special mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Min.
∗1
Typ.
Max.
Unit
SO1 cycle time
tLCY
SO1
SI1
SI1 data setup time
tLSU
tLHD
SI1
2
µs
SI1
2
µs
SI1 data hold time
∗1
104
µs
tLCY is specified only when serial mode register (CH1) (SIOM1: 01FAH) lower 2 bits (SO1 clock selection) is
set at 104µs according to the system clock frequency.
Note) The load of SO1 pin is 50pF + 1TTL.
Serial transfer (CH1) (Special mode) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Min.
∗1
Typ.
Max.
Unit
SO1 cycle time
tLCY
SO1
SI1
SI1 data setup time
tLSU
tLHD
SI1
2
µs
SI1
2
µs
SI1 data hold time
∗1
104
µs
tLCY is specified only when serial mode register (CH1) (SIOM1: 01FAH) lower 2 bits (SO1 clock selection) is
set at 104µs according to the system clock frequency.
Note) The load of SO1 pin is 50pF.
Fig. 6. Serial transfer CH1 timing (Special mode)
tLCY
SO1
tLCY
Start bit
Output data bit
0.5VDD
tLCY/2
tLSU
tLHD
Input
data bit
SI1
– 21 –
0.8VDD
0.2VDD
CXP81120/81124
(3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
Item
Symbol
Pin
Condition
Min.
Typ.
Resolution
Only for A/D converter
operation
Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V
Linearity error
Absolute error
Sampling time
Reference input voltage VREF
Analog input voltage
AVREF current
AVREF
VIAN
Item
AVREF
Pin
0
Operating mode
AVREF = 4.0 to 5.5V
0.6
Sleep mode
Stop mode
Condition
Min.
Typ.
Only for A/D converter
operation
Ta=25°C
VDD = AVDD = AVREF = 3.3V
VSS = AVSS = 0V
Linearity error
Absolute error
LSB
±2
LSB
AVDD
V
AVREF
V
1.0
mA
10
µA
AVREF
Analog input voltage
AN0 to AN7
VIAN
IREF
Max.
Unit
8
Bits
±1
LSB
±2
LSB
160/fADC∗1
12/fADC∗1
tCONV
tSAMP
Reference input voltage VREF
AVREF current
±1
µs
Resolution
Sampling time
Bits
(Ta = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V reference)
Symbol
Conversion time
8
µs
VDD = AVDD = 4.5 to 5.5V AVDD – 0.5
AN0 to AN7
IREF
A/D converter characteristics
Unit
160/fADC∗1
12/fADC∗1
tCONV
tSAMP
Conversion time
Max.
AVREF
µs
µs
VDD = AVDD = 3.0 to 3.6V AVDD – 0.3
0
Operating mode
AVREF = 2.7 to 3.6V
0.4
Sleep mode
Stop mode
AVDD
V
AVREF
V
0.7
mA
10
µA
Fig. 7. Definitions of A/D converter terms
Digital conversion value
FFH
FEH
∗1 The value of fADC is as follows by interruption selection/
ADC operation clock selection regeister (MSC: 01FFH )
bit 0 (ADCCK).
When PS2 is selected, fADC = fc/2
Linearity error
01H
When PS1 is selected, fADC = fc
00H
VFT
VZT
Analog input
– 22 –
CXP81120/81124
(4) Interruption, reset input
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
External interruption
high and low level widths
tIH
tIL
INT0
INT1
INT2
PJ0 to PJ7
Reset input low level width
tRSL
RST
Min.
Max.
Unit
1
µs
32/fc
µs
Fig. 8. Interruption input timing
tIH
INT0
INT1
INT2
PD0 to PD7
(During standby release input)
(Falling edge)
tIL
0.8VDD
0.2VDD
Fig. 9. Reset input timing
tRSL
RST
0.2VDD
(5) Power-on reset∗1
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
Item
Symbol Pin
tR
tOFF
Power supply rising time
VDD
Condition
Power-on reset
Repetitive power-on reset
Power supply cut-off time
∗1 Specifies only when power-on reset function is selected.
Min.
Max.
Unit
0.05
30
ms
1
ms
Fig. 10. Power-on reset
VDD
3.0V
0.2V
0.2V
tR
tOFF
The power supply should be turned on smoothly.
– 23 –
CXP81120/81124
Appendix
Fig. 11. SPC 700 Series recommended oscillation circuit
AAAA
AAAA
AAAA
Main clock
EXTAL
XTAL
Rd
C1
C2
Manufacturer
RIVER ELETEC
CO., LTD.
Model
fc (MHz)
C1 (pF)
C2 (pF)
8.00
10
10
5
5
22 (15)
22 (15)
12.00
15
15
16.00
12
12
10.00
HC-49/U03
12.00
Rd (Ω)
Circuit
example
0
(i)
0
(i)
16.00
8.00
KINSEKI LTD.
HC-49/U (-S)
10.00
Mask Option Table
Item
Content
Reset pin pull-up resistor
Non-existent
Existent
Power-on reset circuit
Non-existent
Existent
– 24 –
CXP81120/81124
Characteristics Curve
IDD vs. VDD
IDD vs. fc
(fc = 16MHz, Ta = 25°C, Typical)
(VDD = 5V, Ta = 25°C, Typical)
20
1/2 dividing mode
1/4 dividing mode
1/2 dividing mode
1/16 dividing mode
Sleep mode
1.0
IDD – Supply current [mA]
IDD – Supply current [mA]
10
15
1/4 dividing mode
10
5
1/16 dividing mode
0.1
Sleep mode
2
3
4
5
6
VDD – Supply voltage [V]
1
7
5
10
15
fc – System clock [MHz]
IDD vs. VDD
IDD vs. fc
(fc = 12MHz, Ta = 25°C, Typical)
(VDD = 3.3V, Ta = 25°C, Typical)
20
1/2 dividing mode
IDD – Supply current [mA]
1/16 dividing mode
Sleep mode
1.0
IDD – Supply current [mA]
1/4 dividing mode
10
15
10
1/2 dividing mode
1/4 dividing mode
5
0.1
1/16 dividing mode
Sleep mode
2
3
4
5
6
7
1
VDD – Supply voltage [V]
5
10
fc – System clock [MHz]
– 25 –
15
CXP81120/81124
Package Outline
Unit: mm
64PIN QFP(PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
51
0.15
64
20
1
16.3
32
+ 0.4
14.0 – 0.1
52
17.9 ± 0.4
33
+ 0.2
0.1 – 0.05
0.8 ± 0.2
19
+ 0.15
0.4 – 0.1
1.0
+ 0.35
2.75 – 0.15
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP–64P–L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
QFP064–P–1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.5g
JEDEC CODE
– 26 –
CXP81120/81124
64PIN LQFP (PLASTIC)
12.0 ± 0.2
∗
10.0 ± 0.1
48
33
32
64
17
(0.22)
0.5 ± 0.2
(11.0)
49
A
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
16
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-64P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
LQFP064-P-1010
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.3g
JEDEC CODE
– 27 –