Revised August 1999 74F823 9-Bit D-Type Flip-Flop General Description Features The 74F823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. ■ 3-STATE outputs ■ Clock Enable and Clear Ordering Code: Order Number Package Number Package Description 74F823SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F823SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009596 www.fairchildsemi.com 74F823 9-Bit D-Type Flip-Flop April 1988 74F823 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL D0–D8 Data Inputs 1.0/1.0 20 µA/−0.6 mA OE Output Enable Input 1.0/1.0 20 µA/−0.6 mA CLR Clear 1.0/1.0 20 µA/−0.6 mA 20 µA/−1.2 mA CP Clock Input 1.0/2.0 EN Clock Enable 1.0/1.0 20 µA/−0.6 mA O0–O8 3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) Function Table Functional Description The 74F823 device consists of nine D-type edge-triggered flip-flops. It has 3-STATE true outputs and is organized in broadside pinning. The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flipflops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOWto-HIGH CP transition. With the OE LOW the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. In addition to the Clock and Output Enable pins, the 74F823 has Clear (CLR) and Clock Enable (EN) pins. When the CLR is LOW and the OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flipflops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state regardless of the data or clock inputs transitions. This device is ideal for parity bus interfacing in high performance systems. Inputs Internal Output Function OE CLR EN CP D Q O H H L H X NC Z Hold H H L L X NC Z Hold H H H X X NC Z Hold L H H X X NC NC Hold H L X X X H Z Clear L L X H L Clear H H L H H Z Load H H L H L Z Load L H L X L H L Data Available L H L L H L L H L X H L H H X NC NC No Change in Data Data Available L X NC NC No Change in Data L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 5% VCC 2.7 5% VCC 2.7 VOL Output LOW V IOH = −3 mA IOH = −1 mA IOL = 24 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 Input LOW −0.6 mA Max VIN = 0.5V (OE, CLR, EN) Current −1.2 mA Max VIN = 0.5V (CP) Input HIGH Input HIGH Current Output HIGH Input Leakage 4.75 Output Leakage Circuit Current IIL Min Min Test IOD IIN = −18 mA V 10% VCC Leakage Current VID Recognized as a LOW Signal Min IOH = −3 mA Breakdown Test ICEX Conditions Recognized as a HIGH Signal IOH = −1 mA Current IBVI VCC V 0.5 Voltage IIH 2.0 Units VIH IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded IOZH Output Leakage Current 50 µA Max VOUT = 2.7V IOZL Output Leakage Current −50 µA Max VOUT = 0.5V IOS Output Short-Circuit Current −150 mA Max VOUT = 0V IZZ Buss Drainage Test 500 µA 0.0V VOUT = 5.25V ICCZ Power Supply Current 100 mA Max VO = HIGH Z −60 75 3 www.fairchildsemi.com 74F823 Absolute Maximum Ratings(Note 1) 74F823 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°V to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 100 160 tPLH Propagation Delay 2.0 5.6 9.5 2.0 10.5 2.0 10.5 tPHL CP to On 2.0 5.2 9.5 2.0 10.5 2.0 10.5 tPHL Propagation Delay 4.0 7.1 12.0 4.0 13.0 4.0 13.0 CLR to On Max Min Max 60 Min Max 70 MHz tPZH Output Enable Time 2.0 5.8 10.5 2.0 13.0 2.0 11.5 tPZL OE to On 2.0 5.5 10.5 2.0 13.0 2.0 11.5 tPHZ Output Disable Time 1.5 2.9 7.0 1.0 7.5 1.5 7.5 OE to On 1.5 2.7 7.0 1.0 7.5 1.5 7.5 tPLZ Units ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°V to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 2.5 4.0 tS(L) Dn to CP 2.5 4.0 3.0 tH(H) Hold Time, HIGH or LOW 2.5 2.5 2.5 Units Max 3.0 tH(L) Dn to CP 2.5 2.5 2.5 tS(H) Setup Time, HIGH or LOW 4.5 5.0 5.0 tS(L) EN to CP 2.5 3.0 3.0 tH(H) Hold Time, HIGH or LOW 2.0 3.0 2.0 ns ns tH(L) EN to CP 0 1.0 0 tW(H) CP Pulse Width 5.0 6.0 6.0 tW(L) HIGH or LOW 5.0 6.0 6.0 tW(L) CLR Pulse Width, LOW 5.0 5.0 5.0 ns tREC CLR Recovery Time 5.0 5.0 5.0 ns www.fairchildsemi.com 4 ns 74F823 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74F823 9-Bit D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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