SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS299A – JANUARY 1993 – REVISED JULY 1995 D D D D D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages DB, DW, OR PW PACKAGE (TOP VIEW) LEBA OEBA A1 A2 A3 A4 A5 A6 A7 A8 CEAB GND description 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CEBA B1 B2 B3 B4 B5 B6 B7 B8 LEAB OEAB This octal registered transceiver is designed for 2.7-V to 3.6-V VCC operation. The SN74LVC543 contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB places the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow for B to A is similar to that of A to B but uses CEBA, LEBA, and OEBA. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVC543 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE† INPUTS OEAB A OUTPUT B X X X Z X H X Z L H L X L L L L B0‡ L CEAB LEAB H X L L L H H † A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. ‡ Output level before the indicated steady-state input conditions were established Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS299A – JANUARY 1993 – REVISED JULY 1995 logic symbol† 2 1EN3 OEBA 23 CEBA 1 1C5 LEBA 13 OEAB 11 CEAB 14 LEAB A1 A2 A3 A4 A5 A6 A7 A8 G1 2EN4 G2 2C6 3 4 3 1 5D 6D 1 4 22 21 5 20 6 19 7 18 8 17 9 16 10 15 B1 B2 B3 B4 B5 B6 B7 B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OEBA CEBA LEBA OEAB CEAB LEAB A1 2 23 1 13 11 14 C1 3 1D C1 1D To Seven Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 22 B1 SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS299A – JANUARY 1993 – REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . 1.7 W PW package . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) VCC VIH Supply voltage VIL Low-level input voltage High-level input voltage VI Input voltage VO Output voltage MIN MAX 2.7 3.6 VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 2 Control inputs 0 5.5 Data inputs 0 VCC VCC IOH High level output current High-level IOL Low level output current Low-level VCC = 2.7 V VCC = 3 V ∆t /∆v Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V 0.8 0 VCC = 2.7 V VCC = 3 V UNIT – 12 12 – 24 24 V V V mA mA 0 10 ns / V – 40 85 °C 3 SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS299A – JANUARY 1993 – REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCC† MIN to MAX TEST CONDITIONS IOH = – 100 µA IOH = – 24 mA IOL = 100 µA TYP‡ MAX VCC – 0.2 2.2 2.7 V IOH = – 12 mA VOH MIN 3V 2.4 3V 2.2 UNIT V MIN to MAX 0.2 VOL IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 II VI = 5.5 V or GND 3.6 V ±5 µA IOZ§ ICC VO = VCC or GND 3.6 V ± 10 µA 20 µA 500 µA VI = VCC or GND, One input at VCC – 0.6 V, nICC IO = 0 Other inputs at VCC or GND 3.6 V 3 V to 3.6 V Ci Control inputs VI = VCC or GND 3.3 V Cio A or B ports VO = VCC or GND 3.3 V † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. ‡ All typical values are at VCC = 3.3 V, TA = 25°C. § For I/O ports, the parameter IOZ includes the input leakage current. V 4.6 pF 7.2 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC = 3.3 V ± 0.3 V MIN tw tsu Pulse duration th MAX VCC = 2.7 V MIN UNIT MAX 4 4 ns Setup time, data before LE↑ or CE↑ 1.5 1.5 ns Hold time, data after LE↑ or CE↑ 2.5 2.5 ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd d ten tdis di 4 FROM (INPUT) A or B TO (OUTPUT) B or A LE OE A or B CE OE A or B CE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX MIN 1.5 8 9 1.5 9.5 10.5 1.5 8.5 9.5 1.5 9 10 1.5 8.5 9.5 1.5 9 10 UNIT MAX ns ns ns SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS299A – JANUARY 1993 – REVISED JULY 1995 operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd d TEST CONDITIONS Outputs enabled Power dissipation capacitance per transceiver Outputs disabled pF CL = 50 pF, TYP 32 f = 10 MHz 4.6 UNIT pF PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V 1.5 V Input th 2.7 V 1.5 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 0V tPLH 1.5 V tPLH VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 6 V (see Note B) VOH VOL tPHL 1.5 V tPZL tPHL 1.5 V Output 2.7 V Output Control 1.5 V Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. 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