Revised January 1999 74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs General Description Features The ABT16543 16-bit transceiver contains two sets of Dtype latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Each byte has separate control inputs, which can be shorted together for full 16-bit operation. ■ Back-to-back registers for storage ■ Bidirectional data path ■ A and B outputs have current sourcing capability of 32 mA and current sinking capability of 64 mA ■ Separate control logic for each byte ■ 16-bit version of the ABT543 ■ Separate controls for data flow in each direction ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Nondestructive hot insertion capability Ordering Code: Order Number Package Number 74ABT16543CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Description 74ABT16543CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Assignment for SSOP and TSSOP Pin Names Description OEABn A-to-B Output Enable Input (Active LOW) OEBAn B-to-A Output Enable Input (Active LOW) CEABn A-to-B Enable Input (Active LOW) CEBAn B-to-A Enable Input (Active LOW) LEABn A-to-B Latch Enable Input (Active LOW) LEBAn B-to-A Latch Enable Input (Active LOW) A0–A15 A-to-B Data Inputs or B-to-A 3-STATE Outputs B0–B15 B-to-A Data Inputs or A-to-B 3-STATE Outputs © 1999 Fairchild Semiconductor Corporation DS011646.prf www.fairchildsemi.com 74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs October 1993 74ABT16543 Logic Symbol Data I/O Control Table Inputs Latch Status Output Buffers CEABn LEABn OEABn (Byte n) (Byte n) HIGH Z H X X Latched X H X Latched — L L X Transparent — X X H — HIGH Z L X L — Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn Functional Description mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Each byte has separate control inputs, allowing the device to be used as two 8-bit transceivers or as one 16-bit transceiver. The ABT16543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB) input must be low in order to enter data from the A port or take data from the B-Port as indicated in the Data I/O Control Table. With CEAB low, a low signal on (LEAB) input makes the A to B latches transparent; a subsequent low to high transition of the LEAB line puts the A latches in the storage Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C Over Voltage Latchup (I/O) −0.5V to +7.0V Free Air Ambient Temperature Input Voltage (Note 2) −0.5V to +7.0V Supply Voltage Input Current (Note 2) −30 mA to +5.0 mA in the Disable or −0.5V to +5.5V Data Input 50 mV/ns Enable Input 20 mV/ns 100 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) in LOW State (Max) +4.5V to +5.5V Clock Input −0.5V to VCC in the HIGH State −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) Voltage Applied to Any Output Power-Off State 10V Recommended Operating Conditions VCC Pin Potential to Ground Pin −500 mA DC Latchup Source Current DC Electrical Characteristics Symbol Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VID Input Leakage Test Typ VCC Max Units V Recognized HIGH Signal 0.8 V Recognized LOW Signal −1.2 V 2.0 Min Conditions IIN = −18 mA (Non I/O Pins) 2.5 IOH = −3 mA, (An, Bn) 2.0 IOH = −32 mA, (An, Bn) 0.55 4.75 V Min V 0.0 IOL = 64 mA, (A n, Bn) IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded IIH µA Max VIN = 2.7V (Non-I/O Pins) ((Note 3) 7 µA Max VIN = 7.0V (Non-I/O Pins) 100 µA Max VIN = 5.5V (An, Bn) −1 µA Max VIN = 0.5V (Non-I/O Pins) (Note 3) Input HIGH Current 1 VIN = VCC (Non-I/O Pins) 1 IBVI IBVIT Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) IIL Input LOW Current −1 VIN = 0.0V (Non-I/O Pins) IIH + IOZH Output Leakage Current 10 µA 0V–5.5V VOUT = 2.7V (An, Bn); IIL + IOZL Output Leakage Current −10 µA 0V–5.5V VOUT = 0.5V (An, Bn); IOS Output Short-Circuit Current −275 mA Max VOUT = 0V (An, Bn) ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC (An, Bn) IZZ Bus Drainage Test 100 µA 0.0V VOUT = 5.5V (An, Bn); All Others GND ICCH Power Supply Current 1.0 mA Max All Outputs HIGH ICCL Power Supply Current 60 mA Max All Outputs LOW ICCZ Power Supply Current 1.0 mA Max Outputs 3-STATE ICCT Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V ICCD Dynamic ICC OEAB or CEAB = 2V OEAB or CEAB = 2V −100 All Others at VCC or GND All Others at VCC or GND (Note 3) Outputs Open, CEAB, OEAB, LEAB = GND, No Load 0.25 mA/MHz Max CEBA = VCC, One Bit Toggling, 50% Duty Cycle Note 3: Guaranteed but not tested. 3 www.fairchildsemi.com 74ABT16543 Absolute Maximum Ratings(Note 1) 74ABT16543 AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay tPHL An to Bn or Bn to An tPLH Propagation Delay tPHL LEABn to Bn, LEBAn to An tPZH Enable Time tPZL OEBAn or OEABn to An or Bn tPHZ Disable Time tPLZ OEABn or OEBAn to An or Bn tPZH Enable Time tPZL CEBAn or CEABn to An or Bn tPHZ Disable Time tPLZ CEBAn or CEABn to An or Bn TA = +25°C TA = −55°C to +85°C VCC = +5.0V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Units Min Typ Max Min Max 1.5 3.0 5.7 1.5 5.7 ns 1.5 3.0 5.5 1.5 5.5 ns 1.5 2.8 5.2 1.5 5.2 ns 1.6 3.1 6.0 1.6 6.0 ns 1.5 3.1 6.2 1.5 6.2 ns 1.7 3.2 6.3 1.7 6.3 ns AC Operating Requirements (SSOP Package) Symbol Parameter TA = +25°C TA = −55°C to +85°C VCC = +5.0V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Max Min tS(H) Setup Time, HIGH or LOW 2.0 2.0 tS(L) An or Bn to LEBAn or LEABn 2.0 2.0 tH(H) Hold Time, HIGH or LOW 1.0 1.0 tH(L) An or Bn to LEBAn or LEABn 1.0 1.0 tW(L) Pulse Width, LOW 3.0 3.0 Max ns ns ns Capacitance Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Capacitance 5.0 pF VCC = 0V (non I/O pins) CI/O (Note 4) Output Capacitance 11.0 pF VCC = 5.0V (An, Bn) Note 4: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 Units 74ABT16543 AC Loading *Includes jig and probe capacitance FIGURE 2. VM = 1.5V FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude Rep. Rate tW tr tf 3V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.fairchildsemi.com 74ABT16543 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A www.fairchildsemi.com 6 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)