Revised November 1999 74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs General Description Features The ABT16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in high Z state. ■ Separate control logic for each byte ■ 16-bit version of the ABT373 ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Non-destructive hot insertion capability ■ Guaranteed latch-up protection Ordering Code: Order Number Package Number 74ABT16373CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Description 74ABT16373CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description OEn Output Enable Input (Active LOW) LEn Latch Enable Input D0–D15 Data Inputs O0–O15 Outputs © 1999 Fairchild Semiconductor Corporation DS011666 www.fairchildsemi.com 74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs March 1994 74ABT16373 Functional Description Truth Tables The ABT16373 contains sixteen D-type latches with 3STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Outputs LE1 OE1 D0–D7 O0–O7 Z X H X H L L L H L H H L L X (Previous) LE2 OE2 D8–D15 O8–O15 Z Inputs Outputs X H X H L L L H L H H L L X (Previous) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Previous = previous output prior to HIGH-to-LOW transition of LE Logic Diagrams www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Voltage Applied to Any Output in the Disabled or −0.5V to +5.5V Power-Off State −0.5V to VCC in the HIGH State Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Latchup Source Current: OE Pin −350 mA (Across Comm Operating Range) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −500 mA Other Pins Over Voltage Latchup (I/O) 10V Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH Voltage VOL Output LOW Voltage 0.55 IIH Input HIGH Current 1 V 2.5 1 IBVI Input HIGH Current Breakdown Test 7 IIL Input LOW Current −1 −1 Input Leakage Test 4.75 IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current ICEX V Conditions Recognized HIGH Signal Recognized LOW Signal Min Min 2.0 VID VCC Min µA Max µA Max µA Max V 0.0 IIN = −18 mA IOH = −3 mA IOH = −32 mA IOL = 64 mA VIN = 2.7V (Note 3) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 3) VIN = 0.0V IID = 1.9 µA All Other Pins Grounded 10 µA 0 − 5.5V VOUT = 2.7V; OE = 2.0V 0 − 5.5V VOUT = 0.5V; OE = 2.0V −10 µA −275 mA Max VOUT = 0.0V Output HIGH Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND ICCH Power Supply Current 2.0 mA Max All Outputs HIGH ICCL Power Supply Current 62 mA Max All Outputs LOW ICCZ Power Supply Current 2.0 mA Max OE = V CC ICCT Additional ICC/Input 2.5 mA −100 All Others at VCC or GND Outputs Enabled Outputs 3-STATE 2.5 mA Outputs 3-STATE 2.5 mA VI = VCC − 2.1V Max Enable Input VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ (Note 3) 0.15 MHz Max Outputs Open, LE = VCC OE = GND, (Note 4) One Bit Toggling, 50% Duty Cycle Note 3: Guaranteed, but not tested. Note 4: For 8 bits toggling, ICCD < 0.8 mA/MHz. 3 www.fairchildsemi.com 74ABT16373 Absolute Maximum Ratings(Note 1) 74ABT16373 AC Electrical Characteristics (SOIC and SSOP Packages) Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF Max Min tPLH Propagation Delay Min 1.4 5.6 1.4 5.6 tPHL Dn to On 1.4 5.6 1.4 5.6 tPLH Propagation Delay 1.7 6.0 1.7 6.0 tPHL LE to On 1.7 5.5 1.7 5.5 tPZH Output Enable Time 1.1 6.1 1.1 6.1 1.5 5.6 1.5 5.6 2.4 7.1 2.4 7.1 1.6 6.5 1.6 6.5 tPZL Output Disable Time tPHZ tPLZ Typ Units Max ns ns ns ns AC Operating Requirements (SOIC and SSOP Packages) Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF Min Typ Max Min fTOGGLE Maximum Toggle Frequency tS(H) Setup Time, HIGH 1.5 1.5 tS(L) or LOW Dn to LE 1.5 1.5 Max 100 MHz tH(H) Hold Time, HIGH 1.0 1.0 tH(L) or LOW Dn to LE 1.0 1.0 tW(H) Pulse Width, 3.0 3.0 LE HIGH ns ns ns Capacitance Symbol Parameter Typ Units Conditions (TA = 25°C) CIN Input Capacitance 5 pF VCC = 0V COUT (Note 5) Output Capacitance 11 pF VCC = 5.0V Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 Units 74ABT16373 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS48A 5 www.fairchildsemi.com 74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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