TI 6PAIC23BIPWRG4Q1

TLV320AIC23B-Q1
Stereo Audio Codec, 8- to 96-kHz, With Integrated
Headphone Amplifier
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SGLS240C
March 2004 – Revised June 2012
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
Stereo Audio Codec, 8- to 96-kHz, With Integrated Headphone
Amplifier
Check for Samples: TLV320AIC23B-Q1
1
1 Introduction
1.1
Features
1
• Qualified for Automotive Applications
• High-Performance Stereo Codec
– 90-dB SNR Multibit Sigma-Delta ADC (Aweighted at 48 kHz)
– 100-dB SNR Multibit Sigma-Delta DAC (Aweighted at 48 kHz)
– 1.42 V – 3.6 V Core Digital Supply:
Compatible With TI C54x DSP Core Voltages
– 2.7 V – 3.6 V Buffer and Analog Supply:
Compatible Both TI C54x DSP Buffer
Voltages
– 8-kHz – 96-kHz Sampling-Frequency Support
• Software Control Via TI McBSP-Compatible
Multiprotocol Serial Port
– 2-wire-Compatible and SPI-Compatible
Serial-Port Protocols
– Glueless Interface to TI McBSPs
• Audio-Data Input/Output Via TI McBSPCompatible Programmable Audio Interface
– I2S-Compatible Interface Requiring Only One
McBSP for both ADC and DAC
– Standard I2S, MSB, or LSB Justified-Data
Transfers
– 16/20/24/32-Bit Word Lengths
– Audio Master/Slave Timing Capability
Optimized for TI DSPs (250/272 fs), USB
mode
– Industry-Standard Master/Slave Support
Provided Also (256/384 fs), Normal mode
– Glueless Interface to TI McBSPs
• Integrated Total Electret-Microphone Biasing
and Buffering Solution
– Low-Noise MICBIAS pin at 3/4 AVDD for
Biasing of Electret Capsules
– Integrated Buffer Amplifier With Tunable
Fixed Gain of 1 to 5
– Additional Control-Register Selectable Buffer
Gain of 0 dB or 20 dB
• Stereo-Line Inputs
– Integrated Programmable Gain Amplifier
– Analog Bypass Path of Codec
• ADC Multiplexed Input for Stereo-Line Inputs
and Microphone
• Stereo-Line Outputs
– Analog Stereo Mixer for DAC and Analog
Bypass Path
• Volume Control With Mute on Input and Output
• Highly Efficient Linear Headphone Amplifier
– 30 mW into 32 Ω From a 3.3-V Analog Supply
Voltage
• Flexible Power Management Under Total
Software Control
– 23-mW Power Consumption During Playback
Mode
– Standby Power Consumption < 150 µW
– Power-Down Power Consumption < 15 µW
• 28-Pin TSSOP (62 mm2 Total Board Area)
• Ideally Suitable for Portable Solid-State Audio
Players and Recorders
1.2
Description
1
The TLV320AIC23B-Q1 is a high-performance stereo audio codec with highly integrated analog
functionality. The analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) within the
TLV320AIC23B-Q1 use multibit sigma-delta technology with integrated oversampling digital interpolation
filters. Data-transfer word lengths of 16, 20, 24, and 32 bits, with sample rates from 8 kHz to 96 kHz, are
supported. The ADC sigma-delta modulator features third-order multibit architecture with up to 90-dBA
signal-to-noise ratio (SNR) at audio sampling rates up to 96 kHz, enabling high-fidelity audio recording in a
compact, power-saving design. The DAC sigma-delta modulator features a second-order multibit
architecture with up to 100-dBA SNR at audio sampling rates up to 96 kHz, enabling high-quality digital
audio-playback capability, while consuming less than 23 mW during playback only. The TLV320AIC23BQ1 is the ideal analog input/output (I/O) choice for portable digital audio-player and recorder applications,
such as MP3 digital audio players.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2004–2012, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
Integrated analog features consist of stereo-line inputs with an analog bypass path, a stereo headphone
amplifier, with analog volume control and mute, and a complete electret-microphone-capsule biasing and
buffering solution. The headphone amplifier is capable of delivering 30 mW per channel into 32 Ω. The
analog bypass path allows use of the stereo-line inputs and the headphone amplifier with analog volume
control, while completely bypassing the codec, thus enabling further design flexibility, such as integrated
FM tuners. A microphone bias-voltage output provides a low-noise current source for electret-capsule
biasing. The AIC23B has an integrated adjustable microphone amplifier (gain adjustable from 1 to 5) and
a programmable gain microphone amplifier (0 dB or 20 dB). The microphone signal can be mixed with the
output signals if a sidetone is required.
While the TLV320AIC23B-Q1 supports the industry-standard oversampling rates of 256 fs and 384 fs,
unique oversampling rates of 250 fs and 272 fs are provided, which optimize interface considerations in
designs using TI C54x digital signal processors (DSPs) and universal serial bus (USB) data interfaces. A
single 12-MHz crystal can supply clocking to the DSP, USB, and codec. The TLV320AIC23B-Q1 features
an internal oscillator that, when connected to a 12-MHz external crystal, provides a system clock to the
DSP and other peripherals at either 12 MHz or 6 MHz, using an internal clock buffer and selectable
divider. Audio sample rates of 48 kHz and compact-disc (CD) standard 44.1 kHz are supported directly
from a 12-MHz master clock with 250 fs and 272 fs oversampling rates.
Low power consumption and flexible power management allow selective shutdown of codec functions,
thus extending battery life in portable applications. This design solution makes powerful portable stereo
audio designs easily realizable in a cost-effective, space-saving total analog I/O solution: the
TLV320AIC23B-Q1.
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
1 Introduction
3
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
1.3
www.ti.com
Functional Block Diagram
VADC
AVDD
1.0X
50 kΩ
DSPcodec
TLV320AIC23B
VDAC
VMID
1.0X
VMID
50 kΩ
1.0X
AGND
CS
Control
Interface
1.5X
MICBIAS
SDIN
SCLK
MODE
12 to –34.5 dB,
1.5-dB Steps
Line
Mute
RLINEIN
Bypass
Mute
50 kΩ
Σ−∆
ADC
2:1
MUX
Mute,
0 dB, 20 dB
10 kΩ
VADC
MICIN
VMID
12 to –34 dB,
1.5-dB Steps
HPVDD
HPGND
Headphone
Driver
Σ−∆
ADC
2:1
MUX
Line
Mute
LLINEIN
Sidetone
Mute
6 to –73 dB,
1-dB Steps
DVDD
Digital
Filters
BVDD
DGND
Bypass
Mute
Σ−∆
DAC
Σ
RHPOUT
ROUT
VDAC
LOUT
Σ
LHPOUT
Headphone
Driver
Σ−∆
DAC
6 to –73 dB,
1-dB Steps
CLKIN
Divider
(1x, ½x)
LRCIN
XTI/MCLK
OSC
XTO
DIN
CLKOUT
Divider
(1x, ½x)
Digital
Audio
Interface
CLKOUT
LRCOUT
DOUT
BCLK
NOTE: MCLK, BCLK, and SCLK are all asynchronous to each other.
B0486-01
4
1 Introduction
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
1.4
SGLS240C – MARCH 2004 – REVISED JUNE 2012
Pin Assignments
PW Package
(Top View)
BVDD
1
28
DGND
CLKOUT
2
27
DVDD
BCLK
3
26
XTO
DIN
4
25
XTI/MCLK
LRCIN
5
24
SCLK
DOUT
6
23
SDIN
LRCOUT
7
22
MODE
HPVDD
8
21
CS
LHPOUT
9
20
LLINEIN
RHPOUT
10
19
RLINEIN
HPGND
11
18
MICIN
LOUT
12
17
MICBIAS
ROUT
13
16
VMID
AVDD
14
15
AGND
P0043-05
1.5
Ordering Information
TA
PACKAGE
REEL
ORDERABLE PART NUMBER
TOP-SIDE MARKING
−40°C to 85°C
TSSOP
2000
TLV320AIC23BIPWRQ1
AIC23BIQ1
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
1 Introduction
5
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
1.6
www.ti.com
Pin Functions
Table 1-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
AGND
15
Analog supply return
AVDD
14
Analog supply input. Voltage level is 3.3 V nominal.
BCLK
3
BVDD
1
CLKOUT
2
O
Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X frequencies of
XTI. Bit 07 in the sample rate control register controls frequency selection.
CS
21
I
Control port input latch/address select. For SPI control mode this input acts as the data latch control.
For 2-wire control mode this input defines the seventh bit in the device address field. See Section 3.1 for
details.
DIN
4
I
I2S format serial data input to the sigma-delta stereo DAC
DGND
28
DOUT
6
DVDD
27
Digital supply input. Voltage range is 1.4 V to 3.6 V.
HPGND
11
Analog headphone amplifier supply return
HPVDD
8
Analog headphone amplifier supply input. Voltage level is 3.3 V nominal.
LHPOUT
9
O
Left stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of
–73 dB to 6 dB is provided in 1-dB steps.
LLINEIN
20
I
Left stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is
provided in 1.5-dB steps.
LOUT
12
O
Left stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
LRCIN
5
I/O
I2S DAC-word clock signal. In audio master mode, the AIC23B generates this framing signal and sends
it to the DSP. In audio slave mode, the signal is generated by the DSP.
LRCOUT
7
I/O
I2S ADC-word clock signal. In audio master mode, the AIC23B generates this framing signal and sends
it to the DSP. In audio slave mode, the signal is generated by the DSP.
MICBIAS
17
O
Buffered low-noise-voltage output suitable for electret-microphone-capsule biasing. Voltage level is 3/4
AVDD nominal.
MICIN
18
I
Buffered amplifier input suitable for use with electret-microphone capsules. Without external resistors a
default gain of 5 is provided. See Section 2.3.1.2 for details.
MODE
22
I
Serial-interface-mode input. See Section 3.1 for details.
I/O
I2S serial-bit clock. In audio master mode, the AIC23B generates this signal and sends it to the DSP. In
audio slave mode, the signal is generated by the DSP.
Buffer supply input. Voltage range is from 2.7 V to 3.6 V.
Digital supply return
O
NC
I2S format serial data output from the sigma-delta stereo ADC
Not Used—No internal connection
RHPOUT
10
O
Right stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of
−73 dB to 6 dB is provided in 1-dB steps.
RLINEIN
19
I
Right stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is
provided in 1.5-dB steps.
ROUT
13
O
Right stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
SCLK
24
I
Control-port serial-data clock. For SPI and 2-wire control modes this is the serial-clock input. See
Section 3.1 for details.
SDIN
23
I
Control-port serial-data input. For SPI and 2-wire control modes this is the serial-data input and also is
used to select the control protocol after reset. See Section 3.1 for details.
VMID
16
I
Midrail voltage decoupling input. 10-μF and 0.1-μF capacitors should be connected in parallel to this
terminal for noise filtering. Voltage level is 1/2 AVDD nominal.
XTI/MCLK
25
I
Crystal or external-clock input. Used for derivation of all internal clocks on the AIC23B.
XTO
26
O
Crystal output. Connect to external crystal for applications where the AIC23B is the audio timing master.
Not used in applications where external clock source is used.
6
1 Introduction
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
2
Electrical Specifications
2.1
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
–0.3 to 3.63
V
–0.3 to 3 .63
V
Digital
–0.3 to DVDD
V
Analog
–0.3 to AVDD
V
240
°C
Operating free-air temperature range: Industrial, TA
–40 to 85
°C
Storage temperature range, Tstg
–65 to 150
°C
AVDD to AGND, DVDD to DGND,
BVDD to DGND, HPVDD to HPGND
Supply voltage range (2)
Analog supply return to digital supply return AGND to DGND
Input voltage range, all input signals
Case temperature for 10 seconds
(1)
(2)
2.2
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DVDD may not exceed BVDD 0.3 V; BVDD may not exceed AVDD 0.3 V or HPVDD 0.3.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Analog supply voltage, AVDD, HPVDD
Digital buffer supply voltage, BVDD
(1)
(1)
Digital core supply voltage, DVDD (1)
MIN
NOM
MAX
2.7
3.3
3.6
V
2.7
3.3
3.6
V
1.42
1.5
3.6
V
Analog input voltage, full scale − 0 dB (AVDD = 3.3 V)
Stereo-line output load resistance
Headphone-amplifier output load resistance
1
UNIT
VRMS
10
kΩ
0
Ω
CLKOUT digital output load capacitance
20
pF
All other digital output load capacitance
10
pF
Stereo-line output load capacitance
50
XTI master clock Input
ADC or DAC conversion rate
Operating free-air temperature, TA
(1)
Industrial
–40
pF
18.43
MHz
96
kHz
85
°C
Digital voltage values are with respect to DGND; analog voltage values are with respect to AGND.
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
Electrical Specifications
7
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
2.3
www.ti.com
Electrical Characteristics
over recommended operating conditions, AVDD, HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, slave mode, XTI/MCLK = 256 fs, fs = 48
kHz (unless otherwise stated)
2.3.1
ADC
2.3.1.1
Line Input to ADC
PARAMETER
TEST CONDITIONS
MIN
Input signal level (0 dB)
Signal-to-noise ratio, A-weighted, 0-dB gain
TYP
fs = 48 kHz (3.3 V)
(1) (2)
85
fs = 48 kHz (2.7 V)
Dynamic range, A-weighted, –60-dB full-scale input
(2)
85
90
90
AVDD = 3.3 V
–80
AVDD = 2.7 V
80
Power supply rejection ratio
1 kHz, 100 mVpp
50
ADC channel separation
1 kHz input tone
Programmable gain
1 kHz input tone, RSOURCE < 50 Ω
Programmable gain step size
Monotonic
Mute attenuation
0 dB, 1 kHz input tone
Total harmonic distortion, –1-dB input, 0-dB gain
Input resistance
dB
dB
dB
90
–34.5
dB
12
1.5
10
0 dB input gain
28
dB
dB
80
12 dB input gain
Input capacitance
(2)
dB
90
AVDD = 3.3 V
UNIT
VRMS
90
AVDD = 2.7 V
(1)
MAX
1
dB
20
35
10
kΩ
pF
Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to
20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in
higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
2.3.1.2
Microphone Input to ADC
0-dB Gain, fs = 8 kHz (40-KΩ source impedance, see Section 1.3)
PARAMETER
TEST CONDITIONS
MIN
Input signal level (0 dB)
1
AVDD = 3.3 V
Signal-to-noise ratio, A-weighted, 0-dB gain (1) (2)
77
AVDD = 2.7 V
Dynamic range, A-weighted, –60-dB full-scale input (2)
Total harmonic distortion, –1-dB input, 0-dB gain
TYP
85
84
AVDD = 3.3 V
77
85
AVDD = 2.7 V
84
AVDD = 3.3 V
–60
AVDD = 2.7 V
–60
MAX
UNIT
VRMS
dB
dB
dB
Power supply rejection ratio
1 kHz, 100 mVpp
50
dB
Programmable gain boost
1 kHz input tone, RSOURCE < 50 Ω
20
dB
Microphone-path gain
MICBOOST = 0, RSOURCE < 50 Ω
14
dB
Mute attenuation
0 dB, 1 kHz input tone
Input resistance
Input capacitance
(1)
(2)
8
60
80
dB
8
14
kΩ
10
pF
Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to
20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in
higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
Electrical Specifications
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
2.3.1.3
SGLS240C – MARCH 2004 – REVISED JUNE 2012
Microphone Bias
PARAMETER
TEST CONDITIONS
Bias voltage
MIN
TYP
MAX
3/4 AVDD − 100 m
3/4 AVDD
3/4 AVDD + 100 m
Bias-current source
Output noise voltage
2.3.2
UNIT
V
3
1 kHz to 20 kHz
mA
25
nV/√Hz
DAC
Line output, load = 10 kΩ, 50 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
90
100
0-dB full-scale output voltage (FFFFFF)
AVDD = 3.3 V
fs = 48kHz
AVDD = 2.7 V
fs = 48 kHz
85
AVDD = 2.7 V
AVDD = 3.3 V
Total harmonic distortion
AVDD = 2.7 V
Power supply rejection ratio
dB
90
dB
TBD
1 kHz, 0 dB
–88
–80
1 kHz, –3 dB
–92
–86
1 kHz, 0 dB
–85
1 kHz, –3 dB
–88
1 kHz, 100 mVpp
DAC channel separation
(3)
VRMS
100
AVDD = 3.3 V
Dynamic range, A-weighted (2)
(2)
UNIT
1
Signal-to-noise ratio, A-weighted, 0-dB gain (1) (2) (3)
(1)
MAX
dB
dB
50
dB
100
dB
Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to
20-kHz bandwidth using an audio analyzer
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in
higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
Ratio of output level with 1-kHz full-scale input, to the output level with all zeros into the digital input, measured A-weighted over a 20-Hz
to 20-kHz bandwidth.
2.3.3
Analog Line Input to Line Output (Bypass)
PARAMETER
TEST CONDITIONS
MIN
0-dB full-scale output voltage
TYP
MAX
1
AVDD = 3.3 V
Signal-to-noise ratio, A-weighted, 0-dB gain (1) (2)
90
AVDD = 2.7 V
AVDD = 3.3 V
Total harmonic distortion
AVDD = 2.7 V
UNIT
VRMS
95
dB
95
1 kHz, 0 dB
–86
–80
1 kHz, –3 dB
–92
–86
1 kHz, 0 dB
–86
1 kHz, –3 dB
–92
dB
dB
Power supply rejection ratio
1 kHz, 100 mVpp
50
dB
DAC channel separation (left to right)
1 kHz, 0 dB
80
dB
(1)
(2)
Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to
20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in
higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
Electrical Specifications
9
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
2.3.4
www.ti.com
Stereo Headphone Output
PARAMETER
TEST CONDITIONS
MIN
TYP
0-dB full-scale output voltage
Maximum output power, PO
Signal-to-noise ratio, A-weighted
(1)
RL = 32 Ω
30
RL = 16 Ω
40
AVDD = 3.3 V
Total harmonic distortion
AVDD = 3.3 V,
1 kHz output
Power supply rejection ratio
1 kHz, 100 mVpp
Programmable gain
1 kHz output
88
Mute attenuation
dB
0.1
PO = 20 mW
1
50
%
dB
−73
6
dB
1
dB
80
dB
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in
higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
2.3.5
Analog Reference Levels
PARAMETER
MIN
Reference voltage
AVDD/2 − 50 mV
Divider resistance
40
2.3.6
PARAMETER
Input low level
VIH
Input high level
VOL
Output low level
VOH
Output high level
2.3.7
60
kΩ
TYP
MAX
UNIT
V
V
V
0.9 × BVDD
V
Supply Current
MIN
TYP
MAX
Record and playback (all active)
TEST CONDITIONS
20
24
26
Record and playback (osc, clk, and MIC output powered down)
16
18
20
Oscillator enabled
6
7.5
9
11
13.5
15
4
4.5
6
1.5
3
0.8
Oscillator disabled
UNIT
mA
0.01
Digital-Interface Timing
System-clock pulse duration, MCLK/XTI
MIN
High
18
Low
18
System-clock period, MCLK/XTI
Propagation delay, CLKOUT
Electrical Specifications
TYP
MAX
UNIT
ns
54
Duty cycle, MCLK/XTI
tpd(1)
V
0.1 × BVDD
PARAMETER
tc(1)
UNIT
0.7 × BVDD
Power down, DVDD = 1.5 V,
AVDD
= BVDD = HPVDD = 3.3 V
tw(2)
50
MIN
Line playback only
Total supply current, Record only
No input signal ITOT
Analog bypass (line in to line out)
tw(1)
MAX
AVDD/2 + 50 mV
0.3 × BVDD
PARAMETER
2.4
TYP
Digital I/O
VIL
10
mW
PO = 10 mW
1 kHz output
UNIT
VRMS
97
Programmable-gain step size
(1)
MAX
1
ns
40/60
60/40
%
0
10
ns
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
tc(1)
tw(1)
tw(2)
MCLK/XTI
tpd(1)
CLKOUT
CLKOUT
(Div 2)
T0547-01
Figure 2-1. System-Clock Timing Requirements
2.4.1
Audio Interface (Master Mode)
PARAMETER
MIN
TYP
MAX UNIT
tpd(2)
Propagation delay, LRCIN/LRCOUT
0
10
ns
tpd(3)
Propagation delay, DOUT
0
10
ns
tsu(1)
Setup time, DIN
10
ns
th(1)
Hold time, DIN
10
ns
BCLK
tpd(2)
LRCIN
LRCOUT
tpd(3)
DOUT
DIN
tsu(1)
th(1)
T0548-01
Figure 2-2. Master-Mode Timing Requirements
2.4.2
Audio Interface (Slave-Mode)
PARAMETER
tw(3)
tw(4)
Pulse duration, BCLK
MIN
High
20
Low
20
TYP
MAX
UNIT
ns
tc(2)
Clock period, BCLK
tpd(4)
Propagation delay, DOUT
50
tsu(2)
Setup time, DIN
10
ns
th(2)
Hold time, DIN
10
ns
tsu(3)
Setup time, LRCIN
10
ns
th(3)
Hold time, LRCIN
10
ns
0
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
ns
10
Electrical Specifications
ns
11
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
www.ti.com
tc(2)
tw(4)
tw(3)
BCLK
LRCIN
LRCOUT
tsu(2)
th(3)
tsu(3)
DIN
tpd(2)
th(2)
DOUT
T0549-01
Figure 2-3. Slave-Mode Timing Requirements
2.4.3
3-Wire Control Interface (SDIN)
PARAMETER
tw(5)
tw(6)
Clock pulse duration, SCLK
MIN
High
20
Low
20
TYP
MAX
UNIT
ns
tc(3)
Clock period, SCLK
80
ns
tsu(4)
Clock rising edge to CS rising edge, SCLK
60
ns
tsu(5)
Setup time, SDIN to SCLK
20
ns
th(4)
Hold time, SCLK to SDIN
20
ns
tw(7)
tw(8)
Pulse duration, CS
High
20
Low
20
ns
tw(8)
CS
tc(3)
tw(5)
tsu(4)
tw(6)
SCLK
tsu(5)
DIN
th(4)
LSB
T0550-01
Figure 2-4. 3-Wire Control Interface Timing Requirements
12
Electrical Specifications
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
2.4.4
SGLS240C – MARCH 2004 – REVISED JUNE 2012
2-Wire Control Interface
PARAMETER
tw(9)
tw(10)
Clock pulse duration, SCLK
MIN
High
1.3
Low
600
TYP
MAX
UNIT
µs
ns
f(sf)
Clock frequency, SCLK
0
400
th(5)
Hold time (start condition)
600
tsu(6)
Setup time (start condition)
600
th(6)
Data hold time
tsu(7)
Data setup time
tr
Rise time, SDIN, SCLK
300
ns
tf
Fall time, SDIN, SCLK
300
ns
tsu(8)
Setup time (stop condition)
tsp
Pulse width of spikes suppressed by input filter
ns
ns
900
100
ns
0
tw(10)
ns
ns
600
tw(9)
kHz
50
ns
tsp
SCLK
th(5)
th(6)
tsu(7)
tsu(8)
DIN
T0551-01
Figure 2-5. 2-Wire Control Interface Timing Requirements
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
Electrical Specifications
13
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
www.ti.com
3
How to Use the TLV320AIC23B-Q1
3.1
Control Interfaces
The TLV320AIC23B-Q1 has many programmable features. The control interface is used to program the
registers of the device. The control interface complies with SPI (3-wire operation) and 2-wire operation
specifications. The state of the MODE terminal selects the control interface type. The MODE pin must be
hardwired to the required level.
3.1.1
MODE
INTERFACE
0
2-wire
1
SPI
SPI
In SPI mode, SDIN carries the serial data, SCLK is the serial clock and CS latches the data word into the
TLV320AIC23B-Q1. The interface is compatible with microcontrollers and DSPs with an SPI interface.
A control word consists of 16 bits, starting with the MSB. The data bits are latched on the rising edge of
SCLK. A rising edge on CS after the 16th rising clock edge latches the data word into the AIC (see
Figure 3-1).
The control word is divided into two parts. The first part is the address block, the second part is the data
block:
B[15:9]
Control Address Bits
B[8:0]
Control Data Bits
CS
SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
MSB
B1
B0
LSB
T0552-01
Figure 3-1. SPI Timing
3.1.2
2-Wire
In 2-wire mode, the data transfer uses SDIN for the serial data and SCLK for the serial clock. The start
condition is a falling edge on SDIN while SCLK is high. The seven bits following the start condition
determine which device on the 2-wire bus receives the data. R/W determines the direction of the data
transfer. The TLV320AIC23B-Q1 is a write only device and responds only if R/W is 0. The device operates
only as a slave device whose address is selected by setting the state of the CS pin as follows.
14
CS STATE
(Default = 0)
ADDRESS
0
0011010
1
0011011
How to Use the TLV320AIC23B-Q1
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
The device that recognizes the address responds by pulling SDIN low during the ninth clock cycle,
acknowledging the data transfer. The control follows in the next two eight-bit blocks. The stop condition
after the data transfer is a rising edge on SDIN when SCLK is high (see Figure 3-2).
The 16-bit control word is divided into two parts. The first part is the address block, the second part is the
data block:
B[15:9]
Control Address Bits
B[8:0]
Control Data Bits
Start
Stop
7
1
SCLK
ADDR
SDI
8
9
R/W
ACK
1
8
B15–B8
9
1
ACK
8
9
ACK
B7–B0
T0553-01
Figure 3-2. 2-Wire Compatible Timing
3.1.3
Register Map
The TLV320AIC23B-Q1 has the following set of registers, which are used to program the modes of
operation. To minimize corruption and potential noise injection due to improper sequencing, program the
registers while the device is powered down (Register 0x06, value 0x80). After the registers are
programmed, power on the device (Register 0x06, value 0x28).
ADDRESS
REGISTER
0000000
Left line input channel volume control
0000001
Right line input channel volume control
0000010
Left channel headphone volume control
0000011
Right channel headphone volume control
0000100
Analog audio path control
0000101
Digital audio path control
0000110
Power down control
0000111
Digital audio interface format
0001000
Sample rate control
0001001
Digital interface activation
0001111
Reset register
Table 3-1. Left Line Input Channel Volume Control (Address: 0000000)
BIT
Function
Default
LRS
LIM
LIV[4:0]
X
D8
LRS
0
D7
LIM
1
D6
X
0
D5
X
0
D4
LIV4
1
D3
LIV3
0
D2
LIV2
1
D1
LIV1
1
D0
LIV0
1
Left/right line simultaneous volume/mute update
Simultaneous update
0 = Disabled
1 = Enabled
Left line input mute
0 = Normal
1 = Muted
Left line input volume control (10111 = 0 dB default)
11111 = 12 dB down to 00000 = –34.5 dB in 1.5-dB steps
Reserved
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
How to Use the TLV320AIC23B-Q1
15
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
www.ti.com
Table 3-2. Right Line Input Channel Volume Control (Address: 0000001)
BIT
Function
Default
RLS
RIM
RIV[4:0]
X
D8
RLS
0
D7
RIM
1
D6
X
0
D5
X
0
D4
RIV4
1
D3
RIV3
0
D2
RIV2
1
D1
RIV1
1
D0
RIV0
1
Right/left line simultaneous volume/mute update
Simultaneous update
0 = Disabled
1 = Enabled
Right line input mute
0 = Normal
1 = Muted
Right line input volume control (10111 = 0 dB default)
11111 = 12 dB down to 00000 = –34.5 dB in 1.5-dB steps
Reserved
Table 3-3. Left Channel Headphone Volume Control (Address: 0000010)
BIT
Function
Default
LRS
D8
LRS
0
D7
LZC
1
D6
LHV6
1
D5
LHV5
1
D4
LHV4
1
D3
LHV3
1
D2
LHV2
0
D1
LHV1
0
D0
LHV0
1
Left/right headphone channel simultaneous volume/mute update
LZC
LHV[6:0]
Simultaneous update
0 = Disabled
1 = Enabled
Left channel zero-cross detect
Zero-cross detect
0 = Off
1 = On
Left Headphone volume control (1111001 = 0 dB default)
1111111 = 6 dB, 79 steps between 6 dB and −73 dB (mute), 0110000 = −73 dB (mute), anything below 0110000 does nothing −
you are still muted
Table 3-4. Right Channel Headphone Volume Control (Address: 0000011)
BIT
Function
Default
LRS
RZC
RHV[6:0]
16
D8
RLS
0
D7
RZC
1
D6
RHV6
1
D5
RHV5
1
D4
RHV4
1
D3
RHV3
1
D2
RHV2
0
D1
RHV1
0
D0
RHV0
1
Right/left headphone channel simultaneous volume/mute update
Simultaneous update
0 = Disabled
1 = Enabled
Right channel zero-cross detect
Zero-cross detect
0 = Off
1 = On
Right headphone volume control (1111001 = 0 dB default)
1111111 = 6 dB, 79 steps between 6 dB and −73 dB (mute), 0110000 = −73 dB (mute), any thing below 0110000 does
nothing − you are still muted
How to Use the TLV320AIC23B-Q1
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
Table 3-5. Analog Audio Path Control (Address: 0000100)
BIT
Function
Default
D8
STA2
0
STA[2:0] and STE
STE
1
1
1
1
1
0
DAC
BYP
INSEL
MICM
MICB
X
D7
STA1
0
D6
STA0
0
STA2
1
0
0
0
0
X
DAC select
Bypass
Input select for ADC
Microphone mute
Microphone boost
Reserved
D5
STE
0
STA1
X
0
0
1
1
X
0
0
0
0
0
STA0
X
0
1
0
1
X
D4
DAC
1
D3
BYP
1
D2
INSEL
0
D1
MICM
1
D0
MICB
0
D1
DEEMP0
0
D0
ADCHP
0
D1
MIC
1
D0
LINE
1
ADDED SIDETONE
0 dB
-6 dB
-9 dB
-12 dB
-18 dB
Disabled
= DAC off
= Disabled
= Line
= Normal
= dB
1
1
1
1
1
= DAC selected
= Enabled
= Microphone
= Muted
= 20 dB
Table 3-6. Digital Audio Path Control (Address: 0000101)
BIT
Function
Default
DACM
DEEMP[1:0]
ADCHP
X
D8
X
0
D7
X
0
D6
X
0
DAC soft mute
0 = Disabled
De-emphasis control 00 = Disabled
ADC high-pass filter 1 = Disabled
Reserved
D5
X
0
D4
X
0
D3
DACM
0
1 = Enabled
01 = 32 kHz
0 = Enabled
10 = 44.1 kHz
D2
DEEMP1
1
11 = 48 kHz
Table 3-7. Power Down Control (Address: 0000110)
BIT
Function
Default
OFF
CLK
OSC
OUT
DAC
ADC
MIC
LINE
X
D8
X
0
Device power
Clock
Oscillator
Outputs
DAC
ADC
Microphone input
Line input
Reserved
D7
OFF
0
0
0
0
0
0
0
0
0
= On
= On
= On
= On
= On
= On
= On
= On
D6
CLK
0
1
1
1
1
1
1
1
1
D5
OSC
0
D4
OUT
0
D3
DAC
0
D2
ADC
1
= Off
= Off
= Off
= Off
= Off
= Off
= Off
= Off
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
How to Use the TLV320AIC23B-Q1
17
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
www.ti.com
Table 3-8. Digital Audio Interface Format (Address: 0000111)
BIT
Function
Default
D8
X
0
MS
LRSWAP
LRP
Maser/slave mode
DAC left/right swap
DAC left/right phase
IWL[1:0]
FOR[1:0]
Input bit length
Data format
X
D7
X
0
D6
MS
0
D5
LRSWAP
0
D4
LRP
0
D3
IWL1
0
D2
IWL0
0
D1
FOR1
0
D0
FOR0
1
0 = Slave
1 = Master
0 = Disabled 1 = Enabled
0 = Right channel on, LRCIN high
1 = Right channel on, LRCIN low
DSP mode
1 = MSB is available on second BCLK rising edge after LRCIN rising edge
0 = MSB is available on first BCLK rising edge after LRCIN rising edge
00 = 16 bit
01 = 20 bit
10 = 24 bit
11 = 32 bit
11 = DSP format, frame sync followed by two data words
10 = I2S format, MSB first, left – 1 aligned
01 = MSB first, left aligned
00 = MSB first, right aligned
Reserved
NOTES:
1. In master mode, the TLV320AIC23B-Q1 supplies the BCLK, LRCOUT, and LRCIN. In slave mode, BCLK, LRCOUT, and
LRCIN are supplied to the TLV320AIC23B-Q1.
2. In normal mode, BCLK = MCLK/4 for all sample rates except for 88.2 kHz and 96 kHz. For 88.2 kHz and 96 kHz sample rate,
BCLK = MCLK.
3. In USB mode, bit BCLK = MCLK
Table 3-9. Sample Rate Control (Address: 0001000)
BIT
Function
D8
X
D7
CLKOUT
D6
CLKIN
D5
SR3
D4
SR2
D3
SR1
D2
SR0
D1
BOSR
Default
0
0
0
1
0
0
0
0
D0
USB/Norma
l
0
D1
X
0
D0
ACT
0
D1
RES
0
D0
RES
0
CLKIN
CLKOUT
SR[3:0]
BOSR
Clock input divider
0 = MCLK
1 = MCLK/2
Clock output divider
0 = MCLK
1 = MCLK/2
Sampling rate control (see Section 3.3.2.1 and Section 3.3.2.2)
Base oversampling rate
USB mode:
0 = 250 fs
1 = 272 fs
Normal mode:
0 = 256 fs
1 = 384 fs
Clock mode select:
0 = Normal
1 = USB
Reserved
USB/Normal
X
Table 3-10. Digital Interface Activation (Address: 0001001)
BIT
Function
Default
ACT
X
D8
X
0
D7
RES
0
Activate interface
Reserved
D6
RES
0
0 = Inactive
D5
X
0
D4
X
0
D3
X
0
D2
X
0
1 = Active
Table 3-11. Reset Register (Address: 0001111)
BIT
Function
Default
RES
18
D8
RES
0
D7
RES
0
D6
RES
0
D5
RES
0
D4
RES
0
D3
RES
0
D2
RES
0
Write 000000000 to this register triggers reset
How to Use the TLV320AIC23B-Q1
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
3.2
3.2.1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
Analog Interface
Line Inputs
The TLV320AIC23B-Q1 has line inputs for the left and the right audio channels (RLINEIN and LLINEIN).
Both line inputs have independently programmable volume controls and mutes. Active and passive filters
for the two channels prevent high frequencies from folding back into the audio band.
The line-input gain is logarithmically adjustable from 12 dB to –34.5 dB in 1.5-dB steps. The ADC fullscale range is 1 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with analog supply voltage
AVDD. To avoid distortions, it is important not to exceed the full-scale range.
The gain is independently programmable on both left and right line-inputs. To reduce the number of
software write cycles required. Both channels can be locked to the same value by setting the RLS and
LRS bits (see Section 3.1.3).
The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to
standby mode, the line inputs are kept biased to VMID using special antithump circuitry. This reduces
audible clicks that otherwise might be heard when reactivating the inputs.
For interfacing to a CD system, the line input should be scaled to 1 VRMS to avoid clipping, using the circuit
shown in Figure 3-3.
Where:
R1
R1 = 5 kΩ
R2 = 5 kΩ
C1 = 47 pF
C2 = 470 nF
C2
+
CDIN
LINEIN
R2
C1
AGND
S0526-01
Figure 3-3. Analog Line Input Circuit
R1 and R2 divide the input signal by two, reducing the 2 VRMS from the CD player to the nominal 1 VRMS of
the AIC23B inputs. The C1 filters high-frequency noise, and C2 removes any dc component from the
signal.
3.2.2
Microphone Input
MICIN is a high-impedance, low-capacitance input that is compatible with a wide range of microphones. It
has a programmable volume control and a mute function. Active and passive filters prevent high
frequencies from folding back into the audio band.
The MICIN signal path has two gain stages. The first stage has a nominal gain of G1 = 50 k/10 k = 5. By
adding an external resistor (RMIC) in series with MICIN, the gain of the first stage can be adjusted by G1 =
50 k/(10 k + RMIC). For example, RMIC = 40 k gives a gain of 0 dB. The second stage has a software
programmable gain of 0 dB or 20 dB (see Section 3.1.3).
50 kΩ
10 kΩ
MICIN
To ADC
VMID
0 dB/20 dB
S0527-01
Figure 3-4. Microphone Input Circuit
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
How to Use the TLV320AIC23B-Q1
19
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
www.ti.com
The microphone input is biased internally to VMID. When the line inputs are muted, the MICIN input is
kept biased to VMID using special antithump circuitry. This reduces audible clicks that may otherwise be
heard when reactivating the input.
The MICBIAS output provides a low-noise reference voltage suitable for biasing electret type microphones
and the associated external resistor biasing network. The maximum source current capability is 3 mA.
This limits the smallest value of external biasing resistors that safely can be used.
The MICBIAS output is not active in standby mode.
3.2.3
Line Outputs
The TLV320AIC23B-Q1 has two low-impedance line outputs (LLINEOUT and RLINEOUT) capable of
driving line loads with 10-kΩ and 50-pF impedances.
The DAC full-scale output voltage is 1 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with the
analog supply voltage AVDD. The DAC is connected to the line outputs via a low-pass filter that removes
out-of-band components. No further external filtering is required in most applications.
The DAC outputs, line inputs, and the microphone signal are summed into the line outputs. These sources
can be switched off independently. For example, in bypass mode, the line inputs are routed to the line
outputs, bypassing the ADC and the DAC. If sidetone is enabled, the microphone signal is routed to both
line outputs via a four-step programmable attenuation circuit.
The line outputs are muted by either muting the DAC (analog) or soft muting (digital) and disabling the
bypass and sidetone paths (see Section 3.1.3).
3.2.4
Headphone Output
The TLV320AIC23B-Q1 has stereo headphone outputs (LHPOUT and RHPOUT), and is designed to drive
16-Ω or 32-Ω headphones. The headphone output includes a high-quality volume control and mute
function.
The headphone volume is logarithmically adjustable from 6 dB to –73 dB in 1-dB steps. Writing 000000 to
the volume-control registers (see Section 3.1.3) mutes the headphone output. When the headphone
output is muted or the device is placed in standby mode, the dc voltage is maintained at the outputs to
prevent audible clicks.
A zero-cross detection circuit is provided under the control of the LZC and RZC bits. If this circuit is
enabled, the volume-control values are updated only when the input signal to the gain stage is close to the
analog ground level.
This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no timeout, so, if only dc levels are being applied to the gain stage input of more than 20 mV, the gain is not
updated.
The gain is independently programmable on the left and right channels. Both channels can be locked to
the same value by setting the RLS and LRS bits (see Section 3.1.3).
3.2.5
Analog Bypass Mode
The TLV320AIC23B-Q1 includes a bypass mode in which the analog line inputs are directly routed to the
analog line outputs, bypassing the ADC and DAC. This is enabled by selecting the bypass bit in the
analog audio path control register (see Section 3.1.3).
For a true bypass mode, the output from the DAC and the sidetone should be disabled. The line input and
headphone output volume controls and mutes are still operational in bypass mode. Therefore the line
inputs, DAC output, and microphone input can be summed together. The maximum signal at any point in
the bypass path must be no greater than 1 VRMS at AVDD = 3.3 V to avoid clipping and distortion. This
amplitude tracks linearly with AVDD.
20
How to Use the TLV320AIC23B-Q1
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
3.2.6
SGLS240C – MARCH 2004 – REVISED JUNE 2012
Sidetone Insertion
The TLV320AIC23B-Q1 has a sidetone insertion made where the microphone input is routed to the line
and headphone outputs. This is useful for telephony and headset applications. The attenuation of the
sidetone signal may be set to −6 dB, −9 dB, −12 dB, −15 dB, or 0 dB, by software selection (see
Section 3.1.3). If this mode is used to sum the microphone input with the DAC output and line inputs, care
must be taken not to exceed signal level to avoid clipping and distortion.
3.3
Digital Audio Interface
3.3.1
Digital Audio-Interface Modes
The TLV320AIC23B-Q1 supports four audio-interface modes.
• Right justified
• Left justified
• I2S mode
• DSP mode
The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except rightjustified mode, which does not support 32 bits).
The digital audio interface consists of clock signal BCLK, data signals DIN and DOUT, and
synchronization signals LRCIN and LRCOUT. BCLK is an output in master mode and an input in slave
mode.
3.3.1.1
Right-Justified Mode
In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN
or LRCOUT (see Figure 3-5).
1/fs
LRCIN/
LRCOUT
BCLK
Left Channel
DIN/
DOUT
0
n
n−1
MSB
Right Channel
1
0
n
n−1
1
0
LSB
T0554-01
Figure 3-5. Right-Justified Mode Timing
3.3.1.2
Left-Justified Mode
In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN
or LRCOUT (see Figure 3-6).
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
How to Use the TLV320AIC23B-Q1
21
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
www.ti.com
1/fs
LRCIN/
LRCOUT
BCLK
Left Channel
DIN/
DOUT
n
n−1
n
0
1
MSB
Right Channel
n−1
n
0
1
LSB
T0555-01
Figure 3-6. Left-Justified Mode Timing
3.3.1.3
I2S Mode
In I2S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN or
LRCOUT (see Figure 3-7).
1/fs
LRCIN/
LRCOUT
BCLK
Left Channel
1BCLK
DIN/
DOUT
n
n−1
1
MSB
Right Channel
n
0
n−1
0
1
LSB
T0556-01
2
Figure 3-7. I S Mode Timing
3.3.1.4
DSP Mode
The DSP mode is compatible with the McBSP ports of TI DSPs. LRCIN and LRCOUT must be connected
to the Frame Sync signal of the McBSP. A falling edge on LRCIN or LRCOUT starts the data transfer. The
left-channel data consists of the first data word, which is immediately followed by the right channel data
word (see Figure 3-8). Input word length is defined by the IWL register. Figure 3-8 shows LRP = 1 (default
LRP = 0).
LRCIN/
LRCOUT
BCLK
Left Channel
DIN/
DOUT
n
n−1
MSB
Right Channel
1
0
n
LSB
MSB
n−1
1
0
LSB
T0557-01
Figure 3-8. DSP Mode Timing
22
How to Use the TLV320AIC23B-Q1
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
3.3.2
SGLS240C – MARCH 2004 – REVISED JUNE 2012
Audio Sampling Rates
The TLV320AIC23B-Q1 can operate in master or slave clock mode. In the master mode, the
TLV320AIC23B-Q1 clock and sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock
signal is compatible with the USB specification. The TLV320AIC23B-Q1 can be used directly in a USB
system.
In the slave mode, an appropriate MCLK or crystal frequency and the sample rate control register settings
control the TLV320AIC23B-Q1 clock and sampling rates.
The settings in the sample rate control register control the clock mode and sampling rates.
Table 3-12. Sample Rate Control (Address: 0001000)
BIT
Function
Default
D8
X
0
CLKIN
CLKOUT
SR[3:0]
BOSR
USB/Normal
X
D7
CLKOUT
0
D6
CLKIN
0
D5
SR3
1
D4
SR2
0
D3
SR1
0
D2
SR0
0
D1
BOSR
0
D0
USB/Normal
0
Clock input divider
0 = MCLK
1 = MCLK/2
Clock output divider
0 = MCLK
1 = MCLK/2
Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2)
Base oversampling rate
USB mode:
0 = 250 fs
1 = 272 fs
Normal mode:
0 = 256 fs
1 = 384 fs
Clock mode select:
0 = Normal
1 = USB
Reserved
The clock circuit of the AIC23B has two internal dividers. The first, controlled by CLKIN, applies to the
sampling-rate generator of the codec. The second, controlled by CLKOUT, applies only to the CLKOUT
terminal. By setting CLKIN to 1, the entire codec is clocked with half the frequency, effectively dividing the
resulting sampling rates by two. The following sampling-rate tables are based on CLKIN = MCLK.
3.3.2.1
USB-Mode Sampling Rates (MCLK = 12 MHz)
In the USB mode, the following ADC and DAC sampling rates are available:
SAMPLING RATE (1)
ADC (kHz)
(1)
DAC (kHz)
FILTER TYPE
SAMPLING-RATE CONTROL SETTINGS
SR3
SR2
SR1
SR0
BOSR
96
96
3
0
1
1
1
0
88.2
88.2
2
1
1
1
1
1
48
48
0
0
0
0
0
0
44.1
44.1
1
1
0
0
0
1
32
32
0
0
1
1
0
0
8.021
8.021
1
1
0
1
1
1
8
8
0
0
0
1
1
0
48
8
0
0
0
0
1
0
44.1
8.021
1
1
0
0
1
1
8
48
0
0
0
1
0
0
8.021
44.1
1
1
0
1
0
1
The sampling rates are derived from the 12-MHz master clock. The available oversampling rates do not produce exactly 8-kHz, 44.1kHz, and 88.2-kHz sampling rates, but 8.021 kHz, 44.117 kHz, and 88.235 kHz, respectively. See Figure 3-9 through Figure 3-26 for
filter responses.
3.3.2.2
Normal-Mode Sampling Rates
In normal mode, the following ADC and DAC sampling rates, depending on the MCLK frequency, are
available:
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
How to Use the TLV320AIC23B-Q1
23
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
MCLK = 12.288 MHz
SAMPLING RATE
ADC (kHz)
DAC (kHz)
96
96
48
32
8
www.ti.com
FILTER TYPE
SAMPLING-RATE CONTROL SETTINGS
SR3
SR2
SR1
SR0
BOSR
2
0
1
1
1
0
48
1
0
0
0
0
0
32
1
0
1
1
0
0
8
1
0
0
1
1
0
48
8
1
0
0
0
1
0
8
48
1
0
0
1
0
0
MCLK = 11.2896 MHz
SAMPLING RATE
FILTER TYPE
SAMPLING-RATE CONTROL SETTINGS
ADC (kHz)
DAC (kHz)
SR3
SR2
SR1
SR0
BOSR
88.2
88.2
2
1
1
1
1
0
44.1
44.1
1
1
0
0
0
0
8.021
8.021
1
1
0
1
1
0
44.1
8.021
1
1
0
0
1
0
8.021
44.1
1
1
0
1
0
0
MCLK = 18.432 MHz
SAMPLING RATE
FILTER TYPE
SAMPLING-RATE CONTROL SETTINGS
ADC (kHz)
DAC (kHz)
SR3
SR2
SR1
SR0
BOSR
96
96
2
0
1
1
1
1
48
48
1
0
0
0
0
1
32
32
1
0
1
1
0
1
8
8
1
0
0
1
1
1
48
8
1
0
0
0
1
1
8
48
1
0
0
1
0
1
MCLK = 16.9344 MHz
SAMPLING RATE
ADC (kHz)
DAC (kHz)
88.2
88.2
44.1
44.1
8.021
FILTER TYPE
SAMPLING-RATE CONTROL SETTINGS
SR3
SR2
SR1
SR0
BOSR
2
1
1
1
1
1
1
1
0
0
0
1
8.021
1
1
0
1
1
1
44.1
8.021
1
1
0
0
1
1
8.021
44.1
1
1
0
1
0
1
3.3.3
Digital Filter Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Filter Characteristics (TI DSP 250 fs Mode Operation)
Passband
±0.05 dB
Stopband
–6 dB
0.416 fs
Hz
0.5 fs
Passband ripple
Stopband attenuation
Hz
±0.05
f > 0.584 fs
–60
dB
dB
ADC Filter Characteristics (TI DSP 272 fs and Normal Mode Operation)
Passband
±0.05 dB
Stopband
–6 dB
0.4535 fs
Hz
0.5 fs
Passband ripple
Stopband attenuation
24
How to Use the TLV320AIC23B-Q1
Hz
±0.05
f > 0.5465 fs
–60
dB
dB
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC High-Pass Filter Characteristics
Corner frequency
–3 dB, fs = 44.1 kHz
3.7
Hz
4
Hz
–0.5 dB, fs = 44.1 kHz
10.4
Hz
–0.5 dB, fs = 48 kHz
11.3
Hz
–0.1 dB fs = 44.1 kHz
21.6
Hz
–0.1 dB, fs = 48 kHz
23.5
Hz
–3 dB, fs = 48 kHz
DAC Filter Characteristics (48-kHz Sampling Rate)
Passband
±0.03 dB
Stopband
–6 dB
0.416 fs
Hz
0.5 fs
Passband ripple
Hz
±0.03
Stopband attenuation
f > 0.584 fs
–50
dB
dB
DAC Filter Characteristics (44.1-kHz Sampling Rate)
Passband
±0.03 dB
Stopband
–6 dB
0.4535 fs
Hz
0.5 fs
Passband ripple
±0.03
Stopband attenuation
f > 0.5465 fs
–50
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
0
0
−2
−2
Filter Response (dB)
Filter Response (dB)
Hz
−4
−6
−8
−10
dB
dB
−4
−6
−8
0
0.1
0.2
0.3
0.4
Normalized Audio Sampling Frequency
0.5
−10
0
0.1
0.2
0.3
0.4
Normalized Audio Sampling Frequency
G001
Figure 3-9. Digital De-Emphasis Filter Response −
44.1 kHz Sampling
0.5
G002
Figure 3-10. Digital De-Emphasis Filter Response −
48 kHz Sampling
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
How to Use the TLV320AIC23B-Q1
25
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
www.ti.com
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
10
Filter Response (dB)
−10
−30
−50
−70
−90
0
0.5
1
1.5
2
Normalized Audio Sampling Frequency
2.5
3
G003
Figure 3-11. ADC Digital Filter Response 0: USB Mode (Group Delay = 12 Output Samples)
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
0.1
0.08
Filter Response (dB)
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Normalized Audio Sampling Frequency
0.4
0.45
0.5
G004
Figure 3-12. ADC Digital Filter Ripple 0: USB (Group Delay = 20 Output Samples)
26
How to Use the TLV320AIC23B-Q1
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
10
Filter Response (dB)
−10
−30
−50
−70
−90
0
0.5
1
1.5
2
Normalized Audio Sampling Frequency
2.5
3
G005
Figure 3-13. ADC Digital Filter Response 1: USB Mode Only
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
0.1
0.1
Filter Response (dB)
0.1
0
0
0
0
0
−0.1
−0.1
−0.1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Normalized Audio Sampling Frequency
0.4
0.45
0.5
G006
Figure 3-14. ADC Digital Filter Ripple 1: USB Mode Only
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
How to Use the TLV320AIC23B-Q1
27
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
www.ti.com
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
10
Filter Response (dB)
−10
−30
−50
−70
−90
0
0.5
1
1.5
2
Normalized Audio Sampling Frequency
2.5
3
G007
Figure 3-15. ADC Digital Filter Response 2: USB Mode and Normal Modes (Group Delay = 3 Output
Samples)
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
0.4
0.3
Filter Response (dB)
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Normalized Audio Sampling Frequency
0.4
0.45
0.5
G008
Figure 3-16. ADC Digital Filter Ripple 2: USB Mode and Normal Modes
28
How to Use the TLV320AIC23B-Q1
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
10
Filter Response (dB)
−10
−30
−50
−70
−90
0
0.5
1
1.5
2
Normalized Audio Sampling Frequency
2.5
3
G009
Figure 3-17. ADC Digital Filter Response 3: USB Mode Only
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
0.4
0.3
Filter Response (dB)
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Normalized Audio Sampling Frequency
0.4
0.45
0.5
G010
Figure 3-18. ADC Digital Filter Ripple 3: USB Mode Only
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
How to Use the TLV320AIC23B-Q1
29
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
www.ti.com
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
10
Filter Response (dB)
−10
−30
−50
−70
−90
0
0.5
1
1.5
2
Normalized Audio Sampling Frequency
2.5
3
G011
Figure 3-19. DAC Digital Filter Response 0: USB Mode
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
0.1
0.08
Filter Response (dB)
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Normalized Audio Sampling Frequency
0.4
0.45
0.5
G012
Figure 3-20. DAC Digital Filter Ripple 0: USB Mode
30
How to Use the TLV320AIC23B-Q1
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
10
Filter Response (dB)
−10
−30
−50
−70
−90
0
0.5
1
1.5
2
Normalized Audio Sampling Frequency
2.5
3
G013
Figure 3-21. DAC Digital Filter Response 1: USB Mode Only
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
0.1
0.08
Filter Response (dB)
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Normalized Audio Sampling Frequency
0.4
0.45
0.5
G014
Figure 3-22. DAC Digital Filter Ripple 1: USB Mode Only
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
How to Use the TLV320AIC23B-Q1
31
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
www.ti.com
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
10
Filter Response (dB)
−10
−30
−50
−70
−90
0
0.5
1
1.5
2
Normalized Audio Sampling Frequency
2.5
3
G015
Figure 3-23. DAC Digital Filter Response 2: USB Mode and Normal Modes
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
0.4
0.3
Filter Response (dB)
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Normalized Audio Sampling Frequency
0.4
0.45
0.5
G016
Figure 3-24. DAC Digital Filter Ripple 2: USB Mode and Normal Modes
32
How to Use the TLV320AIC23B-Q1
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
10
Filter Response (dB)
−10
−30
−50
−70
−90
0
0.5
1
1.5
2
Normalized Audio Sampling Frequency
2.5
3
G017
Figure 3-25. DAC Digital Filter Response 3: USB Mode Only
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
0.4
0.3
Filter Response (dB)
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Normalized Audio Sampling Frequency
0.4
0.45
0.5
G018
Figure 3-26. DAC Digital Filter Ripple 3: USB Mode Only
The delay between the converter is a function of the sample rate. The group delays for the AIC23B are
shown in the following table. Each delay is one LR clock (1/sample rate).
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
How to Use the TLV320AIC23B-Q1
33
TLV320AIC23B-Q1
SGLS240C – MARCH 2004 – REVISED JUNE 2012
www.ti.com
Table 3-13. Group Delays
34
How to Use the TLV320AIC23B-Q1
FILTER
GROUP DELAY
DAC type 0
11
DAC type 1
18
DAC type 2
5
DAC type 3
5
ADC type 0
12
ADC type 1
20
ADC type 2
3
ADC type 3
6
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2008) to Revision C
•
Page
Added sentences after: The TLV320AIC23B-Q1 has the following set of registers, which are used to
program the modes of operation, in the Register Map section. ......................................................... 15
Copyright © 2004–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC23B-Q1
How to Use the TLV320AIC23B-Q1
35
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
6PAIC23BIPWRG4Q1
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
TLV320AIC23BIPWRQ1
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV320AIC23B-Q1 :
• Catalog: TLV320AIC23B
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2012
• Catalog - TI's standard catalog product
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated