ADS5424-SP www.ti.com SLWS194B – MAY 2008 – REVISED MARCH 2012 CLASS V, 14-BIT, 105-MSPS ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS5424-SP FEATURES 1 • • • • • • • • • • • 14-Bit Resolution 105-MSPS Maximum Sample Rate SNR = 70 dBc at 105 MSPS and 50 MHz IF SFDR = 78 dBc at 105 MSPS and 50 MHz IF 2.2-VPP Differential Input Range 5-V Supply Operation 3.3-V CMOS Compatible Outputs 2.3-W Total Power Dissipation 2s Complement Output Format On-Chip Input Analog Buffer, Track and Hold, and Reference Circuit 52-Pin Ceramic Nonconductive Tie-Bar Package (HFG) • • Military Temperature Range ( –55°C to 125°C Tcase) QML-V Qualified, SMD 5962-07206 APPLICATIONS • • • • Single and Multichannel Digital Receivers Base Station Infrastructure Instrumentation Video and Imaging RELATED DEVICES • • Clocking: CDC7005 Amplifiers: OPA695, THS4509 DESCRIPTION/ORDERING INFORMATION The ADS5424 is a 14-bit, 105-MSPS analog-to-digital converter (ADC) that operates from a 5-V supply, while providing 3.3-V CMOS compatible digital outputs. The ADS5424 input buffer isolates the internal switching of the on-chip track and hold (T&H) from disturbing the signal source. An internal reference generator is also provided to further simplify the system design. The ADS5424 has outstanding low noise and linearity, over input frequency. With only a 2.2-VPP input range, ADS5424 simplifies the design of multicarrier applications, where the carriers are selected on the digital domain. The ADS5424 is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The ADS5424 is built on state of the art Texas Instruments complementary bipolar process (BiCom3) and is specified over full military temperature range (–55°C to 125°C Tcase) Table 1. ORDERING INFORMATION (1) (1) (2) TA PACKAGE (2) ORDERING PART NUMBER TOP-SIDE MARKING –55°C to 125°C Tcase 52/ HFG 5962-0720601VXC 5962-0720601VXC ADS5424MHFG-V For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2012, Texas Instruments Incorporated ADS5424-SP SLWS194B – MAY 2008 – REVISED MARCH 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM AVDD AIN AIN TH1 A1 + TH2 Σ + TH3 A2 ADC1 DAC1 A3 ADC3 − − VREF Σ DRVDD ADC2 DAC2 Reference 5 5 6 C1 C2 CLK+ CLK− Digital Error Correction Timing DMID OVR DRY D[13:0] GND ABSOLUTE MAXIMUM RATINGS over operating temperature range (unless otherwise noted) (1) ADS5424 Supply voltage AVDD to GND 6 DRVDD to GND 5 UNIT V Analog input to GND –0.3 V to AVDD + 0.3 V Clock input to GND –0.3 V to AVDD + 0.3 V ±2.5 V CLK to CLK Digital data output to GND TC Characterized case operating temperature range TJ Maximum junction temperature Tstg Storage temperature range (1) 2 –0.3 V to DRVDD + 0.3 V –55°C to 125 °C 150 °C –65°C to 150 °C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP ADS5424-SP www.ti.com SLWS194B – MAY 2008 – REVISED MARCH 2012 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT 4.75 5 5.25 V 3 3.3 3.6 V SUPPLIES AVDD Analog supply voltage DRVDD Output driver supply voltage ANALOG INPUT VCM Differential input range 2.2 VPP Input common mode voltage 2.4 V 10 pF DIGITAL OUTPUT Maximum output load CLOCK INPUT ADCLK input sample rate (sine wave) 30 Clock amplitude, differential sine wave Clock duty cycle TC 105 MSPS 3 VPP 50% Open case temperature range –55 125 °C ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) Typical values at TC = 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Resolution TYP MAX UNIT 14 Bits 2.2 Vpp 1 kΩ ANALOG INPUTS Differential input range Differential input resistance See Figure 11 Differential input capacitance See Figure 11 Analog input bandwidth 1.5 pF 570 MHz INTERNAL REFERENCE VOLTAGES VREF Reference voltage 2.38 2.4 2.41 V DYNAMIC ACCURACY No missing codes DNL Differential linearity error INL Integral linearity error Tested fIN = 10 MHz fIN = 10 MHz TC= 25°C and TC,MAX fIN = 10 MHz TC= TC,MIN Offset error –0.98 ±0.5 1.5 LSB –5.0 ±3.0 +5.0 LSB +6.9 LSB –-6.9 –1.5 Offset temperature coefficient 0 1.5 0.0007 Gain error –5 Gain temperature coefficient 0.9 %FS %FS/°C 5 0.006 %FS %FS/°C POWER SUPPLY IAVDD Analog supply current VIN = full scale, fIN = 70 MHz FS = 105 MSPS 355 410 mA IDRVDD Output buffer supply current VIN = full scale, fIN = 70 MHz FS = 105 MSPS 47 55 mA Power dissipation Total power with 10-pF load on each digital output to ground, fIN = 70 MHz FS = 105 MSPS 1.9 2.3 W FS = 105 MSPS 20 Power-up time Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP ms 3 ADS5424-SP SLWS194B – MAY 2008 – REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued) Typical values at TC = 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP TC= 25°C 70.5 72.4 TC = TC,MAX 71.0 TC= TC,MIN 70.5 Full Temp Range 70.0 TC= 25°C 68.2 TC = TC,MAX 67.0 TC= TC,MIN 68.0 MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz fIN = 30 MHz fIN = 50 MHz SNR Signal-to-noise ratio fIN = 70 MHz 68.9 66.3 fIN = 230 MHz 64.0 TC = 25°C 72.0 Full Temp Range 71.0 TC= 25°C 77.0 TC = TC,MAX 69.0 TC= TC,MIN 75.0 TC= 25°C 68.0 TC = TC,MAX 69.0 TC= TC,MIN 67.0 fIN = 50 MHz fIN = 70 MHz fIN = 170 MHz 68.0 dBc 65.4 TC= 25°C 68.6 TC = TC,MAX 68.3 TC= TC,MIN 68.2 TC= 25°C 69.4 TC = TC,MAX 67.0 TC= TC,MIN 69.4 TC= 25°C 65.8 TC = TC,MAX 64.6 TC= TC,MIN 65.0 fIN = 50 MHz fIN = 70 MHz 4 82.6 82.5 fIN = 30 MHz Signal-to-noise + distortion 80.6 fIN = 100 MHz fIN = 10 MHz dBc 81.6 78.1 fIN = 230 MHz SINAD 70.1 fIN = 170 MHz fIN = 30 MHz Spurious free dynamic range 70.9 fIN = 100 MHz fIN = 10 MHz SFDR 71.5 71.3 70.2 69.9 fIN = 100 MHz 68.6 fIN = 170 MHz 64.0 fIN = 230 MHz 61.1 Submit Documentation Feedback dBc 69.7 Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP ADS5424-SP www.ti.com SLWS194B – MAY 2008 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued) Typical values at TC = 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise noted) PARAMETER TEST CONDITIONS fIN = 10 MHz fIN = 30 MHz HD2 Second harmonic 81.8 Full Temp Range 71.0 TC= 25°C 77.0 TC = TC,MAX 69.0 TC= TC,MIN 75.0 TC= 25°C 68.0 TC = TC,MAX 69.0 TC= TC,MIN 67.0 86.5 85.0 86.1 fIN = 170 MHz 93.0 fIN = 230 MHz 71.0 fIN = 30 MHz TC = 25°C 72.0 Full Temp Range 71.0 TC= 25°C 77.0 TC = TC,MAX 69.0 TC= TC,MIN 75.0 TC= 25°C 68.0 TC = TC,MAX 69.0 TC= TC,MIN 67.0 fIN = 50 MHz fIN = 70 MHz 82.6 83.3 fIN = 170 MHz 68.0 fIN = 30 MHz fIN = 70 MHz dBc 65.4 Full Temp Range 75.0 85.5 TC= 25°C 80.0 83.8 TC = TC,MAX 74.0 TC= TC,MIN 80.0 fIN = 50 MHz Worst other harmonic/spur (other than HD2 and HD3) dBc 81.3 78.1 fIN = 230 MHz UNIT 81.6 fIN = 100 MHz fIN = 10 MHz MAX 80.6 fIN = 100 MHz fIN = 10 MHz Third harmonic TYP 72.0 fIN = 50 MHz fIN = 70 MHz HD3 MIN TC = 25°C 87.0 TC= 25°C 74.0 TC = TC,MAX 72.0 TC= TC,MIN 74.0 83.0 fIN = 100 MHz 82.5 fIN = 170 MHz 79.8 fIN = 230 MHz 78.0 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP dBc 5 ADS5424-SP SLWS194B – MAY 2008 – REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued) Typical values at TC = 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise noted) PARAMETER TEST CONDITIONS fIN = 10 MHz fIN = 30 MHz THD Total harmonic distortion Full Temp Range 70.0 TC= 25°C 75.0 TC = TC,MAX 68.0 TC= TC,MIN 73.8 TC= 25°C 67.4 TC = TC,MAX 67.2 TC= TC,MIN 66.4 MAX 79.9 67.6 fIN = 230 MHz 64.1 fIN = 30 MHz 11.1 TC = TC,MAX 11.0 TC= TC,MIN 11.0 TC= 25°C 11.2 TC = TC,MAX 10.8 TC= TC,MIN 11.2 TC= 25°C 10.6 TC = TC,MAX 10.4 TC= TC,MIN 10.5 Input pins tied together dBC 79.6 fIN = 170 MHz TC= 25°C UNIT 77.4 fIN = 100 MHz fIN = 70 MHz RMS idle channel noise 77.8 76.7 fIN = 10 MHz Effective number of bits TYP 71.0 fIN = 50 MHz fIN = 70 MHz ENOB MIN TC = 25°C 11.7 11.5 Bits 11.4 0.9 LSB DIGITAL CHARACTERISTICS (Unchanged after 100 kRad) Typical values at TC = 25 °C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, AVDD = 5 V, DRVDD = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.1 0.6 UNIT Digital Outputs Low-level output voltage CLOAD = 10 pF (1) High-level output voltage (1) CLOAD = 10 pF 2.6 Output capacitance DMID (1) 6 1.65 V 3.2 V 3 pF 1.8 V Equivalent capacitance to ground of (load + parasitics of transmission lines) Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP ADS5424-SP www.ti.com SLWS194B – MAY 2008 – REVISED MARCH 2012 TIMING CHARACTERISTICS (1)(Unchanged after 100 kRad) Typical values at TC = 25°C, Over full temperature range, AVDD = 5 V, DRVDD = 3.3 V, sampling rate = 105 MSPS PARAMETER MI N TYP MAX UNIT Aperture Time tA Aperture delay 500 ps tJ Clock slope independent aperture uncertainty (jitter) 150 fs kJ Clock slope dependent jitter factor 50 μV tCLK Clock period 9.5 ns tCLKH Clock pulse width high 4.75 ns tCLKL Clock pulse width low 4.75 ns Clock Input Clock to DataReady (DRY) tDR Clock rising 50% to DRY falling 50% 2.2 tC_DR Clock rising 50% to DRY rising 50% tC_DR_50% Clock rising 50% to DRY rising 50% with 50% duty cycle clock 3.0 4.7 tDR + tCLKH 7.0 7.8 ns ns 9.5 ns Clock to DATA, OVR (2) tr Data VOL to data VOH (rise time) 0.6 ns tf Data VOH to data VOL (fall time) 0.6 ns L Latency tsu_c Valid DATA (3) to clock 50% with 50% duty cycle clock (setup time) 1.8 3.6 ns Clock 50% to invalid DATA (3) (hold time) 2.6 4.1 ns Valid DATA (3) to DRY 50% with 50% duty cycle clock (setup time) 0.9 1.40 ns 3.9 6.3 ns th_c DataReady (DRY)/DATA, OVR Cycl es (2) tsu(DR)_50% th(DR)_50% (1) (2) (3) 3 DRY 50% to invalid DATA (hold time) (3) with 50% duty cycle clock All values obtained from design and characterization. Data is updated with clock rising edge or DRY falling edge. See VOH and VOL levels. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP 7 ADS5424-SP SLWS194B – MAY 2008 – REVISED MARCH 2012 www.ti.com tA N+3 N AIN N+1 N+2 tCLKH tCLK CLK, CLK N+1 N N+4 tCLKL N+2 N+3 tC_DR D[13:0], OVR DRY N−3 tr N−2 tf tsu(C) N−1 tsu(DR) N+4 th(C) N th(DR) tDR Figure 1. Timing Diagram 8 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP ADS5424-SP www.ti.com SLWS194B – MAY 2008 – REVISED MARCH 2012 DEVICE INFORMATION D4 GND D5 D6 DRVDD D8 D7 D10 D9 D12 D11 DRY D13 (MSB) HFG PACKAGE (TOP VIEW) DRVDD 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 D3 GND 2 38 D2 VREF 3 37 GND 4 36 D1 D0 (LSB) CLK 5 35 DMID CLK GND AVDD 6 34 7 33 GND DRVDD 8 32 OVR AVDD 9 31 GND 10 30 DNC AVDD AIN 11 29 AIN GND 12 28 C2 GND GND AVDD GND C1 GND AVDD GND GND AVDD GND AVDD AVDD 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 GND AVDD TERMINAL FUNCTIONS TERMINAL NAME DRVDD DESCRIPTION NO. 1, 33, 43 3.3 V power supply, digital output stage only GND 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34, 42 VREF 3 2.4 V reference. Bypass to ground with a 0.1 μF microwave chip capacitor. CLK 5 Clock input. Conversion initiated on rising edge CLK 6 Complement of CLK, differential input AVDD 8, 9, 14, 16, 18, 22, 26, 28, 30 Ground 5 V analog power supply AIN 11 Analog input AIN 12 Complement of AIN, differential analog input C1 20 Internal voltage reference. Bypass to ground with a 0.1 μF chip capacitor. C2 24 Internal voltage reference. Bypass to ground with a 0.1 μF chip capacitor. DNC 31 Do not connect OVR 32 Overrange bit. A logic level high indicates the analog input exceeds full scale. DMID 35 Output data voltage midpoint. Approximately equal to (DVCC)/2 D0 (LSB) 36 Digital output bit (least significant bit); two's complement D1–D5, D6–D12 37–41, 44–50 Digital output bits in two's complement D13 (MSB) 51 Digital output bit (most significant bit); two's complement DRY 52 Data ready output Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP 9 ADS5424-SP SLWS194B – MAY 2008 – REVISED MARCH 2012 www.ti.com THERMAL CHARACTERISTICS TEST CONDITIONS TYP UNIT RθJA Junction-to-free-air thermal resistance PARAMETER Board Mounted, Per JESD 51-5 methodology 21.81 °C/W RθJC Junction-to-case thermal resistance MIL-STD-883 Test Method 1012 0.849 °C/W THERMAL NOTES This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly underneath the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI typically recommends a 16-mm2 board-mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias must be included to keep the device within recommended operating conditions. This pad must be electrically at ground potential. 1000.00 Years estimated life 100.00 Electromigration Fail Mode 10.00 1.00 80 90 100 110 120 130 140 150 160 170 180 Continuous Tj (°C) Figure 2. ADS5424 Estimated Device Life at Elevated Temperatures Electromigration Fail Mode 10 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP ADS5424-SP www.ti.com SLWS194B – MAY 2008 – REVISED MARCH 2012 DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree celsius of the parameter from TMIN or TMAX. It is computed as the maximum variation of that parameter over the whole temperature range divided by TMAX – TMIN. Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and in the first five harmonics. P SNR + 10Log 10 S PN SNR is given either in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Minimum Conversion Rate The minimum sampling rate at which the ADC functions Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD + 10Log 10 PN ) PD Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSB. SINAD is given either in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to Full Scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Integral Nonlinearity (INL) INL is the deviation of the ADC transfer function from a best-fit line determined by a least-squares curve fit of that transfer function, measured in units of LSB. Gain Error Gain error is the deviation of the ADC actual input full-scale range from its ideal value. Gain error is given as a percentage of the ideal input full-scale range. Offset Error The offset error is the difference, given in number of LSBs, between the ADC's actual value average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first five harmonics (PD). P THD + 10Log 10 S PD THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1). IMD3 is given either in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when it is referred to the full-scale range Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP 11 ADS5424-SP SLWS194B – MAY 2008 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 105 MSPS, 3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted) AC PERFORMANCE vs INPUT AMPLITUDE (170 MHz) AC Performance - dB AC Performance - dB AC PERFORMANCE vs INPUT AMPLITUDE (70 MHz) fS = 92.16 MSPS fIN = 70 MHz AIN - Input Amplitude - dB 12 fS = 92.16 MSPS fIN = 170 MHz AIN - Input Amplitude - dB Figure 3. Figure 4. AC PERFORMANCE vs CLOCK LEVEL (70 MHz) AC PERFORMANCE vs CLOCK LEVEL (170 MHz) Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP ADS5424-SP www.ti.com SLWS194B – MAY 2008 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 105 MSPS, 3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted) SIGNAL-TO-NOISE RATIO vs SUPPLY VOLTAGE AND AMBIENT TEMPERATURE SNR - Signal-to-Noise - dBc SFDR - Sprious-Free Dynamic Range - dBc SPURIOUS-FREE DYNAMIC RANGE vs SUPPLY VOLTAGE AND AMBIENT TEMPERATURE DRVDD - Supply Voltage - V DRVDD - Supply Voltage - V Figure 7. Figure 8. SNR vs INPUT FREQUENCY and SAMPLING FREQUENCY SFDR vs INPUT FREQUENCY and SAMPLING FREQUENCY Figure 9. Figure 10. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP 13 ADS5424-SP SLWS194B – MAY 2008 – REVISED MARCH 2012 www.ti.com EQUIVALENT CIRCUITS DRVDD AVDD AIN BUF T/H 500 Ω BUF VREF AVDD 500 Ω AIN BUF T/H Figure 11. Analog Input Figure 12. Digital Output AVDD AVDD + CLK Bandgap 1 kΩ Clock Buffer 25 Ω − VREF 1.2 kΩ 1.2 kΩ Bandgap AVDD 1 kΩ CLK Figure 13. Clock Input 14 Figure 14. Reference Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP ADS5424-SP www.ti.com SLWS194B – MAY 2008 – REVISED MARCH 2012 EQUIVALENT CIRCUITS (continued) AVDD DRVDD 10 kΩ − DAC Bandgap + IOUTP DMID IOUTM C1, C2 10 kΩ Figure 15. Decoupling Pin Figure 16. DMID Generation Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP 15 ADS5424-SP SLWS194B – MAY 2008 – REVISED MARCH 2012 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS5424 is a 14-bit, 105-MSPS, monolithic pipeline analog to digital converter. Its bipolar analog core operates from a 5-V supply, while the output uses 3.3-V supply for compatibility with the CMOS family. The conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is captured by the input track and hold (T&H) and the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of three clock cycles, after which the output data is available as a 14 bit parallel word, coded in binary 2's complement format. INPUT CONFIGURATION The analog input for the ADS5424 (see Figure 11) consists of an analog differential buffer followed by a bipolar track-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching. The input common mode is set internally through a 500-Ω resistor connected from 2.4 V to each of the inputs. This results in a differential input impedance of 1 kΩ. For a full-scale differential input, each of the differential lines of the input signal (pins 11 and 12) swings symmetrically between 2.4 ±0.55 V and 2.4 –0.55 V. This means that each input is driven with a signal of up to 2.4 ±0.55 V, so that each input has a maximum signal swing of 1.1 VPP for a total differential input signal swing of 2.2 VPP. The maximum swing is determined by the internal reference voltage generator eliminating any external circuitry for this purpose. The ADS5424 obtains optimum performance when the analog inputs are driven differentially. The circuit in Figure 17 shows one possible configuration using an RF transformer with termination either on the primary or on the secondary of the transformer. If voltage gain is required, a step-up transformer can be used. For higher gains that would require impractical higher turn ratios on the transformer, a single-ended amplifier driving the transformer can be used (see Figure 18). Another circuit optimized for performance would be the one on Figure 19, using the THS4304 or the OPA695. Texas Instruments has shown excellent performance on this configuration up to 10-dB gain with the THS4304 and at 14-dB gain with the OPA695. For the best performance, they need to be configured differentially after the transformer (as shown) or in inverting mode for the OPA695 (see SBAA113); otherwise, HD2 from the op amps limits the useful frequency. R0 50W Z0 50W AIN 1:1 R 50W AC Signal Source ADS5424M AIN ADT1−1WT Figure 17. Converting a Single-Ended Input to a Differential Signal Using RF Transformers 5V VIN −5 V RS 100 Ω + OPA695 − 0.1 µF 1000 µF RIN 1:1 RT 100 Ω RIN AIN CIN ADS5424M AIN R1 400 Ω R2 57.5 Ω AV = 8V/V (18 dB) Figure 18. Using the OPA695 With the ADS5424 16 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP ADS5424-SP www.ti.com SLWS194B – MAY 2008 – REVISED MARCH 2012 RG RF CM 5V − THS4304 + 1:1 VIN 49.9 Ω CM AIN ADS5424M VREF AIN 5V From 50 Ω Source + THS4304 − RG CM RF CM Figure 19. Using the THS4304 With the ADS5424 Texas Instruments offers a wide selection of single-ended operational amplifiers (including the THS3201, THS3202 and OPA847) that can be selected depending on the application. An RF gain block amplifier, such as Texas Instrument's THS9001, also can be used with an RF transformer for high input frequency applications. For applications requiring dc-coupling with the signal source, instead of using a topology with three single-ended amplifiers, a differential input/differential output amplifier like the THS4509 (see Figure 20) can be used, which minimizes board space and reduces the number of components. From VIN 50 Ω Source 100 Ω 69.8 Ω 348 Ω +5V 225 Ω 0.22 µF 100 Ω 49.9 Ω 0.22 µF 69.8 Ω THS 4509 2.7 pF 225 Ω CM 14-Bit 105 MSPS AIN ADS5424M AIN VREF 49.9 Ω 0.22 µF 348 Ω 0.1 µF 0.1 µF Figure 20. Using the THS4509 With the ADS5424 On this configuration, the THS4509 amplifier circuit provides 10-dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5424. The 225-Ω resistors and 2.7-pF capacitor between the THS4509 outputs and ADS5424 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to about 100 MHz (–3 dB). For this test, an Agilent signal generator is used for the signal source. The generator is an ac-coupled 50-Ω source. A bandpass filter is inserted in series with the input to reduce harmonics and noise from the signal source. Input termination is accomplished via the 69.8-Ω resistor and 0.22-μF capacitor to ground in conjunction with the input impedance of the amplifier circuit. A 0.22-μF capacitor and 49.9-Ω resistor is inserted to ground across the 69.8-Ω resistor and 0.22-μF capacitor on the alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348-Ω feedback resistor. See the THS4509 data sheet for further component values to set proper 50-Ω termination for other common gains. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP 17 ADS5424-SP SLWS194B – MAY 2008 – REVISED MARCH 2012 www.ti.com Because the ADS5424 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a single power supply input with VS+ = 5 V and VS– = 0 V (ground). This maintains maximum headroom on the internal transistors of the THS4509. CLOCK INPUTS The ADS5424 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. In low-input-frequency applications, where jitter may not be a big concern, the use of single-ended clock (see Figure 21) could save cost and board space without any trade-off in performance. When driven on this configuration, it is best to connect CLKM (pin 11) to ground with a 0.01-μF capacitor, while CLKP is ac-coupled with a 0.01-μF capacitor to the clock source, as shown in Figure 22. Square Wave or Sine Wave CLK 0.01 µF ADS5424M CLK 0.01 µF Figure 21. Single-Ended Clock 0.1 µF Clock Source 1:4 CLK MA3X71600LCT−ND ADS5424 M CLK Figure 22. Differential Clock For jitter sensitive applications, the use of a differential clock has advantages (as with any other ADCs) at the system level. The first advantage is that it allows for common-mode noise rejection at the PCB level. A further analysis (see Clocking High Speed Data Converters, SLYT075) reveals one more advantage. The following formula describes the different contributions to clock jitter: (Jittertotal)2 = (EXT_jitter)2 + (ADC_jitter)2 = (EXT_jitter)2 + (ADC_int)2 + (K/clock_slope)2 The first term represents the external jitter, coming from the clock source, plus noise added by the system on the clock distribution, up to the ADC. The second term is the ADC contribution, which can be divided in two portions. The first does not depend directly on any external factor. The second contribution is a term inversely proportional to the clock slope. The faster the slope, the smaller this term will be. As an example, the ADC jitter contribution could be computed from a sinusoidal input clock of 3-Vpp amplitude and Fs = 80 MSPS: ADC_jitter = sqrt ((150 fs)2 + (5 × 10–5/(1.5 × 2 × PI × 80 × 106))2) = 164 fs The use of differential clock allows for the use of bigger clock amplitudes without exceeding the absolute maximum ratings. This, on the case of sinusoidal clock, results on higher slew rates, which minimize the impact of the jitter factor inversely proportional to the clock slope. Figure 23 shows this approach. The back-to-back Schottky can be added to limit the clock amplitude in cases where this would exceed the absolute maximum ratings, even when using a differential clock. 18 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP ADS5424-SP www.ti.com SLWS194B – MAY 2008 – REVISED MARCH 2012 100 nF MC100EP16DT 100 nF D D 100 nF CLK Q VBB Q 100 nF ADS5424M CLK 499 W 499 W 50 Ω 50 Ω 100 nF 113 Ω Figure 23. Differential Clock Using PECL Logic Another possibility is the use of a logic based clock, as PECL. In this case, the slew rate of the edges will most likely be much higher than the one obtained for the same clock amplitude based on a sinusoidal clock. This solution would minimize the effect of the slope dependent ADC jitter. Nevertheless, observe that for the ADS5424, this term is small and has been optimized. Using logic gates to square a sinusoidal clock may not produce the best results as logic gates, which may not have been optimized to act as comparators, adding too much jitter while squaring the inputs. The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is recommended to use an ac coupling, but if for any reason, this scheme is not possible, due to, for instance, asynchronous clocking, the ADS5424 presents a good tolerance to clock common-mode variation. Additionally, the internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty cycle should be provided. DIGITAL OUTPUTS The ADC provides 14 data outputs (D13 to D0, with D13 being the MSB and D0 the LSB), a data-ready signal (DRY, pin 52), and an out-of-range indicator (OVR, pin 32) that equals 1 when the output reaches the full-scale limits. The output format is two's complement. When the input voltage is at negative full scale (around –1.1-V differential), the output will be, from MSB to LSB, 10 0000 0000 0000. Then, as the input voltage is increased, the output switches to 10 0000 0000 0001, 10 0000 0000 0010 and so on until 11 1111 1111 1111 right before mid-scale (when both inputs are tight together if we neglect offset errors). Further increases on input voltage, outputs the word 00 0000 0000 0000, to be followed by 00 0000 0000 0001, 00 0000 0000 0010 and so on until reaching 01 1111 1111 1111 at full-scale input (1.1-V differential). Although the output circuitry of the ADS5424 has been designed to minimize the noise produced by the transients of the data switching, care must be taken when designing the circuitry reading the ADS5424 outputs. Output load capacitance should be minimized by minimizing the load on the output traces, reducing their length and the number of gates connected to them, and by the use of a series resistor with each pin. Typical numbers on the data sheet tables and graphs are obtained with 100-Ω series resistor on each digital output pin, followed by a 74AVC16244 digital buffer as the one used in the evaluation board. POWER SUPPLIES The use of low noise power supplies with adequate decoupling is recommended, being the linear supplies the first choice versus switched ones, which tend to generate more noise components that can be coupled to the ADS5424. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP 19 ADS5424-SP SLWS194B – MAY 2008 – REVISED MARCH 2012 www.ti.com The ADS5424 uses two power supplies. For the analog portion of the design, a 5-V AVDD is used, while for the digital outputs supply (DRVDD), we recommend the use of 3.3 V. All the ground pins are marked as GND, although AGND pins and DRGND pins are not tied together inside the package. Customers willing to experiment with different grounding schemes should know that AGND pins are 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, and 29, while DRGND pins are 2, 34, and 42. We recommend that both grounds are tied together externally, using a common ground plane. That is the case on the production test boards and modules provided to customer for evaluation. To obtain the best performance, user should lay out the board to assure that the digital return currents do not flow under the analog portion of the board. This can be achieved without splitting the board and with careful component placement and increasing the number of vias and ground planes. Finally, notice that the metallic heat sink under the package is also connected to analog ground. LAYOUT INFORMATION The evaluation board represents a good guideline of how to lay out the board to obtain the maximum performance out of the ADS5424. General design rules for use of multilayer boards, single ground plane for both, analog and digital ADC ground connections, and local decoupling ceramic chip capacitors should be applied. The input traces should be isolated from any external source of interference or noise, including the digital outputs as well as the clock traces. Clock also should be isolated from other signals, especially on applications where low jitter is required, as high IF sampling. Besides performance oriented rules, special care has to be taken when considering the heat dissipation out of the device. The thermal package information describes the TJA values obtained on the different configurations. 20 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5424-SP PACKAGE OPTION ADDENDUM www.ti.com 8-Mar-2012 PACKAGING INFORMATION Orderable Device 5962-0720601VXC Status (1) Package Type Package Drawing ACTIVE CFP HFG Pins Package Qty 52 1 Eco Plan TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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