TRF3710 www.ti.com SLWS199 – AUGUST 2007 IQ DEMODULATOR To Microcontroller FEATURES To Microcontroller • • VOFFI VCMI Gain_B1 Gain_B2 NC Gain_B0 MIXIoutn NC STROBE MIXIoutp CLOCK 1 VCCDIG 2 35 AGND CHIP_EN 3 34 BBIoutp VCCMIX 4 33 BBIoutn NC 5 32 NC MIXinp 6 31 LOip RF in VCCBBI To ADC in phase Local Osc TRF3710 MIXinn 7 30 LOin NC 8 29 VCCLO VCCMIX 9 28 BBQoutp NC 10 27 BBQoutn NC 11 26 NC 25 12 13 14 15 16 17 18 19 20 21 22 23 24 AGND VCCBBQ VCMQ VOFFQ VCCBIAS GNDBIAS NC REXT NC NC MIXQoutn Wireless Infrastructure – WCDMA – CDMA Wireless Local Loop High Linearity Direct-Down Conversion Receiver MIXQoutp To ADC Quadrature APPLICATIONS • 48 47 46 45 44 43 42 41 40 39 38 37 36 GNDDIG NC • • • • • • Frequency Range: 1.7–2.0 GHz Integrated Baseband Programmable Gain Amplifier On Chip Programmable Baseband Filter High Cascaded IP3: 21 dBm at 1.9 GHz High IP2: 60 dBm at 1.9 GHz Hardware and Software Power Down 3-Wire Serial Programmable Interface Single Supply: 4.5 V to 5.5 V Operation NC • • DATA 1 30 kW DESCRIPTION The TRF3710 is a highly linear and integrated direct-conversion Quadrature Demodulator optimized for Third-Generation (3G) wireless infrastructure. The TRF3710 integrates balanced I and Q mixers, LO buffers and phase splitters to convert an RF signal directly to I and Q baseband. The on-chip Programmable-Gain Amplifiers allow adjustment of the output signal level without the need for external variable-gain (attenuator) devices. The TRF3710 integrates programmable baseband low-pass filters that attenuate nearby interference, eliminating the need for an external baseband filter. Housed in a 7X7mm QFN package, the TRF3710 provides the smallest and most integrated receiver solution available for high performance equipment. AVAILABLE DEVICE OPTIONS (1) PRODUCT PACKAGE LEAD PACKAGE DESIGNATOR (1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKINGS TRF3710 QFN-48 RGZ –40°C to 85°C TRF3710 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TRF3710IRGZR Tape and Reel, 2500 TRF3710IRGZT Tape and Reel, 500 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TRF3710 www.ti.com SLWS199 – AUGUST 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM Decoupling required VCCDIG 2 VCCMIX 4 and 9 VCCBIAS 21 VCCBBQ 25 VCCBBI 36 VCCLO 29 OutBuffer VCCs PGA Gnds GNDDIG 1 GNDBIAS 22 AGND 26 AGND 35 DC Offset Cancel PGA Fast Gain Control 0° 90° MIXinp 6 MIXinn 7 SPI DC Offset Cancel PGA 33 BBIoutn 34 BBIoutp 37 VCMI 38 VOFFI 48 CLOCK 47 DATA 46 STROBE 23 VOFFQ 24 VCMQ 27 BBQoutn 28 BBQoutp OutBuffer 40 41 39 Gain_B2 Gain_B1 Gain_B0 30 31 Power Down LOin 3 LOip CE VCMI Gain_B2 VOFFI Gain_B0 Gain_B1 NC NC MIXIoutp MIXIoutn DATA STROBE CLOCK RGZ Package (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 36 VCCBBI GNDDIG 1 VCCDIG 2 35 AGND CHIP_EN 3 34 BBIoutp VCCMIX 4 33 BBIoutn NC 5 32 NC MIXinp 6 31 LOip MIXinn 7 30 LOin NC 8 29 VCCLO VCCMIX 9 28 BBQoutp NC 10 27 BBQoutn NC 11 26 NC 25 12 13 14 15 16 17 18 19 20 21 22 23 24 2 Submit Documentation Feedback AGND VCCBBQ VCMQ VOFFQ GNDBIAS REXT VCCBIAS NC NC MIXQoutn MIXQoutp NC NC NC TRF3710 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 TRF3710 www.ti.com SLWS199 – AUGUST 2007 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION GNDDIG 1 VCCDIG 2 Digital ground, grounds can be tied together. CHIP_EN 3 VCCMIX 4 MIXinp 6 I Mixer input: positive terminal, connected to external balun; balun type is frequency specific. MIXinn 7 I Mixer input: negative terminal, connected to external balun; balun type is frequency specific. Digital power supply, 4.5 V to 5.5 V. Decoupled from other sources. I Chip enable, enabled = logic level 1, disabled = logic level 0 Mixer power supply, 4.5 V to 5.5 V. Decoupled from other sources. VCCMIX 9 MIXQoutp 16 O Mixer power supply, 4.5 V to 5.5 V. Decoupled from other sources. Mixer Q output: positive terminal (test pin), NC for normal operation. MIXQoutn 17 O Mixer Q output: negative terminal (test pin), NC for normal operation. REXT 20 O Reference-bias external resistor: 30 kΩ; used to set the bias of internal circuits of chip VCCBIAS 21 GDNBIAS 22 VOFFQ 23 I Q-chain Analog-offset correction input, 0 V to 3 V. VCMQ 24 I Baseband Q chain input common mode, nominally 1.5 V. VCCBBQ 25 Baseband Q chain power supply, 4.5 V to 5.5 V. Decoupled from other sources. AGND 26 Analog ground; grounds can be tied together. BBQoutn 27 O Baseband Q output: negative terminal. BBQoutp 28 O Baseband Q output: positive terminal. VCCLO 29 LOin 30 I Local Oscillator input: negative terminal. LOip 31 I Local Oscillator input: positive terminal. BBIoutn 33 O Baseband I output: negative terminal. BBIoutp 34 O Baseband I output: positive terminal. AGND 35 VCCBBI 36 VCMI 37 I Baseband I chain input common mode, nominally 1.5 V. VOFFI 38 I I-chain Analog-offset correction input, 0 V to 3 V. Gain_B2 39 I PGA fast gain control bit 2 Gain_B1 40 I PGA fast gain control bit 1 Gain_B0 41 I PGA fast gain control bit 0 MIXIoutn 44 O Mixer I output: negative terminal (test pin), NC for normal operation. MIXIoutp 45 O Mixer I output: positive terminal (test pin), NC for normal operation. STROBE 46 I SPI enable (latches data into SPI after final clock pulse. Logic level = 1) DATA 47 I SPI data input (programming data for baseband filter frequency setting, PGA gain settings and dc offset calibration). CLOCK 48 I SPI clock input Bias-block power supply, 4.5 V to 5.5 V. Decoupled from other sources. Bias-block ground; grounds can be tied together. Local Oscillator power supply, 4.5 V to 5.5 V. Decoupled from other sources. Analog ground; grounds can be tied together. Baseband I power supply, 4.5 V to 5.5 V. Decoupled from other sources. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 3 TRF3710 www.ti.com SLWS199 – AUGUST 2007 THERMAL CHARACTERISTICS Over operating free-air temperature range (unless otherwise noted) PARAMETER (1) TEST CONDITIONS MIN TYP Soldered slug, no airflow θJA Thermal derating, junction-to-ambient θJA (2) θJB (1) (2) Thermal derating, junction-to-board MAX UNIT 26 Soldered slug, 200-LFM airflow 20.1 Soldered slug, 400-LFM airflow 17.4 7 × 7 mm 48 pin PDFP 25 7 × 7 mm 48 pin PDFP 12 °C/W Determined using JEDEC standard JESD-51 with High K board 16 layers, high-K board ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT Supply voltage range (2) –0.3 to 5.5 V Digital I/O voltage range –0.3 to VCC + 0.5 V TJ Operating virtual junction temperature range –40 to 150 °C TA Operating ambient temperature range –40 to 85 °C Tstg Storage temperature range –65 to 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted) VCC Power supply voltage MIN NOM MAX 4.5 5 5.5 UNIT V 940 μVpp TA Operating ambient temperature range -40 85 °C TJ Operating virtual junction temperature range -40 150 °C MAX UNIT Power supply voltage ripple ELECTRICAL CHARACTERISTICS Power supply = 5.0 V, LO = 0 dBm at 25°C (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP DC PARAMETERS ICC Total supply current 360 mA Power down current 5 mA IQ DEMODULATOR AND BASEBAND SECTION fRF Frequency range GminBB Minimum gain GmaxBB Maximum gain 1700 43 Gain range NFBB IIP3BB (1) (2) (3) (4) 4 22 (2) Gain step See Noise figure Gain setting = 15 rd 3 order input intercept point 2000 dB 45 dB 24 dB 1 Gain setting = 15 13.5 (3) (4) 21 MHz 20 dB 14.5 dB dBm Balun used for measurements: Band 1:1700 MHz Balun = Murata LDB211G8005C-001, Band 2: 1800 to 1900 MHz Balun = Murata LDB211G9005C-001 Two consecutive gain setting Two CW tones of –30 dBm at ±900-kHz and ±1.7-MHz offset (baseband filter 1-dB cutoff frequency of Min LPF). Two CW tones of –30 dBm at ±2.7-MHz and ±5.9-MHz offset (baseband filter 1-dB cutoff frequency of Max LPF). Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 TRF3710 www.ti.com SLWS199 – AUGUST 2007 ELECTRICAL CHARACTERISTICS (continued) Power supply = 5.0 V, LO = 0 dBm at 25°C (unless otherwise noted) TEST CONDITIONS (1) PARAMETER rd OIP3BB Output 3 intercept point Gain setting = 15; 2 tones 1 VPP each OIP1BB Output compression point 1 tone (6) IIP2BB 2nd order input intercept point Gain setting = 15 (7) fLPF Baseband low pass filter cutoff 1-dB point (8) frequency MIN (5) TYP 3 dBVrms 60 dBm 0.615 1.92 MHz 1 900 kHz 10 1.7 MHz 50 5 MHz dB 60 20 MHz 100 1.92 MHz 1 2.7 MHz Baseband relative attenuation at Max LPF cutoff frequency (9) 5.0 MHz 10 dB 50 20 MHz 100 Baseband filter phase linearity rms phase deviation from linear phase (10) 1.8 Degree Baseband filter amplitude ripple See 0.5 dB 1 kΩ 20 pF (10) Sideband suppression Output load impedance 35 Parallel resistance Parallel capacitance VCM UNIT dBVrms 615 kHz Baseband relative attenuation at Min LPF cutoff frequency (9) MAX 32 Output common mode Measured at I and Q channel baseband outputs 0.7 dB 1.5 4.0 V LOCAL OSCILLATOR PARAMETERS Local oscillator frequency 1700 LO input level LO leakage 2000 0 At MIXinn/p MHz dBm –58 dBm VCC V 0.8 V DIGITAL INTERFACE VIH High-level input voltage 2 VIL Low-level input voltage 0 VOH High-level output voltage VOL Low-level output voltage 5 0.8 × VCC V 0.2 × VCC V (5) (6) (7) Two CW tones at an offset from LO frequency smaller than the baseband filter cutoff frequency. Single CW tone at an offset from LO smaller than the baseband filter cutoff frequency. Two tones at FRF1 = FLO ±900 kHz and FRF2= FLO ±1 MHz; IM2 product measured at 100-kHz output frequency (for Min baseband filter 1-dB cutoff frequency). The 2 tones are at FRF1 = FLO ±2.7 MHz and FRF2 = FLO ±2.8 MHz, and the IM2 product measured at 100 kHz output frequency (for Max baseband filter 1-dB cutoff frequency). (8) Baseband low pass filter 1-dB cutoff frequency is programmable through SPI between Min and Max value. (9) Attenuation relative to passband gain. (10) Across filter passband: 615 kHz (Min baseband filter cutoff frequency) and 1.92 MHz (Max baseband filter cutoff frequency). Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 5 TRF3710 www.ti.com SLWS199 – AUGUST 2007 TIMING REQUIREMENTS Power supply = 5.0 V, LO = 0 dBm at 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(CLK) Clock period 50 ns tsu1 Setup time, data 10 ns th Hold time, data 10 ns tw Pulse width, STROBE 20 ns tsu2 Setup time, STROBE 10 ns tsu1 t(CLK) th st 1 Clock Pulse CLOCK DATA DB0 (LSB) Address Bit 1 DB1 Address Bit 2 DB2 Cmd Bit 3 DB3 Cmd Bit 4 DB29 Cmd Bit 30 DB30 Cmd Bit 31 DB31 (MSB) Cmd Bit 32 tsu2 tw STROBE Figure 1. Serial Programming Timing Diagram 6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 TRF3710 www.ti.com SLWS199 – AUGUST 2007 TYPICAL CHARACTERISTICS VCC = 5 V, TA = 25°C, 1950 MHz, Gain setting = 24 (unless otherwise stated). (CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7) GAIN vs FREQUENCY GAIN vs GAIN STATE 44 45 43 CDMA CDMA 41 43.5 -40°C 39 37 Gain - dB 35 Gain - dB 43 -40°C 42.5 25°C 33 31 29 27 85°C 25 25°C 23 42 21 19 85°C 41.5 1820 1840 1860 1880 1900 1920 1940 f - Frequency - MHz 1960 1980 17 15 2000 0 2 4 6 8 10 Figure 2. IIP3 vs FREQUENCY CDMA 28 25°C 85°C 5.5 V 26 5V 24 IIP3 - dBm IIP3 - dBm 24 WCDMA -40°C 22 20 22 20 4.5 V 18 18 16 16 14 14 12 12 10 1690 1700 1710 1720 10 1730 1740 1750 1760 1770 f - Frequency - MHz 1780 1790 1820 1840 1860 1880 Figure 4. 1900 1920 1940 f - Frequency - MHz 1960 1980 2000 1960 1980 2000 Figure 5. IIP3 vs FREQUENCY IIP3 vs FREQUENCY 30 30 WCDMA 28 26 WCDMA 26 24 85°C 25°C 24 22 IIP3 - dBm IIP3 - dBm 22 IIP3 vs FREQUENCY 24 20 20 18 30 26 28 16 Figure 3. 30 28 12 14 Gain state 25°C -40°C 18 22 85°C 20 18 -40°C 16 16 14 14 12 12 10 1690 1700 1710 1720 1730 1740 1750 1760 1770 1780 1790 f - Frequency - MHz 10 1820 1840 Figure 6. 1860 1880 1900 1920 1940 f - Frequency - MHz Figure 7. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 7 TRF3710 www.ti.com SLWS199 – AUGUST 2007 TYPICAL CHARACTERISTICS (continued) VCC = 5 V, TA = 25°C, 1950 MHz, Gain setting = 24 (unless otherwise stated). (CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7) IIP2 vs FREQUENCY IIP2 vs FREQUENCY 80 78 80 78 76 4.5 V 74 85°C 25°C 72 70 72 68 68 70 IIP2 - dBm IIP2 - dBm 76 74 66 64 -40°C 62 60 58 5.5 V 66 5V 64 62 60 58 56 56 54 54 52 WCDMA 52 50 1690 1700 1710 1720 1730 1740 1750 1760 1770 1780 1790 f - Frequency - MHz 50 1820 WCDMA 1840 1860 1880 1900 1920 1940 f - Frequency - MHz Figure 8. IIP2 vs FREQUENCY IIP2 vs FREQUENCY 85°C 78 76 WCDMA -40°C 76 74 74 25°C 72 72 70 70 IIP2 - dBm IIP2 - dBm 2000 80 78 68 66 64 -40°C 68 66 62 60 60 58 58 56 56 54 WCDMA 52 50 1690 1700 1710 1720 1730 1740 1750 1760 f - Frequency - MHz 52 50 1820 1770 1780 1790 25°C 64 62 54 85°C 1840 1860 Figure 10. 1880 1900 1920 1940 f - Frequency - MHz 1960 1980 2000 Figure 11. OIP3 vs FREQUENCY OIP3 vs FREQUENCY 40 40 CDMA 38 38 25°C 36 WCDMA 25°C 36 85°C 85°C 34 OIP3 - dBVrms 34 OIP3 - dBVrms 1980 Figure 9. 80 32 30 -40°C 28 32 30 26 24 24 22 22 1840 1860 1880 1900 1920 1940 f - Frequency - MHz 1960 1980 2000 -40°C 28 26 20 1820 20 1820 1840 Figure 12. 8 1960 1860 1880 1900 1920 1940 f - Frequency - MHz 1960 1980 2000 Figure 13. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 TRF3710 www.ti.com SLWS199 – AUGUST 2007 TYPICAL CHARACTERISTICS (continued) VCC = 5 V, TA = 25°C, 1950 MHz, Gain setting = 24 (unless otherwise stated). (CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7) OIP3 vs GAIN STATE OIP3 vs GAIN STATE 40 40 WCDMA 38 25°C 36 85°C 34 OIP3 - dBVrms 34 OIP3 - dBVrms CDMA 38 25°C 36 32 30 -40°C 28 32 85°C 30 28 26 26 24 24 22 22 20 -40°C 20 0 5 10 15 Gain State 20 25 0 30 5 10 Figure 14. OIP3 vs LO POWER 30 4 6 IIP3 vs LO POWER WCDMA WCDMA 30 35 25 IIP3 - dBm OIP3 - dBVrms 25 35 40 30 20 25 15 20 10 -4 -2 0 LO Power - dBm 2 4 5 -6 6 -4 -2 Figure 16. 0 LO Power - dBm 2 Figure 17. IIP2 vs LO POWER GAIN ERROR vs GAIN STATE 75 70 20 Figure 15. 45 15 -6 15 Gain State 0.018 WCDMA 1850 MHz 0.016 65 0.014 60 0.012 Gain Error - dB IIP2 - dBm 55 50 45 40 35 0.01 0.008 0.006 0.004 30 25 0.002 20 0 15 -6 -0.002 -4 -2 0 LO Power - dBm 2 4 6 0 5 10 15 20 25 Gain State Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 9 TRF3710 www.ti.com SLWS199 – AUGUST 2007 TYPICAL CHARACTERISTICS (continued) VCC = 5 V, TA = 25°C, 1950 MHz, Gain setting = 24 (unless otherwise stated). (CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7) GAIN vs BASEBAND FREQUENCY 60 GAIN vs BASEBAND FREQUENCY 42.6 Filter Gain Shape 25°C, (1.92 MHz) BB Filter Setting = 7 40 Filter Gain Shape 25°C, (1.92 MHz) BB Filter Setting = 7 42.5 42.4 42.3 0 Gain - dB Gain - dB 20 Filter Gain Shape 25°C, (615 KHz) BB Filter Setting = 90 -20 Filter Gain Shape 25°C, (615 KHz) BB Filter Setting = 90 42.2 42.1 42 41.9 -40 41.8 -60 41.7 -80 0.01 0.1 1 10 41.6 0.01 100 0.1 Base Band Frequency - MHz 1 10 Base Band Frequency - MHz Figure 20. Figure 21. CORNER FREQUENCY vs BB - FREQUENCY SETTING INTEGRATED NF vs GAIN STATE 30 3 CDMA Mode 1950 MHz 25°C 1-dB_5 V_25°C_1950 MHz 2.5 4.5 V Noise Figure - dB f - Frequency - MHz 25 2 1.5 1 20 5.5 V 15 5V 0.5 10 0 0 16 32 48 64 80 96 112 0 128 5 10 15 20 25 Gain State BB - Frequency Setting Figure 22. Figure 23. INTEGRATED NF vs GAIN STATE 30 CDMA Mode 1950 MHz 5V Noise Figure - dB 25 85°C 20 25°C -40°C 15 10 0 5 10 15 20 25 Gain State Figure 24. 10 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 TRF3710 www.ti.com SLWS199 – AUGUST 2007 TYPICAL CHARACTERISTICS HISTOGRAM PLOTS CONVERSION GAIN DISTRIBUTION IIP3 DISTRIBUTION 80 60 CDMA 50 WCDMA 60 Distribution - % Distribution - % 40 30 20 40 20 10 0 42.6 42.8 43 43.2 43.4 43.6 0 18.5 43.8 19 19.5 20 Gain - dB Figure 25. 20.5 21 21.5 IIP3 - dBm 22 22.5 23 Figure 26. IIP2 DISTRIBUTION OIP3 DISTRIBUTION 40 35 CDMA CDMA 30 WCDMA WCDMA 30 Distribution - % Distribution - % 25 20 20 15 10 10 5 0 54 58 62 66 70 IIP2 - dBm 74 78 0 29 82 30 31 Figure 27. 32 33 OIP3 - dBVrms 34 35 36 Figure 28. NF DISTRIBUTION 70 60 Distribution - % 50 40 30 20 10 0 12.75 13 13.25 13.5 NF - dB 13.75 14 14.25 Figure 29. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 11 TRF3710 www.ti.com SLWS199 – AUGUST 2007 SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION The TRF3710 features a 3-wire serial programming interface (SPI) that controls an internal 32-bit shift register. There are a total of 3 signals that need to be applied: the CLOCK (pin 48), the serial DATA (pin 47) and the STROBE (pin 46). The DATA (DB0-DB31) is loaded LSB first and is read on the rising edge of the CLOCK. The STROBE is asynchronous to the CLOCK and at its rising edge the data in the shift register gets loaded onto the selected internal register. The first two bits (DB0-DB1) are the address to select the available internal registers. tsu1 t(CLK) th st 1 Clock Pulse CLOCK DATA DB0 (LSB) Address Bit 1 DB1 Address Bit 2 DB2 Cmd Bit 3 DB3 Cmd Bit 4 DB29 Cmd Bit 30 DB30 Cmd Bit 31 DB31 (MSB) Cmd Bit 32 tsu2 tw STROBE Figure 30. Serial Interface Timing 12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 TRF3710 www.ti.com SLWS199 – AUGUST 2007 Register 0 Register Address Bit0 Bit1 PWD Mixer PWD LO Buff PWD Test Buff PWD Filter PWD Output Buff RSVD PWD Dig Cal Block PWD Ana Cal Block Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Baseband Freq Cutoff Settings Cont. Bit16 Bit17 Bit18 Bit19 Bit20 RSVD Bit21 Bit22 Bit23 Bit10 DC Detector Bandwidth Bit24 BB Freq Cutoff Set Baseband Gain Setting Bit25 Bit11 Bit12 RSVD Bit26 Bit27 Bit28 Bit13 Bit14 Bit15 Cal Reset Spare Spare Bit29 Bit30 Bit31 Figure 31. Register 0 MapFigure Table 1. Register 0: Device Setup REGISTER 0 NAME RESET VALUE WORKING DESCRIPTION Bit0 ADDR_0 0 Address bits Bit1 ADDR_1 0 Bit2 PWD_MIX 0 Mixer Power Down (off = 1) Bit3 PWD_LO 0 LO buffer Power Down (off = 1) Bit4 PWD_BUF1 1 Test buffer Power Down (off = 1) Bit5 PWD_FILT 0 Baseband Filter Power Down (off = 1) Bit6 PWD_BUF2 0 Output buffer Power Down (off = 1) Bit7 Reserved 0 Bit8 PWD_DC_OFF_DIG 1 Digital Calibration Blocks Power Down (off = 1) Bit9 PWD_DC_OFF_ANA 1 Analog calibration Blocks Power Down (off = 1) Bit10 BBGAIN_0 1 Bit11 BBGAIN_1 1 Bit12 BBGAIN_2 1 Sets baseband gain; the default power on setting = 15 (typ gain = 34 dB) Example: There are 25 gain settings (0 to 24) in 1 dB increments. Setting gain to 27 dB use this equation Gain Setting Max -(typical gain - gain wanted) = New Gain Setting. So 24-(43 dB-27 dB) = 8 which would be from bit 10 to bit 14 <00010>. Bit13 BBGAIN_3 1 Bit14 BBGAIN_4 0 Bit15 BBFREQ_0 1 Bit16 BBFREQ_1 0 Bit17 BBFREQ_2 1 Bit18 BBFREQ_3 0 Bit19 BBFREQ_4 1 Bit20 BBFREQ_5 0 Bit21 BBFREQ_6 1 Bit22 Reserved 1 Bit23 Reserved 0 Bit24 EN_FLT_B0 0 Bit25 EN_FLT_B1 0 Bit26 Reserved 0 Bit27 Internal use only 0 Bit28 Internal use only 0 Bit29 CAL_RESET 0 Bit30 Spare<0> 0 Bit31 Spare<1> 0 Sets BB Freq cutoff; default = 85. Example: For CDMA, the corner frequency is 615 kHz. Refer to the 1dB Frequency vs. BBFREQ Setting plot to determine the setting, which is 90. Then set Bit 15 through Bit 21 to <1011010> which corresponds to 90. DC detector bandwidth Reset the internal calibration logic when = 1 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 13 TRF3710 www.ti.com SLWS199 – AUGUST 2007 • • • 14 Baseband PGA gain: BBGAIN_<4,0> (B<14,10>) sets the gain of the baseband programmable gain amplifier. The acceptable values are from <00000> to <11000> (Refer to Gain Control paragraph, under the Application Information section, for more information) Baseband filter cutoff frequency: BBFREQ_<6,0> (B<21,15) controls the baseband 1-dB cutoff frequency. An all 0's word sets the filter to its maximum cutoff frequency, while all 1's correspond to minimum filter bandwidth. EN_FLT_B0/1: these bits control the bandwidth of the detector used to measure the dc offset during the automatic calibration. There is an RC filter in front of the detector, that can be fully bypassed. EN_FLT_B0 controls the resistor (bypass = 1), while EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dB cutoff frequencies of the detector bandwidth are summarized in the following table (see Application Information section for more detail on the dc offset calibration and the detector bandwidth). EN_FLT_B1 EN_FLT_B0 Typical 3 dB Cutoff Freq. X 0 10 MHz Maximum bandwidth Bypass R, C 0 1 10 kHz Enable R 1 1 1 kHz Minimum BW, Enable R, C Notes Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 TRF3710 www.ti.com SLWS199 – AUGUST 2007 Register 1 Register Address Bit0 Bit1 Auto Cal Enable Autocal Bit2 Bit3 DAC Bits CONT Bit16 Bit17 DAC Bits To Be Set During Manual Cal I/Q Bit4 Bit5 Bit6 DC Offset Digital Cal. Resolution for I Channel Bit18 Bit19 Bit20 Bit21 Bit7 DC Offset Digital Cal. Resolution for Q Channel Bit22 Bit23 Bit8 Bin Search Bit24 Bit9 Bit10 Bit11 Division Ratio for Clock Divider Bit25 Bit26 Bit27 Bit12 Cal Clk Select Bit28 Bit13 Bit14 Bit15 Internal Osc Freq Trimming Bit29 Bit30 Bit31 Figure 32. Register 1 MapFigure Table 2. Register 1: Device Setup REGISTER 1 NAME RESET VALUE WORKING DESCRIPTION Bit0 ADDR_0 1 Bit1 ADDR_1 0 Bit2 AUTO_CAL 1 Auto dc offset correction when = 1, otherwise manual Bit3 EN_AUTOCAL 0 Auto cal begins when bit= 1, is reset after completion of cal Bit4 IDAC_BIT0 0 Bit5 IDAC_BIT1 0 Bit6 IDAC_BIT2 0 Bit7 IDAC_BIT3 0 Bit8 IDAC_BIT4 0 Bit9 IDAC_BIT5 0 Bit10 IDAC_BIT6 0 Bit11 IDAC_BIT7 1 Bit12 QDAC_BIT0 0 Bit13 QDAC_BIT1 0 Bit14 QDAC_BIT2 0 Bit15 QDAC_BIT3 0 Bit16 QDAC_BIT4 0 Bit17 QDAC_BIT5 0 Bit18 QDAC_BIT6 0 Bit19 QDAC_BIT7 1 Bit20 IDET_B0 1 Bit21 IDET_B1 1 Bit22 QDET_B0 1 Bit23 QDET_B1 1 Bit24 Bin Search 1 Bit25 CLK_DIV_RATIO<0> 0 Bit26 CLK_DIV_RATIO<1> 0 Bit27 CLK_DIV_RATIO<2> 0 Bit28 CAL_CLK_SEL 1 Bit29 OSC_TRIM<0> 1 Bit30 OSC_TRIM<1> 1 Bit31 OSC_TRIM<2> 0 Address bits DAC bits to be set during manual cal I/Q Set the dc offset digital calibration resolution for I channel. Set the dc offset digital calibration resolution for Q channel. Set to 1 for Auto-Calibration; Set to 0 for Manual control. DC offset auto-calibration clock divider: division ratios = 1, 8, 16, 128, 256, 1024, 2048, 16684 Select internal oscillator when 1, SPI clk when 0 Internal Oscillator frequency trimming 000 => 300 kHz 111 => 1.8 MHz Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 15 TRF3710 www.ti.com SLWS199 – AUGUST 2007 • • • • • • 16 AUTO_CAL (bit2): when 1, the dc offset auto calibration is selected. EN_AUTOCAL (bit3): setting this bit to 1 starts the dc offset auto-calibration. At the end of the calibration, the bit is reset to 0 (see Application Information for more details on dc offset correction). IDET_B<1,0>, QDET_B<1,0>: These bits control the maximum output dc voltage of the dc-offset correction DAC (I and Q channel). CLK_DIV_RATIO <2,0>: Frequency divider for the Cal Clock. The incoming clock (either the Serial Interface Clock or the internal oscillator) divided by the divider ratio set by Bits 25–27, generate the reference clock used during the auto-calibration. CAL_CLK_SEL: selects the internal oscillator or the external SPI clock as calibration clock. OSC_TRIM<2,0>: Bits 29–31 control the internal oscillator frequency. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 TRF3710 www.ti.com SLWS199 – AUGUST 2007 Register 2 Register Address I Mixer Offset Side A Bit0 Bit1 Bit2 Bit16 Bit17 Bit18 Bit3 Bit4 Bit5 Bit6 I Mixer Offset Side B Bit7 Bit8 Q Mixer Offset Side A Bit19 Bit20 Bit9 Bit10 Bit11 Bit12 Bit13 Q Mixer Offset Side B Bit21 Bit22 Bit23 Bit24 Bit25 Bit26 Bit27 Bit28 Bit29 Bit14 Bit15 Spare Spare Bit30 Bit31 Figure 33. Register 2 MapFigure Register 2: Device Setup REGISTER 2 NAME RESET VALUE Bit0 ADDR_0 0 Bit1 ADDR_1 1 Bit2 loffa_0 0 Bit3 loffa_1 0 Bit4 loffa_2 0 Bit5 loffa_3 0 Bit6 loffa_4 0 Bit7 loffa_5 0 Bit8 loffa_6 0 Bit9 loffb_0 0 Bit10 loffb_1 0 Bit11 loffb_2 0 Bit12 loffb_3 0 Bit13 loffb_4 0 Bit14 loffb_5 0 Bit15 loffb_6 0 Bit16 Qoffa_0 0 Bit17 Qoffa_1 0 Bit18 Qoffa_2 0 Bit19 Qoffa_3 0 Bit20 Qoffa_4 0 Bit21 Qoffa_5 0 Bit22 Qoffa_6 0 Bit23 Qoffb_0 0 Bit24 Qoffb_1 0 Bit25 Qoffb_2 0 Bit26 Qoffb_3 0 Bit27 Qoffb_4 0 Bit28 Qoffb_5 0 Bit29 Qoffb_6 0 Bit30 Spare<0> 0 Bit31 Spare<1> 0 WORKING DESCRIPTION Address bits I mixer offset side A I mixer offset side B Q mixer offset side A Q mixer offset side B Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 17 TRF3710 www.ti.com SLWS199 – AUGUST 2007 APPLICATION INFORMATION GAIN CONTROL The TRF3710 integrates a base band Programmable Gain Amplifier (PGA) that provides 24 dB of gain range with 1 dB steps. The PGA gain is controlled through SPI by a 5-bit word (register 0 bits<10,14>). Alternatively, the PGA can be programmed by a combination of 5 bits programmed through the SPI and 3 parallel external bits (pins Gain_B2, Gain_B1, Gain_B0). This allows a fast gain change (0 to 7 dB by 1 dB step) without the need to reprogram the SPI registers. The PGA gain control word (BBgain<0,4>) can be programmed to a setting between 0 and 24. This word is the sum of the SPI programmed gain (register 0 bits<10,14>) and the parallel external 3 bits as shown in Figure 34. Setting the PGA gain setting above 24 is not valid. Typical applications will set the PGA gain setting to 15 which allows room to adjust the PGA gain up or down to maintain desired output signal to the Analog-to-Digital Converter over all conditions. From Register1 SPI_BBgain<0,4> + BBgain<0,4> To PGA Fgain<0,2> From External Pins Figure 34. PGA Gain Control Word For example, if a PGA gain setting of 20 dB is desired, then the SPI can be programmed directly to 20. Alternatively, the SPI gain register can be programmed to 15 and the parallel external bits set to 101 (binary) corresponding to an additional 5 dB. AUTOMATED DC OFFSET CALIBRATION The TRF3710 provides an automatic calibration procedure for adjusting the DC offset in the base band I/Q paths. The digital DC offset correction is engaged by setting the PWD_DC_OFF_DIG (register 0, bit 8) to “0” and the PWD_DC_OFF_ANA (register 0, bit 9) to “1”. The internal calibration requires a clock in order to function. TRF3710 can use the internal relaxation oscillator or the external SPI clock. Using the internal oscillator is the preferred method which is selected by setting the Cal_Sel_Clk (register 1, bit 28) to “1”. The internal oscillator frequency is set through the Osc_Trim bits (register 1, bits 29-31). The frequency of the oscillator is detailed in Table 3. Table 3. Internal Oscillator Frequency Control Osc_Trim <2> Osc_Trim <1> Osc_Trim <0> Frequency 0 0 0 300 kHz 0 0 1 500 kHz 0 1 0 700 kHz 0 1 1 900 kHz 1 0 0 1.1 MHz 1 0 1 1.3 MHz 1 1 0 1.5 MHz 1 1 1 1.8 MHz The default setting of these registers corresponds to 900 kHz oscillator frequency; this is sufficient for auto-calibration and does not need to be modified. The internal DC offset correction DACs output full scale range is programmable (IDET_B0,<1> and QDET_B0,<1>, register 1 bit20,<23>). The range is shown in Table 4. 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 TRF3710 www.ti.com SLWS199 – AUGUST 2007 Table 4. DC Offset Correction DAC Programmable Range I(Q)DET_B1 I(Q)DET_B0 Full Scale 0 0 10 mV 0 1 20 mV 1 0 30 mV 1 1 40 mV The I and Q channel output maximum DC offset correction range can be calculating by multiplying the values in the table by the base-band PGA gain. The LSB of the digital correction is dependent on the programmed maximum correction range. For optimum resolution and best correction the DC offset DAC range should be set to 10 mV for both the I and Q channel with the PGA gain set for the nominal condition. The DC offset correction DAC output is affected by a change in the PGA gain but if the initial calibration yields optimum results then the adjustment of the PGA gain during normal operation will not significantly impair the DC offset balance. For example, if the optimized calibration yields a DC offset balance of 2 mV at a gain setting of 17, then the DC offset will maintain less than 10 mV balance as the gain is adjusted ±7 dB. The DC offset correction DACs are programmed from the internal registers when the AUTO_CAL bit (register 1, bit 2) is set to 1. At start-up, the internal registers are loaded at half scale corresponding to a decimal value of 128. When an auto calibration is desired, verify that the Bin_Search bit (register 1, bit 24) is set to 1. The auto-cal is initiated by toggling the EN_AUTOCAL bit (register 1, bit 3) to 1. When the calibration is over, this bit is automatically reset to 0. During calibration the RF Local Oscillator must be applied. At each clock cycle during an auto calibration sequence the internal circuitry senses the output DC offset and calculates the new DC current for the DAC. After the 9th clock cycle, the calibration is complete and the AUTO_CAL bit is reset to 0. The DC offset DAC state is stored in the internal registers and maintained as long as the power supply is kept on or until the Cal Reset (register 1, bit 29) is toggled to 1 or a new calibration is started. The required clock speed for the optimum calibration is determined by the internal detector behavior (integration bandwidth, gain, sensitivity). The input bandwidth of the detector can be adjusted by changing the cut-off frequency of the RC low pass filter in front of the detector (register 0, bits 24–25) corresponding to 3 dB corner frequency steps of 10 MHz, 10 kHz, and 1 kHz. The speed of the clock can be slowed down by selecting a clock divider ratio (register 1, bits 25–27). The detector has more averaging time the slower the clock; hence, it can be desirable to slow down the clock speed for a given condition to achieve optimum results. For example, if there is no RF present on the RF input port, the detection filter can be left wide (10 MHz) and the clock divider can be left at div-by-1. The auto-calibration yields a DC offset balance between the differential base band output ports (I and Q) that is less than 15 mV. Some minor improvement may be obtained by increasing the averaging of the detector by increasing the clock divider up to 256. However, if there is a modulated RF signal present at the input port, it is desirable to reduce the detector bandwidth to filter out most of the modulated signal. The detector bandwidth can be set to a 1 kHz corner frequency. With the modulated signal present, and with the detection bandwidth reduced, additional averaging is required to get the optimum results. A clock divider setting of 1024 yields optimum results. An increase in the averaging is possible by increasing the clock divider at the expense of longer converging time. The convergence time can be calculated by the following: (Auto_Cal_Clk_Cycles) (Clk_Divider) tc + Osc_Freq (1) With a clock divider of 1024 and with the nominal oscillator frequency of 900 kHz the convergence time is: Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 19 TRF3710 www.ti.com SLWS199 – AUGUST 2007 tc + (9) (1024) + 10.24 ms 900 kHz (2) ALTERNATE METHOD FOR ADJUSTING DC OFFSET The internal registers controlling the internal DC current DAC are accessible through the SPI, providing a user programmable method for implementing the DC offset calibration. To employ this option the Auto Cal bit must be set to 0 and the Bin_Search set to “0”. During this calibration, an external instrument monitors the output DC offset between the I/Q differential outputs and programs the internal registers (IDAC_BIT0,<7> and QDAC_BIT0,<7> bits, register 1 bit4,<19>) to cancel the DC offset. The TRF3710 also offers a third DC offset calibration option to control the output DC offset by an external voltage (0–3 V) injected at the VOFFI and VOFFQ pins. Set PWD_DC_OFF_DIG (register 0, bit 8) to 1 (Off) and set PWD_DC_OFF_ANA (register 0, bit 9) to 0 to engage the external analog voltage control of the output DC offset. The analog voltage at the VOFFI and VOFFQ pins can be adjusted to provide the proper DC offset balance. PCB LAYOUT GUIDELINES The TRF3710 device is fitted with a ground slug on the back of the package that must be soldered to the PCB ground with adequate ground vias to ensure a good thermal and electrical connection. The recommended via pattern and ground pad dimensions are shown in Figure 35. The recommended via diameter is 8 mils. The ground pins of the device can be directly tied to the ground slug pad for a low inductance path to ground. Additional ground vias may be added if space allows. The NC (No Connect) pins can also be tied to the ground plane. Decoupling capacitors at each of the supply pins is recommended. The high frequency decoupling capacitors for the RF mixers (VCCMIX) should be placed close to their respective pins. The value of the capacitor should be chosen to provide a low impedance RF path to ground at the frequency of operation. Typically this value is around 10 pF or lower. The other decoupling capacitors at the other supply pins should be kept as close to their respective pins as possible. The device exhibits symmetry with respect to the quadrature output paths. It is recommended that the PCB layout maintain that symmetry in order to ensure the quadrature balance of the device is not impaired. The I/Q output traces should be routed as differential pairs and their lengths all kept equal to each other. Decoupling capacitors for the supply pins should be kept symmetrical where possible. The RF differential input lines related to the RF input and the LO input should also be routed as differential lines with their respective lengths kept equal. If an RF balun is used to convert a single ended input to differential input, then the RF balun should be placed close to the device. Implement the RF balun layout per the manufacturer’s guidelines to provide best gain and phase balance to the differential outputs. On the RF traces, maintain proper trace widths to keep the characteristic impedance of the RF traces at a nominal 50 Ω. 20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 TRF3710 www.ti.com SLWS199 – AUGUST 2007 0.200 0.025 Ø 0.008 0.025 0.200 0.0125 Dimensions: inches Figure 35. PCB Layout Guidelines APPLICATION SCHEMATICS The typical application schematic is shown in Figure 36. The RF bypass caps and coupling caps are depicted with 10 pF capacitors. These values can be adjusted to provide the best high frequency bypass based on the frequency of operation. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 21 TRF3710 www.ti.com Gain_B2 Gain_B0 Gain_B1 STROBE SDAT SCLK SLWS199 – AUGUST 2007 C1 0.1 mF 2 0.1 mF CHIP_EN C4 10 pF 10 pF 7 37 VCMI 38 VOFFI 39 Gain_B2 41 40 Gain_B1 NC Gain_B0 42 43 NC 44 MIXIoutn 45 MIXIoutp 46 DATA NC NC U1 TRF3710 MIXinp LOin 8 NC NC AGND 1000 pF 34 BBIP 33 BBIN VCCBBQ To ADC I 32 LOP To SYNTHESIZER LON VCC 30 C8 29 28 BBQP 27 BBQN 10 pF To ADC Q 26 C10 25 VCMQ 1000 pF VCC 24 VOFFQ 23 22 21 20 NC 14 13 NC NC GNDBIAS BBQoutn VCCBIAS NC REXT BBQoutp NC VCCMIX NC 11 12 VCCLO 19 9 10 C2 35 LOip 31 MIXinn 18 10 pF BBIoutn MIXQoutn VCC VCCMIX 17 C9 C7 BBIoutp MIXQoutp LDB21 6 CHIP_EN 16 10 pF 10 pF 36 AGND NC C6 C5 VCC VCCBBI VCCDIG 15 RF in 5 VCC B1 3 4 STROBE VCC CLOCK 48 C3 1 GNDDIG 47 ADC_CM(~1.5V) ADC_CM(~1.5V) R1 30 kW VCC C11 0.1 mF C12 0.1 mF Figure 36. TRF3710 Application Schematics The RF input port and the RF LO port require differential input paths. Single ended RF inputs to these ports can be converted with an RF balun that is centered at the band of interest. Linearity performance of the TRF3710 is dependant on the amplitude and phase balance of the RF balun; hence, care should be taken with the selection of the balun device and with the RF layout of the device. The recommended RF balun devices are listed in Table 5. Table 5. RF Balun Devices MANUFACTURER PART NUMBER FREQUENCY RANGE (MHz) UNBALANCE IMPEDANCE BALANCE IMPEDANCE Murata LDB211G8005C-001 1800 ±100 MHz 50 Ω 50 Ω Murata LDB211G9005C-001 1900 ±100 MHz 50 Ω 50 Ω ADC INTERFACE The TRF3710 has an integrated ADC driver buffer that allows direct connection to an Analog-to-Digital Converter (ADC) without additional active circuitry. The common mode voltage generated by the ADC can be directly supplied to the TRF3710 through the VCMI/Q pins (pins 24, 37). Otherwise, a nominal common mode voltage of 1.5 V should be applied to those pins. The TRF3710 device can operate with a common mode voltage from 1.5 V to 2.8 V without any impairment to the output performance. Figure 37 illustrates the degradation of the output compression point as the common mode voltage exceeds those values. 22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 TRF3710 www.ti.com SLWS199 – AUGUST 2007 3.5 3 P1dB - dBVrms 2.5 2 1.5 1 0.5 0 0.5 1 1.5 2 2.5 3 3.5 VCM - Common Mode Voltage - V Figure 37. P1dB Performance vs Common Mode Voltage APPLICATION FOR A HIGH PERFORMANCE RF RECEIVER SIGNAL CHAIN The TRF3710 is the centerpiece component in a high performance direct down convert receiver. The device is a highly integrated direct down convert demodulator that requires minimal additional devices to complete the signal chain. A signal chain block diagram example is shown in Figure 38. ADS5232 TRF371x 12 0 90 LNA 12 TRF3761 Figure 38. Block Diagram of Direct Down Convert Receiver The lineup requires a Low Noise Amplifier (LNA) that operates at the frequency of interest with typical 1 to 2 dB Noise Figure (NF) performance. An RF band pass filter (BPF) is selected at the frequency band of interest to eliminate unwanted signals and images outside the band from reaching the demodulator. The TRF3710 incorporates the direct down convert demodulation, base band filtering, and base band gain control functions. An external synthesizer, like the TRF3761, is used to provide the Local Oscillator (LO) source to the TRF3710. The differential outputs of the TRF3761 directly mate with LO input of the TRF3710. The quadrature outputs (I/Q) of the TRF3710 directly drive the input to the Analog-to-Digital Converter (ADC). A dual ADC like the ADS5232 12-bit 80 MSPS ADC mates perfectly with the differential I/Q output of the TRF3710. In addition, the common mode output voltage generated by the ADS5232 is fed directly into the common mode ports (pins 24, 37) to ensure the optimum dynamic range of the ADC is maintained. The cascaded performance of the TRF3710 with the ADS5231 and TRF3761 was measured with WCDMA modulated signals. A single channel WCDMA receive signal was injected into the TRF3710 at –100 dBm. This power roughly corresponds to typical levels this device would see at sensitivity when an appropriate LNA and filter are used. The EVM (Error Vector Magnitude) of the RX channel was measured as a gauge of the system performance. The performance at –100 dBm input is shown in Figure 39. The EVM percentage at -100 dBm is approximately 27.6% at 60 ksym/s. This correlates with the required SNR (signal to noise ratio) for the device with appropriate LNA to meet or exceed the BER (Bit Error Rate) specification of 0.1% per the standards at the input sensitivity level. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 23 TRF3710 www.ti.com SLWS199 – AUGUST 2007 Figure 39. WCDMA RX EVM performance of the TRF3710 with ADS5231 and TRF3761 24 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TRF3710 PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TRF3710IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3710IRGZRG4 ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3710IRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3710IRGZTG4 ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TRF3710IRGZR RGZ 48 SITE 60 330 16 7.3 7.3 1.5 12 16 Q2 TRF3710IRGZT RGZ 48 SITE 60 330 16 7.3 7.3 1.5 12 16 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) TRF3710IRGZR RGZ 48 SITE 60 342.9 336.6 28.58 TRF3710IRGZT RGZ 48 SITE 60 342.9 336.6 28.58 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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