UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com 12-V to 100-V Input, 0.2-A Output Switching Converter Check for Samples: UCC25230 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • Highly Integrated Converter Operating as a Buck, or Isolated Forward-Flyback, Flybuck™ Wide Operating Input Voltage Range from 12 V to 100 V, 105-V Surge. Up to 0.2-A Output Current 9-V Always Available VDD Output with up to 2-mA Current Capability Thermally Enhanced 4-mm x 4-mm SON-8/S-PVSON-N8 (DRM) Package Internally Set Fixed 380-kHz Switching Frequency Internal 2-ms Duration Soft Start Voltage Mode Control with Input Feed Forward Allows Optimal Output Filter Design 2% Accuracy Internal 2.5-V Reference VDD UVLO Cycle-by-Cycle Current Limit with Frequency Fold Back for Initial Start up Under High Capacitive Loads Input UVLO and OVLO with Input Good Signal High Density Isolated Standby Bias Supplies DC-to-DC Converters DESCRIPTION The UCC25230 is a highly integrated PWM converter operating as an isolated forward flyback. It has high-side and low-side power switches integrated and the control circuit with all key converter functions included. The power stage requires only one- or multiple winding coupled inductor and output capacitors for the complete solution. Voltage-mode feed-forward control with external compensation allows optimal output filter selection over wide input voltage range. The UCC25230 has fixed frequency set internally at 380 kHz. It also includes input voltage UVLO and OVLO comparators with hysteresis and input-good, open-collector output signal which can be used to enable PWM controllers. UCC25230 is available in a thermally enhanced 8-pin SON package with PowerPad™ serving as a ground pin. Other features include internal soft start and cycle-by-cycle current protection. Measured efficiency of isolated converter over input voltage and output current ranges are shown in Figure 2. Isolated Buck Converter 100 V 2 3 4 VIN VDD BOOT UV/OV PHASE CONTROL 7 COMP VIN_G FB 9 8 8V 100 mA 1 8V 100 mA 6 5 GND PAD 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad, Flybuck are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TEMPERATURE RANGE, TA = TJ -40°C to +125°C PACKAGE SON-8/S-PVSON-N8 (DRM) TAPE AND REEL QTY. PART NUMBER 250 UCC25230DRMT 3000 UCC25230DRMR ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) MIN Supply voltage range, VIN Output voltage on PHASE DC MAX 100 –0.3 VIN + 0.5 -2 VIN + 1 10 Repetitive surge < 200 ms DC Repetitive pulse < 100 ns UNIT -0.3 105 Voltage BOOT with respect to PHASE -0.3 Voltage VDD -0.3 10 Voltage FB, UV/OV, COMP -0.3 VDD Voltage VIN_G -0.3 5.5 ESD rating HBM 2 kV CDM 500 V Sink current PHASE (peak) 220 (internally limited) Source current PHASE (peak) -220 (internally limited) Operating virtual junction temperature range, TJ -40 150 Operating ambient temperature range, TA -40 125 Storage temperature, TSTG -65 150 Lead temperature (soldering, 10 sec.) (1) (2) 2 V mA °C 300 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Databook for thermal limitations and considerations of packages. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com THERMAL INFORMATION UCC25230 THERMAL METRIC (1) DRM UNITS 8 PINS Junction-to-ambient thermal resistance (2) θJA 33.9 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 11.4 ψJT Junction-to-top characterization parameter (5) 0.4 ψJB Junction-to-board characterization parameter (6) 11.7 θJCbot Junction-to-case (bottom) thermal resistance (7) 2.3 (1) (2) (3) (4) (5) (6) (7) 33.2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER Supply voltage range, VIN MIN TYP 12 Supply bypass capacitor, CVIN MAX 48 UNIT 75, (100 V for 1 ms) 1.0 Supply bypass capacitor, CVDD 0.1 Operating junction temperature range -40 1.0 2.2 +125 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 V μF °C 3 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VIN = 48 V, 1-µF capacitor from VIN to GND, 1-µF capacitor from VDD to GND, TA = TJ = -40°C to 125°C, (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNITS Supply Currents IVIN Quiescent current VIN = 5 V 0.5 2 IVINO VIN operating current FB = COMP 4.5 10 9 9.54 mA VDD Regulator VDD VDD, output voltage 8.46 Line regulation 17 V < VIN < 75 V ±5 ±40 Load regulation -2 mA < IVDD < 0 mA ±5 ±40 -2 -6 -13 VDD current limit (when VDD = 5.5 V) V mV mA Internal Undervoltage Lockout (VDD_UVLO) VDDrising VDD rising threshold 7.0 7.5 8 VDDhyst VDD threshold hysteresis 0.4 0.7 1.1 6.3 6.8 7.3 0.9 1.0 1.1 V 7 11 18 µA VDDfalling VDD falling threshold V Undervoltage (external programmable) Falling threshold Ihyst Overvoltage (external programmable) OVLO Rising threshold 4.5 5 5.5 V Ihyst -15 -22 -40 μA 50 100 Ω 380 445 kHz VIN Power GOOD PG output sink resistance IPG = 5 mA to 10 mA Oscillator f Oscillator frequency fixed DCMIN Minimum duty cycle FB = 3.0 V DCMAX Maximum duty cycle FB = 2.0 V Frequency variation 12 V < VIN < 75 V 4 324 Submit Documentation Feedback 0% 85% -15% 15% Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 48 V, 1-µF capacitor from VIN to GND, 1-µF capacitor from VDD to GND, TA = TJ = -40°C to 125°C, (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNITS Error Amplifier REF voltage Avol FB = COMP, (T = 25°C) 2.42 2.50 2.58 FB = COMP, (T = -40 to 125°C) 2.40 2.50 2.60 40 80 Avol open loop voltage gain dB ±2 Input leakage current, FB V ICOM(sink) COMP sink current VCOMP = 4.5 V 2 4.8 10 ICOM(sourc COMP source current VCOMP = 4.5 V -2 -6.1 -12 VOL COMP voltage range ICOMP = 100 µA .4 1.2 VOH COMP voltage range ICOMP = -100 µA VDD-1.2 VDD-0.7 VDD Time for COMP to ramp FB = COMP 1.75 2.05 2.35 RDS(on) high VIN = 48 V 6 15 RDS(on) low VIN = 48 V 5 10 µA mA e) V Soft Start ms Output Max average current 200 Ω mA ILIMIT (1) ILIMIT phase high VIN = 30 V Propagation delay, blanking delay plus ILIMIT delay ILIMIT phase low VIN = 30 V Propagation delay, blanking delay plus ILIMIT delay (2) (1) (2) -600 -400 -220 60 100 140 220 400 600 60 100 140 mA ns mA ns Continued operation while in ILIM could exceed the maximum power dissipation for the device. For Non-Isolated applications additional external over current protection may be required. Specified by design, not production tested. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 5 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com DEVICE INFORMATION Figure 1. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION PHASE 1 O Phase output of high-side and low-side power FETs. BOOT 2 I 0.1-µF capacitor connected between BOOT and PHASE pins along with the internal diode between BOOT and VDD provides supply voltage to the drive circuit of the upper power FET. UV/OV 3 I Input to internal comparators. Internal linear regulator remains functional. A bypass cap of at least 1000 pF is recommended. VIN_G 4 O VIN power good. Open drain output, state determined by UV/OV pin. FB 5 I Error amplifier inverting input. Connect to output voltage divider with compensation circuit to this pin. COMP 6 O Output of error amplifier. VDD 7 O Output of internal linear regulator. Bypass VDD pin to GND pins close to device package with a high quality, low ESR 1-µF ceramic capacitor. VIN 8 I Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to GND pins close to device package with a high quality, low ESR 1-µF ceramic capacitor. GND PAD 9 - Thermal ground pad and electrical ground for the device. 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com Detailed Pin Description PHASE (pin 1): Output of the internal high and low sides of the internal synchronous FETS. This output drives the external power inductor, or primary side of a coupled inductor for multiple outputs. BOOT (pin 2): Connect a 0.1-µF capacitor between the BOOT pin and the PHASE pin. This provides the necessary level shift voltage to drive the internal upper FET gate. UV/OV (pin 3): Input to the internal window comparator with a 1-V and 5-V reference. The input to the UV/OV pin determines the state of the open drain output of VIN_G. This does not determine the operating range of the UCC25230. A bypass cap at least 1000 pF is recommended for noise immunity. VIN_G (pin 4): Open drain output of The UCC25230’s internal comparator. The output state is determined by the voltage on the UV/OV pin. The UCC25230 will continue to function regardless of the state of this pin. Used for controlling external circuitry. Maximum voltage to this pin is 5.5 V. FB (pin 5): FB is the inverting input of the UCC25230’s internal error amplifier. Connect the output voltage sensing divider to this pin. Internal reference is 2.5 V on the non inverting input. ææ V ö ö R2 = ç ç OUT ÷ - 1÷ ´ R1 è è 2.5 ø ø (1) COMP (pin 6): The COMP pin is the internal error amplifier’s output. The voltage range of COMP is 0 V to 8.3 V. At steady state, a higher COMP pin voltage results in a larger duty cycle. Add compensation components between this pin and FB. VDD (pin 7): This is the 9-V output of the UCC25230’s internal voltage regulator. This output may be used for powering additional circuitry, up to a current of 2 mA, depending on the voltage on the VIN pin. Care must be taken not to exceed the devices total power dissipation. VIN (pin 8): This is the voltage input pin for the UCC25230. It supplies the internal voltage regulator and output switches. Bypass this pin with at least 1-µF low ESR capacitor. GND PAD (pin 9): GND PAD is the ground reference for the whole device. Tie all signal returns to this point. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 7 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com Functional Block Diagram BOOT 2 UV/OV COMP + – 5V + – + VIN_G 4 22 mA 1V + – + – + 3 UV/OV 8 VIN 1 PHASE 11 mA VDD UVLO COMP 7 + VDD Regulator 7.5 V 0.7-V Hyst. + – EN REF EN Feedforward COMP 6 FB 5 EA REF + + PWM Block Logic Block Level Shifter 2.5 V + – Oscillator SS Two -Way Cycle -by-cycle Current Limit 9 GND PAD 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS EFFICIENCY vs OUTPUT POWER OSCILLATOR CHANGE vs TEMPERATURE 100 393 91 81 392 Frequency (kHz) Efficiency (%) 71 61 51 41 391 390 31 21 389 36 V 48 V 80 V 11 1 0.0 0.5 1.0 Output Power (W) −40 1.5 25 Temperature (°C) 90 G000 Figure 2. Figure 3. OSCILLATOR CHANGE vs INPUT VOLTAGE SOFT-START TIME vs TEMPERATURE 400 2.1 395 2.075 Time (s) Frequency (kHz) G000 390 385 380 125 2.05 2.025 20 30 40 50 Input Voltage (V) 60 2 −40 70 25 Temperature (°C) 90 G000 Figure 4. 125 G000 Figure 5. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 9 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VDD CHANGE vs TEMPERATURE 9.11 9.10 Voltage (V) 9.09 9.08 9.07 9.06 9.05 −40 25 Temperature (°C) 90 125 G000 Figure 6. 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com APPLICATION INFORMATION Detailed Description The UCC25230 PWM converter integrates all necessary functions to operate as an isolated auxiliary bias supply. It is capable of operating from an input voltage range of 12 V to 100 V (up to 105-V surge), making it ideal for usage in 24-V or 48-V input telecom applications. High-side and low-side power switches are integrated and provide up to 200 mA of peak output current. The UCC25230 is an ideal, complementary solution to primary-side or secondary-side PWM control methodologies as it provides bias voltages necessary for PWM controllers and/or external peripheral circuitry. UCC25230 is capable of delivering a primary-side and/or secondary-side bias voltage for power supplies. As such, UCC25230 is optimized for Texas Instruments’ family of UCD3k digital and analog PWM controllers as well as the C2000 family of microcontrollers. UCC25230 operates using Texas Instruments’ Flybuck™ Topology, which simplifies design versus a traditional flyback topology. FlybuckTM Topology allows a synchronous buck–like design methodology. It also enables a significant reduction in external parts count, and also allows usage of a small 2-winding transformer. The Flybuck™ Topology does not require a third transformer winding or opto-isolator for regulation. Circuits employing extra transformer windings compromise dynamic response, and add to the transformer’s physical size and cost. The Flybuck™ is a portmanteau of flyback and buck since the transformer is connected as a flyback converter and the input to output voltage relationship is similar to a buck derived converter. Typically, an auxiliary bias supply must be designed such that it is the first device in the system to power up, and be the very last device, in the system, to power down. It must be a robust supply, being able to ride through any fault conditions (OV, UV, OTP, etc) and it also must not prematurely shut down the entire power supply. The UCC25230 was designed with these goals in mind: • A 2-ms soft start ensures a smooth, monotonic startup on both primary and secondary-side voltages. • Voltage mode with input voltage feedforward allows optimal output filter design. • Cycle-by-cycle current limit with frequency foldback permits startup under high-capacitive loading. • Programmable UV/OV detection circuit. • A VIN_G fault output provides a fast propagation open drain signal to indicate when an overvoltage or undervoltage condition has been detected. The UCC25230 is specifically designed to remain operational when a fault is detected in order to allow for fast external shutdown. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 11 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com Operation of the Flybuck™ Converter Figure 7 shows a simplified schematic and the two primary operational states of the Flybuck converter. The power supply is a variation of a Flyback converter and consists of a half bridge power stage SHS and SLS, transformer, primary side capacitor, diode and output capacitor. The output voltage is regulated indirectly by using the primary side capacitor voltage, VPRI, as feedback. The Flybuck is a portmanteau of flyback and buck since the transformer is connected as a flyback converter and the input to output voltage relationship is similar to a buck derived converter, assuming the converter is operating in steady state and the transformer has negligible leakage inductance. The CPRI and LPRI are charged by the input voltage source VIN during the time the high side switch SHS is on. During this time, diode D1 is reversed biased and the load current is supplied by output capacitor CO. During the off time of SHS, SLS conducts and the voltage on CPRI continues to increase during a portion of the SLS conduction time. The voltage increase is due to the energy transfer from LPRI to CPRI. For the remaining portion of the SLS conduction time, the CPRI voltage decreases because of current in LPRI reverses; see the ILPRI and VPRI waveforms in Figure 8. By neglecting the diode voltage drop, conduction dead time and leakage inductance, the input to output voltage conversion ratio can be derived as shown in Equation 2 from the flux balance in LPRI. It can be seen in Equation 2 that the input to output relationship is the same as a buck-derived converter with transformer isolation. The dc voltage VPRI on the primary side capacitor in Equation 3 has the same linear relationship to the input voltage as a buck converter. SHS D1 T1 D1 T1 CIN SLS NPRI NSEC CO _ + SHS VIN C IN NPRI NSEC CO + VPRI _ VO SHS + VPRI _ CPRI D x Ts _ SLS + VO D1 T1 CPRI CIN SLS NPRI NSEC _ + VO _ + VPRI CO CPRI (1 - D) x Ts Figure 7. Simplified Schematic with Two Primary Operational States 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com The small signal model for the Flybuck is derived by changing the transformer to the inductor equivalent and reflecting the output filter to the primary side for the circuit shown in Figure 7. Assuming negligible leakage inductance and equivalent series resistance for the capacitors, the VPRI transfer function is similar to the current mode control buck power stage transfer function with the exception that the CO and load are in parallel with the CPRI only for the 1-D time. Averaging the secondary side components, an approximate transfer function is shown in Equation 4 and pole location in Equation 5. RO is the secondary side load resistance and the RLM is the dc resistance of the primary. Ri is the inverse of the Comp to PH gm. VO VIN = NSEC NPRI ×D (2) spacer VPRI VIN =D (3) æ æN ö÷ ç RO RLM + ççç × ççç PRI ÷÷ ççè (1- D) èç NSEC ø÷÷ Vˆ PRI » æ Vˆ C s ÷÷ö ç ç Ri × ç1 + ÷ 2 × p x fPOLE ÷÷ø èç 2 fPOLE = ÷ö÷ ÷÷ ÷÷ø (4) 1 2 2 æ æN ö ÷ö æç æN ö ÷ö ç RO ÷ ÷ ÷ ç ÷ ç SEC ç PRI ç 2 × p ×çç × çç ÷÷ ÷÷ × ç(1 - D) × CO × çç ÷÷ + CPRI ÷÷÷ çè NPRI ÷÷ø çèç(1 - D) çè NSEC ÷÷ø ÷÷ø ççè ÷ø (5) SHS SLS ILpri_pospk ILpri Im_valley ILpri_negpk Vpri ID1_pk ID1 DTs (1-D) x Ts Figure 8. Simplified Voltage and Current Waveforms Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 13 UCC25230 SLUSAQ6A – NOVEMBER 2011 www.ti.com Typical Application Diagram D1 T1 37 VDC to 75 VDC VIN J4 Isoloated 9 VDC Output C8 UCC25230 C2 1 2 PH VIN BOOT VDD J2 8 7 C6 UV/OV COMP 6 C1 C7 C3 4 VIN_G FB GND_PAD 9 VDC Output R3 C4 3 C9 R2 R1 D2 5 C5 R4 4 Figure 9. Typical Application Diagram 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCC25230 PACKAGE OPTION ADDENDUM www.ti.com 18-Nov-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp UCC25230DRMR ACTIVE VSON DRM 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC25230DRMT ACTIVE VSON DRM 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC25230DRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC25230DRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Dec-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC25230DRMR VSON DRM 8 3000 346.0 346.0 29.0 UCC25230DRMT VSON DRM 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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