LMK00725
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SNAS625A – SEPTEMBER 2013 – REVISED OCTOBER 2013
Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer
Check for Samples: LMK00725
FEATURES
APPLICATIONS
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Five 3.3V Differential LVPECL Outputs
– Additive Jitter: 43 fs RMS (typ) @ 312.5
MHz
– Noise Floor (≥1 MHz offset): -158 dBc/Hz
(typ) @ 312.5 MHz
– Output Frequency: 650 MHz (max)
– Output Skew: 35 ps (max)
– Part-to-Part Skew: 100 ps (max)
– Propagation Delay: 0.37 ns (max)
Two Differential Input Pairs (pin-selectable)
– CLKx, nCLK Input Pairs can accept
LVPECL, LVDS, HCSL, SSTL, LVHSTL, or
Single-Ended Signals
Synchronous Clock Enable
Power Supply: 3.3V ± 5%
Package: 20-Lead TSSOP
Industrial Temperature Range: -40ºC to +85ºC
Wireless and Wired Infrastructure
Networking and Data Communications
Servers and Computing
Medical Imaging
Portable Test and Measurement
High-End A/V
DESCRIPTION
The LMK00725 is a low skew, high-performance
clock fanout buffer which can distribute up to five
3.3V LVPECL outputs from one of two inputs, which
can accept differential or single-ended inputs. The
clock enable input is synchronized internally to
eliminate runt or glitch pulses on the outputs when
the clock enable pin is asserted or de-asserted. The
low additive jitter and phase noise floor and ensured
output and part-to-part skew characteristics make the
LMK00725 ideal for applications demanding high
performance and repeatability.
FUNCTIONAL BLOCK DIAGRAM
CLK_EN
RPU
D
Q
RPD
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
RPU
0
RPD
RPU
1
Q0
nQ0
Q1
nQ1
RPD
Q2
RPU = Pullup
RPD = Pulldown
nQ2
Q3
nQ3
Q4
nQ4
(1)
RPU = 51 kΩ pullup, RPD = 51 kΩ pulldown
Figure 1.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
LMK00725
SNAS625A – SEPTEMBER 2013 – REVISED OCTOBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PINOUT DIAGRAM
Q0
1
20
VCC
nQ0
2
19
CLK_EN
Q1
3
18
VCC
nQ1
4
17
nCLK1
Q2
5
16
CLK1
nQ2
6
15
VEE
Q3
7
14
nCLK0
nQ3
8
13
CLK0
Q4
9
12
CLK_SEL
nQ4
10
11
VCC
Figure 2.
Table 1. PIN DESCRIPTIONS (1) (2)
(1)
(2)
2
NO.
NAME
TYPE (1)
1, 2
Q0, nQ0
O
LVPECL output pair 0
3, 4
Q1, nQ1
O
LVPECL output pair 1
5, 6
Q2, nQ2
O
LVPECL output pair 2
7, 8
Q3, nQ3
O
LVPECL output pair 3
9, 10
Q4, nQ4
O
LVPECL output pair 4
11, 18, 20
VCC
PWR
Power supply pins
12
CLK_SEL
I, RPD
Clock select input. LVCMOS / TTL compatible.
0 = Select CLK0, nCLK0
1 = Select CLK1, nCLK1
13
CLK0
I, RPD
Non-inverting differential clock input 0.
14
nCLK0
I, RPU
Inverting differential clock input 0.
15
VEE
PWR
Negative supply pin
16
CLK1
I, RPD
Non-inverting differential clock input 1.
17
nCLK1
I, RPU
Inverting differential clock input 1.
19
CLK_EN
I, RPU
Synchronous clock enable input. LVCMOS / TTL compatible.
0 = Qx outputs are forced low, nQx outputs are forced high.
1 = Clock outputs are enabled and follow clock input.
DESCRIPTION
G = Ground, I = Input, O = Output, P = Power, RPU = 51 kΩ pullup, RPD = 51 kΩ pulldown
Please refer to Recommendations for Unused Input and Output Pins, if applicable.
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ABSOLUTE MAXIMUM RATINGS (1) (2)
Over operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
V
VCC
Supply Voltage
-0.3
3.6
VIN
Input Voltage Range
-0.3
VCC + 0.3
V
TSTG
Storage Temperature Range
-65
150
°C
TJ
Junction Temperature
150
°C
ESD
Electrostatic
Discharge
(1)
(2)
Human Body Model (HBM)
2000
Machine Model (MM)
150
Charged Device Model (CDM)
750
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
THERMAL CHARACTERISTICS
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
Package Thermal Impedance, Junction to Air (0 LFPM)
θJA
UNIT
107.2
°C/W
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
VCC
Supply Voltage
IOUT
Output Current
TA
Ambient Temperature
TJ
Junction Temperature
TEST CONDITIONS
MIN
TYP
MAX
VEE = GND
3.135
3.3
3.465
UNIT
30
mA
85
°C
125
°C
TYP
MAX
UNIT
52
60
mA
-40
POWER SUPPLY CHARACTERISTICS
Over operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
Power Supply Current
through VEE
IEE
LVCMOS / TTL DC CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
VIH
Input High Voltage
VIL
Input Low Voltage
TEST CONDITIONS
MIN
MAX
UNIT
2
TYP
VCC + 0.3
V
VEE – 0.3
0.4
V
CLK_EN
5
µA
CLK_SEL
150
VCC = VIN = 3.465 V
IIH
Input High Current
VCC = 3.465V, VIN = 0 V
IIL
Input Low Current
CLK_EN
-150
CLK_SEL
-5
µA
CIN
Input Capacitance
1
RIN
Input Pullup or Pulldown
Resistance
51
pF
kΩ
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DIFFERENTIAL INPUT DC CHARACTERISTICS
Over operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VID
Differential Input Voltage
Swing (VIH-VIL) (1) (2)
0.15
1.3
V
VICM
Input Common Mode
Voltage (1) (2) (3)
0.5
VCC – 0.85
V
IIH
Input High Current (4)
nCLKx
5
µA
CLKx
150
VCC = VIN = 3.465 V
VCC = 3.465V, VIN = 0 V
Input Low Current (4)
IIL
(1)
(2)
(3)
(4)
nCLKx
-150
CLKx
-5
µA
VIL should not be less than -0.3V
See Figure 22
Input common mode voltage is defined as VIH
For IIH and IIL measurements on CLKx (or nCLKx), care must be taken to comply with VID and VICM specifications using the appropriate
bias on nCLKx (or CLKx)
LVPECL OUTPUT CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted), outputs terminated with 50Ω to VCC – 2V.
All AC parameters measured at 500 MHz unless otherwise noted.
MAX
UNIT
VOH
SYMBOL
Output High Voltage
PARAMETER
DC measurement
VCC – 1.4
VCC – 0.9
V
VOL
Output Low Voltage
DC measurement
VCC – 2.0
VCC – 1.6
V
VOD
Output Voltage Swing
(VOH-VOL)
DC measurement
0.575
0.85
V
f ≤ 650 MHz
0.17
Output Frequency
tPD
Propagation Delay
(1) (2)
Output Skew
tSK(PP)
Part-to-Part Skew (1) (4) (5)
tR / tF
Output Rise/Fall Time (1)
(4)
(5)
(6)
4
TYP
0.25
(1) (3) (4)
tSK(O)
(1)
(2)
(3)
MIN
(1)
fOUT
JADD
TEST CONDITIONS
Additive Jitter
(6)
20% to 80%, f=50 MHz
100
f = 156.25 MHz, Input slew
rate ≥ 3 V/ns, 10 KHz
to 20 MHz integration band
75
f = 312.5 MHz, Input slew
rate ≥ 3 V/ns, 10 kHz
to 20 MHz integration band
43
650
MHz
0.37
ns
35
ps
100
ps
200
ps
fs RMS
Parameter is specified by characterization. Not tested in production.
Measured from the differential input crossing point to the differential output crossing point.
Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at the output differential
crossing points.
Parameter is defined in accordance with JEDEC Standard 65.
Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, operating at the same
supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device.
Measured at the output differential crossing points.
Buffer Additive Jitter: JADD = SQRT(JSYSTEM - JSOURCE), where JSYSTEM is the RMS jitter of the system output (source+buffer) and
JSOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should
be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (NF). This is usually the case for highquality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and
measurement details.
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LVPECL OUTPUT CHARACTERISTICS (continued)
Over recommended operating free-air temperature range (unless otherwise noted), outputs terminated with 50Ω to VCC – 2V.
All AC parameters measured at 500 MHz unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f = 156.25 MHz, Input slew
rate ≥ 3 V/ns, 10 kHz
to 20 MHz integration band
PNFLOOR
Phase Noise Floor (7)
10 kHz offset
-145
100 kHz offset
-153
1 MHz offset
-158
10 MHz offset
-159
20 MHz offset
-159
f = 312.5 MHz, Input slew
rate ≥ 3 V/ns, 10 kHz
to 20 MHz integration band
10 kHz offset
-149
100 kHz offset
-154
1 MHz offset
-156
10 MHz offset
-158
20 MHz offset
ODC
Output Duty Cycle (8)
50% Input Duty Cycle
PSRR
Power Supply
Ripple Rejection (9)
f = 100 MHz, VCC ripple =
100 mVp-p @ 1 MHz
(7)
(8)
(9)
dBc/Hz
dBc/Hz
-158
48
50
-80
52
%
dBc
Buffer Phase Noise Floor: PNFLOOR (dBc/Hz) = 10*log10[10^(PNTOTAL/10) – 10^(PNSOURCE/10)], where PNTOTAL is the phase noise floor
of the system output (source+buffer) and PNSOURCE is the phase noise floor of the input source. Buffer Phase Noise Floor should be
considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for
high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and
measurement details.
Parameter is specified by characterization. Not tested in production.
Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output
when a single-tone sinusoidal signal (ripple) is injected onto the VCC supply. Assuming no amplitude modulation effects and small index
modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as
follows: DJ (ps p-p) = [ (2 x 10(PSRR / 20)) / (π x fCLK) ] x 1E12.
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TYPICAL CHARACTERISTICS
Unless otherwise noted: TA = 25C, VCC = 3.3 V, Input slew rate ≥ 3 V/ns, 10 kHz to 20 MHz integration band
1.2
0.35
0.30
Additive Jitter (ps RMS)
Output Swing, VOD (V)
1.0
0.8
0.6
0.4
0.2
0.25
0.20
0.15
0.10
0.05
0.0
0.00
0
200
400
600
800
1000
Frequency (MHz)
0
1
2
4
5
6
7
C001
Figure 4. Additive Jitter
vs
Input Slew Rate
0.35
±142
Phase Noise @ 10 MHz offset (dBc/Hz)
3.1 V
fCLK = 156.25 MHz,
RBIAS = 180 to GND,
Outputs AC-coupled
0.30
3
Input Slew Rate (V/ns)
C001
Figure 3. Output Swing, VOD (V)
vs
Frequency (MHz)
Additive Jitter (ps RMS)
100 MHz
156.25 MHz
312.5 MHz
622.08 MHz
RBIAS = 180 to GND,
Outputs AC-coupled
3.3 V
3.5 V
0.25
0.20
0.15
0.10
0.05
0.00
100 MHz
156.25 MHz
312.5 MHz
622.08 MHz
RBIAS = 180 to GND,
Outputs AC-coupled
±145
±148
±151
±154
±157
±160
±163
0
1
2
3
4
5
6
7
Input Slew Rate (V/ns)
0
Phase Noise @ 10 MHz offset (dBc/Hz)
3
4
5
6
7
C003
Figure 6. Phase Noise Floor @ 10 MHz offset
vs
Input Slew Rate
3.1 V
fCLK = 156.25 MHz,
RBIAS = 180 W to GND,
Outputs AC-coupled
±145
2
Input Slew Rate (V/ns)
Figure 5. Additive Jitter
vs
Input Slew Rate, fCLK = 156.25 MHz
±142
1
C002
3.3 V
3.5 V
±148
±151
±154
±157
±160
±163
0
1
2
3
4
5
6
7
Input Slew Rate (V/ns)
C004
Figure 7. Phase Noise Floor @ 10 MHz offset
vs
Input Slew Rate, fCLK = 156.25 MHz
6
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FUNCTIONAL DESCRIPTIONS
CONTROL INPUT FUNCTION
Over operating free-air temperature range (unless otherwise noted)
Table 2.
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
Qx
nQx
0
0
CLK0, nCLK0
Disabled; LOW
Disabled; HIGH
0
1
CLK1, nCLK1
Disabled; LOW
Disabled; HIGH
1
0
CLK0, nCLK0
Enabled
Enabled
1
1
CLK1, nCLK1
Enabled
Enabled
CLOCK ENABLE TIMING
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 8. In the active mode, the output states are a function of the CLKx, nCLKx inputs as
described in CLOCK INPUT FUNCTION.
nCLK[0:1]
CLK[0:1]
CLK_EN
Disabled
Enabled
nQ[0:4]
Q[0:4]
Figure 8. Clock Enable Timing Diagram
CLOCK INPUT FUNCTION
Over operating free-air temperature range (unless otherwise noted)
Table 3.
Inputs
(1)
Outputs
Input to Output
Mode
Polarity
CLK0 or CLK1
nCLK0 or nCLK1
Qx
nQx
0
1
LOW
HIGH
Differential to
Differential
Non-inverting
1
0
HIGH
LOW
Differential to
Differential
Non-inverting
0
Biased (1)
LOW
HIGH
Single-Ended to
Differential
Non-inverting
1
Biased (1)
HIGH
LOW
Single-Ended to
Differential
Non-inverting
Biased (1)
0
HIGH
LOW
Single-Ended to
Differential
Inverting
Biased (1)
1
LOW
HIGH
Single-Ended to
Differential
Inverting
Refer to Input DC Configuration During Device Test
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TEST LOAD CONFIGURATION
2V
Q
ZO = 50
nQ
ZO = 50
DUT
output
R=50from
measurement
equipment (2 places)
-1.3V ± 0.165V
Figure 9. Output DC Configuration; Test Load Circuit
8
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INPUT CLOCK INTERFACE CIRCUITS
3.3V
3.3V
3.3V
R = 100
R = 1N
Rs
CLK
Zo = 50
Zo
DUT
nCLK
R = 100
R = 1N
C = 0.1µF
Clock generator:
Zo + Rs = 50
Figure 10. Single-Ended/LVCMOS Input DC Configuration During Device Test
3.3V
3.3V
3.3V
R = 125
R = 125
Zo = 50
CLK
LVPECL
output
nCLK
DUT
Zo = 50
R = 84
R = 84
Figure 11. LVPECL Input Configuration During Device Test
3.3V
3.3V
Zo = 50
CLK
LVPECL
output
DUT
nCLK
Zo = 50
R = 50
R = 50
R = 50
Figure 12. LVPECL Input Configuration During Device Test
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3.3V
3.3V
R = 33
Zo = 50
CLK
HCSL
output
nCLK
DUT
Zo = 50
R = 33
R = 50
R = 50
Figure 13. HCSL Input Configuration During Device Test
3.3V
3.3V
Zo = 50
CLK
LVDS
output
R = 100
DUT
nCLK
Zo = 50
Figure 14. LVDS Input Configuration During Device Test
3.3V
2.5V
3.3V
R = 120
R = 120
Zo = 60
CLK
SSTL
output
DUT
nCLK
Zo = 60
R = 120
R = 120
Figure 15. SSTL Input Configuration During Device Test
10
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OUTPUT CLOCK INTERFACE CIRCUITS
3.3V
3.3V
3.3V
R = 125
R = 125
ZO = 50
LMK00725
ZO = 50
R = 84
R = 84
Figure 16. LVPECL Output DC Configuration: Typical Application Load
3.3V
3.3V
ZO = 50
LMK00725
ZO = 50
R = 50
R = 50
R = 50
Figure 17. LVPECL Output DC Configuration: Typical Application Load
3.3V
3.3V
ZO = 50
LMK00725
RT = 100
ZO = 50
R = 180
(1)
R-bias can range from 120 Ω to 240 Ω, but 180 Ω is equivalent to loading outputs with 50 Ω to VCC - 2 V.
Figure 18. LVPECL Output AC Configuration: Typical Application Load
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APPLICATION INFORMATION
Application Block Diagram Examples
3.3 V
0.1 PF
(x3)
10 PF
LVPECL Outputs AC-coupled to Inputs of PHYs (x4)
10k
VCC (x3)
0.1 PF
10GE PHY
CLK_EN
Q[3:0]
Z0 = 50:
CLK_SEL
nQ[3:0]
Z0 = 50:
100:
LO = CLK0
HI = CLK1
CLK0
156.25 MHz
LVDS Clock
Gen or Osc
100:
312.5 MHz
LVPECL Clock
Gen or Osc
100:
Internal Input
Termination &
Biasing
180:
LMK00725
nCLK0
CLK1
Q4
nCLK1
nQ4
Unused Output Pair
(Leave Pins Open)
VEE
180:
Figure 19. 10-Gigabit Ethernet PHY Clock Fanout with LVPECL Output AC Configuration
3.3 V
LVPECL to HCSL Interface (4x)
3.3 V
0.1 PF
(x3)
10 PF
VCM = 0.45V
RT = 50:
10k
LO = CLK0
HI = CLK1
100 MHz LVDS
Clock Gen or
Osc
100 MHz,
2.5-V LVCMOS
Oscillator
VCC (x3)
CLK_EN
Q[3:0]
Z0 = 50:
CLK_SEL
nQ[3:0]
Z0 = 50:
Rs
Z0 = 50:
1k
57.6:
180:
CLK0
100:
365:
0.1 PF
LMK00725
nCLK0
CLK1
Q4
nCLK1
2.5 V
HCSL
Receiver
No Internal
Termination
or Biasing
Unused Output Pair
(Leave Pins Open)
nQ4
VEE
1k
0.1 PF
Figure 20. Interfacing LVPECL Outputs to HCSL Receiver Inputs
12
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Input Detail
Vcc (3.3V)
51k
nCLK0
51k
CLK0
Vcc (3.3V)
51k
nCLK1
51k
CLK1
LMK00725
Figure 21. Clock Input Components
Parameter Measurement Information
VCC
VIH = VICM
nCLK
VID = |VIH ± VIL|
CLK
VIL
VCM
GND
NOTE: VCM = VICM – VID/2 = (VIH + VIL)/2
Figure 22. Differential Input Level
VOH
nQ
80%
VOD = |VOH ± VOL|
20%
Q
VOL
tR
tF
Figure 23. Output Voltage, and Rise and Fall Times
LVCMOS
Input
CLK
nCLK
CLK
Differential
Input
tPD
nQx
LVPECL
Outputx
Qx
tSK
nQy
LVPECL
Outputy
Qy
Figure 24. Differential and Single-Ended Output Skew and Propagation Delay
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Recommendations for Unused Input and Output Pins
•
•
•
CLK_SEL and CLK_EN: These inputs have internal pull-up (RPU) or pull-down (RPD) according to Figure 1
and can be left floating if unused. The floating state for CLK_SEL is channel 0 selected, and the default for
CLK-EN is normal output.
CLK/nCLK inputs: See Figure 21 for the internal connections. When using single ended input, take note of
the internal pull-up and pull-down to make sure the unused input is properly biased. For single ended input,
the Figure 10 arrangement is recommended.
Outputs: Unused outputs can be left floating or terminated. If left floating, it is recommended to not attach
any traces to the output pins.
Input Slew Rate Considerations
LMK00725 employs high-speed and low-latency circuit topology, allowing the device to achieve ultra-low additive
jitter/phase noise and high-frequency operation. To take advantage of these benefits in the system application, it
is optimal for the input signal to have a high slew rate of 3 V/ns or greater. Driving the input with a slower slew
rate can degrade the additive jitter and noise floor performance. For this reason, a differential signal input is
recommended over single-ended because it typically provides higher slew rate and common-mode-rejection.
Refer to the “Additive RMS Jitter vs. Input Slew Rate” plots in the TYPICAL CHARACTERISTICS section. Also,
using an input signal with very slow input slew rate, such as less than 0.05 V/ns, has the tendency to cause
output switching noise to feed-back to the input stage and cause the output to chatter. This is especially true
when driving either input in single-ended fashion with a very slow slew rate, such as a sine-wave input signal.
System-Level Phase Noise and Additive Jitter Measurement
For high-performance devices, limitations of the equipment influence phase-noise measurements. The noise floor
of the equipment is often higher than the noise floor of the device. The real noise floor of the device is probably
lower. It is important to understand that system-level phase noise measured at the DUT output is influenced by
the input source and the measurement equipment.
For Figure 25 and Figure 26 system-level phase noise plots, a Rohde & Schwarz SMA100A low-noise signal
generator was cascaded with an Agilent 70429A K95 single-ended to differential converter block with ultra-low
phase noise and fast edge slew rate (>3 V/ns) to provide a very low-noise clock input source to the LMK00725.
An Agilent E5052 source signal analyzer with ultra-low measurement noise floor was used to measure the phase
noise of the input source (SMA100A + 70429A K95) and system output (input source + LMK00725). The input
source phase noise is shown by the light yellow trace, and the system output phase noise is shown by the dark
yellow trace.
The additive phase noise or noise floor of the buffer (PNFLOOR) can be computed as follows:
PNFLOOR (dBc/Hz) = 10*log10[10^(PNSYSTEM/10) – 10^(PNSOURCE/10)]
where
•
•
PNSYSTEM is the phase noise of the system output (source+buffer)
PNSOURCE is the phase noise of the input source
(1)
space
The additive jitter of the buffer (JADD) can be computed as follows:
JADD = SQRT(JSYSTEM2– JSOURCE2),
where
•
•
14
JSYSTEM is the RMS jitter of the system output (source+buffer), integrated from 10 kHz to 20 MHz
JSOURCE is the RMS jitter of the input source, integrated from 10 kHz to 20 MHz
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(2)
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LMK00725
LMK00725
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SNAS625A – SEPTEMBER 2013 – REVISED OCTOBER 2013
Figure 25. 156.25 MHz Input Phase Noise (66 fs rms, Light Yellow) and Output Phase Noise (92.1 fs rms,
Dark Yellow). Additive Jitter = 65 fs rms (10 kHz to 20 MHz) @ 4 V/ns Input Slew Rate
Figure 26. 312.5 MHz Input Phase Noise (43 fs rms, Light Yellow) and Output Phase Noise (55.7 fs rms,
Dark Yellow). Additive Jitter = 36 fs rms (10 kHz to 20 MHz) @ 6 V/ns Input Slew Rate
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15
LMK00725
SNAS625A – SEPTEMBER 2013 – REVISED OCTOBER 2013
www.ti.com
Power Considerations
The power dissipation of the LMK00725 consists of the quiescent power and load related power. Here is the
expression for the total power which uses the values derived for "Quiescent Power" and "Load Power" further
below:
PTotal = PQ (worst case) + PL = 208 mW + 30.2 mW x (# of terminated outputs)
(3)
For all 5 outputs terminated:
PTotal = 208 mW + 27 mW x 5 = 343 mW
(4)
Quiescent Power:
PQ = VCC x IEE= 3.3V x 60 mA = 198 mW
(5)
Considering a 5% tolerance on Vcc:
PQ (worst case) = 198 mW x 1.05 = 208 mW
(6)
Load Power:
Assuming 50% output duty cycle and 50 Ω load from each output (Q and nQ) to Vcc - 2 V (or 1.3 V) and output
voltage levels of 1.1 V and 1.8 V below Vcc for VOH and VOL respectively:
PL / output_pair = P_high + P_low = {1.1 V x [Vcc - 1.1 V - (Vcc - 2 V)] / 50Ω)} + {1.8 V x [Vcc - 1.8 V - (Vcc - 2 V)] /
50Ω)} = 20 mW + 7 mW = 27 mW
(7)
NOTE
For dimensioning the power supply, consider the total power consumption. The total
power consumption is the sum of device power consumption and the power consumption
of the load.
Thermal Management
Power consumption of the LMK00725 can be high enough to require attention to thermal management. For
reliability and performance reasons, limit the die temperature to a maximum of 125°C. That is, as an estimate, TA
(ambient temperature) plus device power consumption times θJA should not exceed 125°C.
Assuming the conditions in the Power Considerations section and operating at an ambient temperature of 70°C
with all outputs loaded, here is an estimate of the LMK00725 junction temperature:
TJ = TA + PTotal x θJA = 70°C + 343 mW x 107.2°C/W = 70°C + 37°C = 107°C
(8)
Here are some recommendations for improving heat flow away from the die:
• Use multi-layer boards
• Specify a higher copper thickness for the board
• Increase the number of vias from the top level ground plane under and around the device to internal layers
and to the bottom layer with as much copper area flow on each level as possible
• Apply air flow
• Leave unused outputs floating
16
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LMK00725
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SNAS625A – SEPTEMBER 2013 – REVISED OCTOBER 2013
Power-Supply Filtering
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is critical to applications.
Use of filter capacitors eliminates the low-frequency noise from power supply, where the bypass capacitors
provide the very low-impedance path for high-frequency noise and guard the power-supply system against
induced fluctuations. The bypass capacitors also provide instantaneous current surges as required by the device,
and should have low ESR. To use the bypass capacitors properly, place them very close to the power supply
pins and lay out traces with short loops to minimize inductance. TI recommends adding as many high-frequency
bypass capacitors (such as 0.1-µF, for example) as there are supply pins in the package. It is recommended, but
not required, to insert a ferrite bead between the board power supply and the chip power supply to isolate the
high-frequency switching noises generated by the clock driver, thereby preventing them from leaking into the
board supply. Choosing an appropriate ferrite bead with very low DC resistance is important, because it is
imperative to provide adequate isolation between the board supply and the chip supply. It is also imperative to
maintain a voltage at the supply pins that is greater than the minimum voltage required for proper operation.
Board
Supply
Vcc
Chip
Supply
Ferrite Bead
C
1 µF
C
10 µF
0.1 µF (3
places, one
per Vcc pin)
Figure 27. Power-Supply Decoupling
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This Revision History highlights the technical changes made to the SNAS625 document to make it a SNAS625A
Revision.
Table 4. LMK00725 Revisions
SEE
FEATURES
ADDITIONS/MODIFICATIONS/DELETIONS
Deleted Item from Features Section.
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Product Folder Links: LMK00725
17
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMK00725PW
ACTIVE
TSSOP
PW
20
73
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMK00725
LMK00725PWR
ACTIVE
TSSOP
PW
20
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMK00725
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMK00725PWR
Package Package Pins
Type Drawing
TSSOP
PW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMK00725PWR
TSSOP
PW
20
2500
367.0
367.0
35.0
Pack Materials-Page 2
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