SN100KT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS13A – APRIL 1990 – REVISED OCTOBER 1990 • • • • • • • DW OR NT PACKAGE 100K Compatible (T0P VIEW) TTL Clock and ECL Control Inputs 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q Noninverting Outputs Flow-Through Architecture Optimizes PCB Layout Center Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise Package Options Include “Small Outline” Packages and Standard Plastic DIPs ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 1D 2D 3D 4D OE(ECL) VCC VEE CLK(TTL) 5D 6D 7D 8D description Function Table This octal TTL-to-ECL translator is designed to provide efficient translation between a TTL signal environment and a 100K ECL signal environment. This device is designed specifically to improve the performance and density of TTL-to-ECL CPU/ bus-oriented functions such as memoryaddress drivers,clock drivers, and bus-oriented receivers and transmitters. The eight flip-flops of the ’5578 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs. The output-control input OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off. OE CLK D Q L ↑ L L L ↑ H H L L X Q0 H X X L logic symbol† CLK OE 1D 2D The SN100KT5578 is characterized for operation from 0°C to 85°C. OUTPUT (ECL) INPUTS 3D 4D 5D 6D 7D 8D 17 20 24 TTL/ECL C1 EN 1D TTL/ECL 1 23 2 22 3 21 4 16 9 15 10 14 11 13 12 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Copyright 1990, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN100KT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS13A – APRIL 1990 – REVISED OCTOBER 1990 logic diagram (positive logic) OE CLK 20 17 TTL/ECL C1 1D 24 TTL/ECL 1D TTL/ECL 1D TTL/ECL C1 1D C1 2D 3D 4D 5D 6D 7D 8D 2 23 22 21 C1 TTL/ECL 15 14 13 TTL/ECL TTL/ECL TTL/ECL 2 1Q 2Q 3 3Q 4 4Q 1D 16 TTL/ECL 1 C1 9 C1 10 C1 11 C1 12 5Q 1D 6Q 1D 7Q 1D 1D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8Q SN100KT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS13A – APRIL 1990 – REVISED OCTOBER 1990 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Supply voltage range, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 8 V to 0 V Input voltage range (TTL) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V Input voltage range (ECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0 V Input current range (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA Current out of any output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Operating ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed. recommended operating conditions MIN NOM MAX VCC VEE TTL supply voltage 4.5 5 5.5 V ECL supply voltage – 4.2 – 4.5 – 4.8 V VIH VIL TTL high-level input voltage IIK VIH TTL input clamp current VIL TA 2 V TTL low-level input voltage ECL high-level input voltage‡ ECL low-level input voltage‡ Operating ambient temperature (see Note 2) UNIT 0.8 V – 18 mA – 1165 – 880 mV – 1810 – 1475 mV 0 85 °C electrical characteristics over recommended operating ambient temperature range (unless otherwise noted) (see Note 2) PARAMETER VIK II D inputs and CLK IIH IIL D inputs and CLK IIH IIL OE only TEST CONDITIONS MIN VCC = 4.5 V, VCC = 5.5 V, VEE = – 4.2 V, VEE = – 4.8 V, II = – 18 mA VI = 7 V VCC = 5.5 V, VCC = 5.5 V, VEE = – 4.8 V, VEE = – 4.8 V, VI = 2.7 V VI = 0.5 V VCC = 5.5 V, VCC = 5.5 V, VEE = – 4.8 V, VEE = – 4.8 V, VIH = – 880 mV VIL = – 1810 mV VOH‡ VOL‡ VCC = 4.5 V, VCC = 4.5 V, VEE = – 4.5 V ± 0.3 V, VEE = – 4.5 V ± 0.3 V, See Note 3 – 1020 See Note 3 – 1810 ICCH ICCL VCC = 5.5 V, VCC = 5.5 V, VEE = – 4.8 V VEE = – 4.8 V D inputs and CLK D inputs and CLK OE only TYP§ MAX – 1.2 0.1 UNIT V mA 20 µA – 0.5 mA 350 µA – 880 mV µA 0.50 – 1620 mV 17 24 mA 14.5 21 mA IEE VCC = 5.5 V, VEE = – 4.8 V – 104 – 149 mA Ci VCC = 5 V, VEE = – 4.5 V, f = 10 MHz 4 pF ‡ The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only. § All typical values are at VCC = 5 V, VEE = – 4.5 V, TA = 25°C. NOTES: 2. Each 100KT series circuit has been designed to meet the dc specifications shown in the test table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear ft/min is maintained. 3. Outputs are terminated through a 50-Ω resistor to – 2 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN100KT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS13A – APRIL 1990 – REVISED OCTOBER 1990 timing requirements VCC = 4.5 V to 5.5 V, VEE = – 4.2 V to – 4.8 V, TA = MIN to MAX† fclock Clock frequency tw Pulse duration, CLK tsu Setup time, data before CLK↑ th Hold time, data after CLK↑ MIN MAX 0 180 High 1.5 Low 2.5 High 4 Low 4 High 1 Low 1 UNIT MHz ns ns ns switching characteristics over recommended ranges of supply voltage and operating ambient temperature (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM TO (IINPUT) (OUTPUT) TYP‡ MAX 0.8 2.3 4.1 0.8 2.2 3.8 0.5 1.4 3 0.5 1.7 3.4 MIN 180 CLK Q OE Q tr tf POST OFFICE BOX 655303 MHz ns ns Y 1.5 ns Y 1.5 ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, VEE = – 4.5 V, TA = 25°C. 4 UNIT • DALLAS, TEXAS 75265 SN100KT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS13A – APRIL 1990 – REVISED OCTOBER 1990 PARAMETER MEASUREMENT INFORMATION From Output Under Test 50 Ω –2 V OUTPUT LOAD CIRCUIT 3V Timing Input 3V High-Level Pulse 1.5 V 1.5 V 0 0 Data Input tw th tsu 3V 1.5 V 3V 1.5 V Low-Level Pulse 0 SETUP AND HOLD TIMES Input (see Note A) 1.5 V 1.5 V 0 PULSE DURATION 3V 1.5 V tf 1.5 V tr 0 80% Output Enable 50% VOH (See Note B) tPLH In-Phase Output 1.5 V 20% 20% 50% VOL – 950 mV 80% 50% – 1690 mV tPHL tPLH tPHL Out-of-Phase Output VOH 50% VOH ECL Output Waveform 1 (See Notes C and D) 50% 50% VOL TTL-INPUT PROPAGATION DELAY TIMES VOL ECL-OUTPUT PROPAGATION DELAY TIMES NOTES: A. For TTL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr = 2.5 ns, tf = 2.5 ns. B. For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr = 0.7 ns, tf = 0.7 ns. C. Waveform 1 is for an output with internal conditions such that the output is high except when disabled by OE. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN100KT5578DW OBSOLETE SOIC DW 24 TBD Call TI Call TI SN100KT5578NT OBSOLETE PDIP NT 24 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. 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