SCLS399J − APRIL 1998 − REVISED APRIL 2005
D
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
SN54LV273A . . . J OR W PACKAGE
SN74LV273A . . . DB, DGV, DW, NS,
OR PW PACKAGE
(TOP VIEW)
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
1Q
1D
2D
2Q
3Q
3D
4D
4Q
20
1D
1Q
CLR
VCC
1
2
19 8Q
3
18 8D
17 7D
4
SN54LV273A . . . FK PACKAGE
(TOP VIEW)
2D
2Q
3Q
3D
4D
16 7Q
15 6Q
5
6
14 6D
13 5D
7
8
12 5Q
9
10
11
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
20
2
VCC
1
SN74LV273A . . . RGY PACKAGE
(TOP VIEW)
CLK
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
D
CLR
D
All Ports
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
GND
D
D Support Mixed-Mode Voltage Operation on
8Q
D 2-V to 5.5-V VCC Operation
D Max tpd of 10.5 ns at 5 V
D Typical VOLP (Output Ground Bounce)
description/ordering information
The ’LV273A devices are octal D-type flip-flops designed for 2-V to 5.5-V VCC operation.
ORDERING INFORMATION
QFN − RGY
SN74LV273ARGYR
LV273A
Tube of 25
SN74LV273ADW
LV273A
Reel of 2000
SN74LV273ADWR
LV273A
SOP − NS
Reel of 2000
SN74LV273ANSR
74LV273A
SSOP − DB
Reel of 2000
SN74LV273ADBR
LV273A
Tube of 70
SN74LV273APW
Reel of 2000
SN74LV273APWR
Reel of 250
SN74LV273APWT
TVSOP − DGV
Reel of 2000
SN74LV273ADGVR
LV273A
CDIP − J
Tube of 20
SNJ54LV273AJ
SNJ54LV273AJ
CFP − W
Tube of 85
SNJ54LV273AW
SNJ54LV273AW
LCCC − FK
Tube of 55
SNJ54LV273AFK
SNJ54LV273AFK
TSSOP − PW
−55°C
−55
C to 125
125°C
C
TOP-SIDE
MARKING
Reel of 1000
SOIC − DW
−40°C
−40
C to 85
85°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LV273A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
!"#$% !%&% %'(#&% !"(($% & ' )"*+!&% &$, ("! !%'(# )$!'!&% )$( $ $(# ' $-& %("#$% &%&( .&((&%/,
("!% )(!$%0 $ % %$!$&(+/ %!+"$ $%0 ' &++
)&(&#$$(,
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1
SCLS399J − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
These devices are positive-edge-triggered flip-flops with direct clear (CLR) input. Information at the data (D)
inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the
clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time
of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has
no effect at the output.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
CLK
OUTPUT
Q
D
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
logic diagram (positive logic)
CLK
1D
2D
3D
4D
3
4
7
8
1D
C1
1D
C1
R
2
6D
13
7D
14
8D
17
18
11
1D
CLR
5D
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
C1
R
R
1
2
5
6
1Q
2Q
3Q
POST OFFICE BOX 655303
9
4Q
• DALLAS, TEXAS 75265
12
5Q
15
6Q
16
7Q
19
8Q
SCLS399J − APRIL 1998 − REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance or
power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
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3
SCLS399J − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV273A
VCC
VIH
High-level input voltage
VIL
Low-level input voltage
VI
VO
Input voltage
IOH
IOL
∆t/∆v
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
2
5.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
Output voltage
UNIT
V
V
0.5
0.5
VCC × 0.3
VCC × 0.3
VCC × 0.3
VCC × 0.3
VCC × 0.3
5.5
0
0
0
VCC
−50
VCC = 2 V
VCC = 2.3 V to 2.7 V
V
VCC
−50
µA
0
V
−2
−6
−6
−12
−12
VCC = 2 V
VCC = 2.3 V to 2.7 V
50
50
2
2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
6
6
12
12
200
200
100
100
20
20
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
VCC × 0.3
5.5
−2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Input transition rise or fall rate
MAX
1.5
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Low-level output current
MIN
1.5
VCC = 2 V
VCC = 2.3 V to 2.7 V
High-level output current
SN74LV273A
mA
µA
mA
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV273A
PARAMETER
VOH
VOL
TEST CONDITIONS
IOH = −50 µA
IOH = −2 mA
IOL = 6 mA
IOL = 12 mA
Ioff
Ci
VI or VO = 0 to 5.5 V
VI = VCC or GND
IO = 0
TYP
MIN
VCC−0.1
2
3V
2.48
2.48
4.5 V
3.8
TYP
MAX
UNIT
V
3.8
2 V to 5.5 V
0.1
0.1
2.3 V
0.4
0.4
3V
0.44
0.44
4.5 V
V
0.55
0.55
0 to 5.5 V
±1
±1
µA
5.5 V
20
20
µA
0
5
5
µA
3.3 V
2
%'(#&% !%!$(% )("! % $ '(#&1$ (
$0% )&$ ' $1$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
4
SN74LV273A
MAX
VCC−0.1
2
2.3 V
IOL = 50 µA
IOL = 2 mA
VI = 5.5 V or GND
VI = VCC or GND,
MIN
2 V to 5.5 V
IOH = −6 mA
IOH = −12 mA
II
ICC
VCC
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2
pF
SCLS399J − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
CLR low
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
CLK high or low
Data
CLR inactive
SN54LV273A
MIN
MAX
SN74LV273A
MIN
6.5
7
7
7
8.5
8.5
8.5
10.5
10.5
4
4
4
0.5
1
1
MAX
UNIT
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
SN54LV273A
MIN
MAX
SN74LV273A
MIN
CLR low
5
6
6
CLK high or low
5
6.5
6.5
Data
5.5
6.5
6.5
CLR inactive
2.5
2.5
2.5
1
1
1
MAX
UNIT
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
fmax
tpd
tPHL
Q
Q
CLK
Q
MIN
5
5
5
5
5
4.5
4.5
4.5
2
2
2
1
1
1
free-air
TA = 25°C
TYP
MAX
SN54LV273A
ns
ns
range,
SN74LV273A
MIN
CL = 15 pF
55*
95*
45*
45
CL = 50 pF
45
75
40
40
MAX
MIN
MAX
18.3*
1*
20.5*
1
20.5
19*
1*
21*
1
21
12.9
22.1
1
25
1
25
CL = 50 pF
CLR
Q
13.1
tsk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
22.8
1
25.5
1
25.5
2
UNIT
MHz
10.3*
CL = 15 pF
UNIT
ns
temperature
LOAD
CAPACITANCE
MIN
MAX
10.4*
tpd
tPHL
CLK
CLR
SN74LV273A
5
CLR inactive
TO
(OUTPUT)
MAX
CLR low
switching characteristics over recommended operating
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
MIN
CLK high or low
Data
PARAMETER
SN54LV273A
ns
ns
2
%'(#&% !%!$(% )("! % $ '(#&1$ (
$0% )&$ ' $1$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
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5
SCLS399J − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
tPHL
CLK
CLR
Q
tpd
tPHL
CLK
Q
CLR
Q
TA = 25°C
TYP
MAX
75*
140*
65*
65
CL = 50 pF
50
110
45
45
CL = 15 pF
CL = 50 pF
fmax
tpd
tPHL
tpd
tPHL
CLK
Q
CLR
Q
CLK
Q
MIN
MAX
MIN
1*
16*
1
16
6.9*
13.6*
1*
16*
1
16
9.1
17.1
1
19.5
1
19.5
8.7
17.1
1
19.5
1
19.5
1.5
ns
ns
1.5
free-air
TA = 25°C
TYP
MAX
UNIT
MHz
13.6*
temperature
SN54LV273A
CL = 15 pF
120*
205*
100*
100
CL = 50 pF
80
160
70
70
MIN
MAX
range,
SN74LV273A
MIN
CL = 50 pF
CLR
Q
tsk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
MAX
7.1*
LOAD
CAPACITANCE
CL = 15 pF
range,
SN74LV273A
CL = 15 pF
Q
TO
(OUTPUT)
SN54LV273A
MIN
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
temperature
LOAD
CAPACITANCE
tsk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PARAMETER
free-air
MIN
MAX
UNIT
MHz
4.8*
9*
1*
10.5*
1
10.5
4.7*
8.5*
1*
10*
1
10
6.2
11
1
12.5
1
12.5
6
10.5
1
12
1
12
1
ns
ns
1
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6)
SN74LV273A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
0.4
0.8
V
Quiet output, minimum dynamic VOL
−0.4
−0.8
V
VOH(V)
VIH(D)
Quiet output, minimum dynamic VOH
2.9
High-level dynamic input voltage
V
2.31
V
VIL(D)
Low-level dynamic input voltage
NOTE 6: Characteristics are for surface-mount packages only.
0.99
V
VCC
3.3 V
TYP
UNIT
5V
17.1
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
%'(#&% !%!$(% )("! % $ '(#&1$ (
$0% )&$ ' $1$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
6
POST OFFICE BOX 655303
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f = 10 MHz
15.9
pF
SCLS399J − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
50% VCC
Input
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
0V
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LV273ADBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ADBRE4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ADBRG4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ADGVR
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ADGVRE4
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ADGVRG4
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ADWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ADWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ADWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ADWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ADWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ANSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ANSRG4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273APWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273APWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273APWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273APWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273APWTE4
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273APWTG4
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV273ARGYR
ACTIVE
VQFN
RGY
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN74LV273ARGYRG4
ACTIVE
VQFN
RGY
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2009
Orderable Device
Status (1)
SN74LV273AZQNR
ACTIVE
Package
Type
BGA MI
CROSTA
R JUNI
OR
Package
Drawing
ZQN
Pins Package Eco Plan (2)
Qty
20
1000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
SNAGCU
MSL Peak Temp (3)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.5
2.5
12.0
16.0
Q1
SN74LV273ADBR
SSOP
DB
20
2000
330.0
16.4
SN74LV273ADGVR
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV273ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
SN74LV273ANSR
SO
NS
20
2000
330.0
24.4
8.2
13.0
2.5
12.0
24.0
Q1
SN74LV273APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
VQFN
SN74LV273ARGYR
8.2
B0
(mm)
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
SN74LV273AZQNR
BGA MI
CROSTA
R JUNI
OR
ZQN
20
1000
330.0
12.4
3.3
4.3
1.6
8.0
12.0
Q1
SN74LV273AZQNR
BGA MI
CROSTA
R JUNI
OR
ZQN
20
1000
330.0
12.4
3.3
4.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV273ADBR
SSOP
DB
20
2000
346.0
346.0
33.0
SN74LV273ADGVR
TVSOP
DGV
20
2000
346.0
346.0
29.0
SN74LV273ADWR
SOIC
DW
20
2000
346.0
346.0
41.0
SN74LV273ANSR
SO
NS
20
2000
346.0
346.0
41.0
SN74LV273APWR
TSSOP
PW
20
2000
346.0
346.0
33.0
SN74LV273ARGYR
VQFN
RGY
20
3000
346.0
346.0
29.0
SN74LV273AZQNR
BGA MICROSTAR
JUNIOR
ZQN
20
1000
340.5
338.1
20.6
SN74LV273AZQNR
BGA MICROSTAR
JUNIOR
ZQN
20
1000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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