TI SN74AUP1G99DCUR

SCES594A – JULY 2004 − REVISED OCTOBER 2004
D Available in the Texas Instruments
D
D
D
D
D
D
D
NanoStar and NanoFree Packages
Low Static-Power Consumption;
ICC = 0.9-µA Max
Low Dynamic-Power Consumption;
Cpd = 5 pF Typ at 3.3 V
Low Input Capacitance; Ci = 1.5 pF Typ
Low Noise − Overshoot and Undershoot
<10% of VCC
Input-Disable Feature Allows Floating Input
Conditions
Ioff Supports Partial-Power-Down Mode
Operation
Includes Schmitt-Trigger Inputs
D Wide Operating VCC Range of 0.8 V to 3.6 V
D Optimized for 3.3-V Operation
D 3.6-V I/O Tolerant to Support Mixed-Mode
D
D
D
D
Signal Operation
tpd = 7.4 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
DCT OR DCU PACKAGE
(TOP VIEW)
OE
A
B
GND
1
8
2
7
3
6
4
5
YEP OR YZP PACKAGE
(BOTTOM VIEW)
GND
B
A
OE
VCC
Y
D
C
4
5
3
6
2
7
1
8
C
D
Y
VCC
description /ordering information
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC
range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity
(see Figures 1 and 2).
Static-Power Consumption
(µA)
100%
80%
60%
3.3-V
Logic†
3.3-V
Logic
LVC †
40%
AUP
0%
2.5
Input
2
Output
1.5
1
0.5
20%
20%
0%
Voltage − V
40%
3.5
3
80%
60%
Switching Characteristics
at 25 MHz†
Dynamic-Power Consumption
(pF)
100%
AUP
† Single, dual, and triple gates
Figure 1. AUP − The Lowest-Power Family
0
−0.5
0
5
10
15
20 25 30
Time − ns
35
40
45
† AUP1G08 data at CL = 15 pF
Figure 2. Excellent Signal Integrity
The SN74AUP1G99 features configurable multiple functions with a 3-state output. This device has the
input-disable feature, which allows floating input signals. The inputs and output are disabled when the
output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input.
The user can choose the logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and
buffer. All inputs can be connected to VCC or GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2004, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0 !)) '!!&"&#+
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCES594A – JULY 2004 − REVISED OCTOBER 2004
description/ordering information (continued)
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition
and better switching noise immunity at the input.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Tape and reel
SN74AUP1G99YEPR
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Tape and reel
SN74AUP1G99YZPR
SSOP − DCT
Tape and reel
SN74AUP1G99DCTR
H99_ _ _
VSSOP − DCU
Tape and reel
SN74AUP1G99DCUR
H99_
_ _ _HY_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES594A – JULY 2004 − REVISED OCTOBER 2004
FUNCTION TABLE
INPUTS
D
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
H
L
L
L
L
L
H
H
H
L
L
H
L
L
L
L
L
H
L
H
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
L
L
L
H
L
H
L
L
H
L
L
H
L
H
L
H
L
H
L
H
H
L
L
H
H
L
L
H
L
H
H
L
H
H
L
H
H
H
L
L
L
H
X†
H
X†
H
X†
H
X†
Z
H
C
B
A
OUTPUT
Y
OE
L
† Floating inputs allowed.
logic diagram (positive logic)
OE
A
B
1
2
3
7
C
D
5
Y
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCES594A – JULY 2004 − REVISED OCTOBER 2004
FUNCTION SELECTION TABLE
COMPLEMENTARY FUNCTION
PRIMARY FUNCTION
4
3-state inverter
4
3-state 2-to-1 data selector MUX
5
3-state 2-to-1 data selector MUX, inverted out
5
3-state 2-input AND
3-state 2-input NOR, both inputs inverted
5
3-state 2-input AND, 1 input inverted
3-state 2-input NOR, 1 input inverted
5
3-state 2-input AND, both inputs inverted
3-state 2-input NOR
5
3-state 2-input NAND
3-state 2-input OR, both inputs inverted
6
3-state 2-input NAND, 1 input inverted
3-state 2-input OR, 1 input inverted
6
3-state 2-input NAND, both inputs inverted
3-state 2-input OR
6
3-state 2-input XOR
6
3-state 2-input XNOR
3-state 2-input XOR, 1 input inverted
3-STATE BUFFER FUNCTIONS AVAILABLE
INPUT
FUNCTION
3-state buffer
OE
L
Y
A
B
C
D
Input
X
L
L
X
Input
H
L
L
H
Input
L
H
L
Input
H
H
X
L
Input
X
L
H
Input
L
L
X
Input
X = H or L
3-STATE INVERTER FUNCTIONS AVAILABLE
INPUT
FUNCTION
3-state inverter
OE
L
Y
A
B
C
D
Input
X
L
H
X
Input
H
H
H
L
H
Input
H
L
Input
L
H
X
L
Input
X
H
H
Input
H
H
X
Input
X = H or L
4
PAGE
3-state buffer
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SCES594A – JULY 2004 − REVISED OCTOBER 2004
3-STATE MUX FUNCTIONS AVAILABLE
A/B
A/B
Input 1
Input 1
Y
Input 2
Y
Input 2
A
B
C
D
3-state 2-to-1, data selector MUX
FUNCTION
OE
Input 1
Input 2
Input 1 or Input 2
L
3-state 2-to-1, data selector MUX
Input 2
Input 1
Input 2 or Input 1
L
Input 1
Input 2
Input 1 or Input 2
H
Input 2
Input 1
Input 2 or Input 1
H
3-state 2-to-1, data selector MUX, inverted out
L
3-state 2-to-1, data selector MUX, inverted out
3-STATE AND/NOR FUNCTIONS AVAILABLE
Input 1
Input 1
Y
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state AND
3-state NOR, both inputs inverted
2
3-state AND
3-state NOR, both inputs inverted
Input 1
2
2
L
A
B
C
D
L
Input 1
Input 2
L
L
Input 2
Input 1
L
Y
Input 2
AND/NAND FUNCTION
3-state AND, with A inverted
3-state AND, with A inverted
OR/NOR FUNCTION
OE
3-state NOR, with B inverted
3-state NOR, with B inverted
Input 1
A
B
C
D
Input 2
L
Input 1
L
H
Input 1
Input 2
H
B
C
D
Input 1
L
Input 2
L
H
Input 2
Input 1
H
L
Input 1
Y
Input 2
NO. OF INPUTS
OE
Input 1
Y
Input 2
NO. OF INPUTS
Y
Input 2
Input 2
Y
Input 2
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state AND, with B inverted
3-state NOR, with A inverted
2
3-state AND, with B inverted
3-state NOR, with A inverted
Input 1
OE
L
Input 1
Y
Input 2
A
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state AND, both inverted inputs
3-state NOR
2
3-state AND, both inverted inputs
3-state NOR
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
OE
L
A
B
C
D
Input 1
H
Input 2
L
Input 2
H
Input 1
L
5
SCES594A – JULY 2004 − REVISED OCTOBER 2004
3-STATE NAND/OR FUNCTIONS AVAILABLE
Input 1
Input 1
Y
Input 2
NO. OF INPUTS
2
2
AND/NAND FUNCTION
3-state NAND
OR/NOR FUNCTION
OE
3-state NAND
3-state OR, both inputs inverted
B
C
D
L
Input 1
Input 2
H
L
Input 2
Input 1
H
B
C
D
Input 2
L
Input 1
H
H
Input 1
Input 2
L
B
C
D
Input 1
L
Input 2
H
H
Input 2
Input 1
L
L
Input 1
Y
Input 2
Y
Input 2
AND/NAND FUNCTION
OR/NOR FUNCTION
OE
2
3-state NAND, with A inverted
3-state OR, with B inverted
2
3-state NAND, with A inverted
3-state OR, with B inverted
Input 1
A
L
Input 1
Y
Input 2
NO. OF INPUTS
A
3-state OR, both inputs inverted
Input 1
NO. OF INPUTS
Y
Input 2
Y
Input 2
AND/NAND FUNCTION
OR/NOR FUNCTION
OE
2
3-state NAND, with B inverted
3-state OR, with A inverted
2
3-state NAND, with B inverted
3-state OR, with A inverted
Input 1
A
L
Input 1
Y
Input 2
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state NAND, both inputs inverted
3-state OR
2
3-state NAND, both inputs inverted
3-state OR
OE
L
A
B
C
D
Input 1
H
Input 2
L
Input 2
H
Input 1
L
3-STATE XOR/XNOR FUNCTIONS AVAILABLE
Input 1
Y
Input 2
FUNCTION
3-state XOR
6
OE
L
A
B
C
D
Input 1
X
L
Input 2
Input 2
X
L
Input 1
X
Input 1
H
Input 2
X
Input 2
H
Input 1
L
H
Input 1
Input 2
L
H
Input 2
Input 1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES594A – JULY 2004 − REVISED OCTOBER 2004
3-STATE XOR/XNOR FUNCTIONS AVAILABLE (continued)
Input 1
Y
Input 2
FUNCTION
OE
A
B
C
D
3-state XOR, with A inverted
L
H
L
Input 1
Input 2
Input 1
Y
Input 2
FUNCTION
OE
A
B
C
D
3-state XOR, with B inverted
L
H
L
Input 1
Input 2
Input 1
Y
Input 2
FUNCTION
3-state XNOR
3-state XNOR
OE
L
A
B
C
D
H
L
Input 1
Input 2
H
L
Input 2
Input 1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Output voltage range in the high or low state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W
DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SCES594A – JULY 2004 − REVISED OCTOBER 2004
recommended operating conditions (see Note 3)
VCC
VI
VO
MIN
MAX
0.8
3.6
V
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
−20
µA
Supply voltage
Input voltage
Output voltage
VCC = 0.8 V
VCC = 1.1 V
IOH
IOL
∆t/∆v
High-level output current
Low-level output current
Input transition rise or fall rate
UNIT
−1.1
VCC = 1.4 V
VCC = 1.65
−1.7
VCC = 2.3 V
VCC = 3 V
−3.1
VCC = 0.8 V
VCC = 1.1 V
20
−1.9
mA
−4
µA
1.1
VCC = 1.4 V
VCC = 1.65 V
1.7
VCC = 2.3 V
VCC = 3 V
3.1
VCC = 0.8 V to 3.6 V
200
1.9
mA
4
ns/V
TA
Operating free-air temperature
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES594A – JULY 2004 − REVISED OCTOBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
Positive-going input
threshold voltage
VT−
Negative-going
input threshold
voltage
∆V
VT
Hysteresis
(VT+ − VT−)
VCC
IOH = −1.7 mA
IOH = −1.9 mA
VOH
IOH = −2.3 mA
IOH = −3.1 mA
0.3
0.6
0.3
1.1 V
0.53
0.9
0.53
0.9
1.4 V
0.74
1.11
0.74
1.11
1.65 V
0.91
1.29
0.91
1.29
2.3 V
1.37
1.77
1.37
1.77
3V
1.88
2.29
1.88
2.29
0.1
0.6
0.1
0.6
1.1 V
0.26
0.65
0.26
0.65
1.4 V
0.39
0.75
0.39
0.75
1.65 V
0.47
0.84
0.47
0.84
2.3 V
0.69
1.04
0.69
1.04
1.24
3V
0.88
1.24
0.88
0.8 V
0.07
0.5
0.07
0.5
1.1 V
0.08
0.46
0.08
0.46
1.4 V
0.18
0.56
0.18
0.56
1.65 V
0.27
0.66
0.27
0.66
2.3 V
0.53
0.92
0.53
0.92
0.79
1.31
0.79
1.31
0.8 V to 3.6 V
1.1 V
IOL = 1.7 mA
IOL = 1.9 mA
VOL
IOL = 2.3 mA
IOL = 3.1 mA
1.4 V
1.11
1.03
1.32
1.3
2.05
1.97
1.9
1.85
2.72
2.67
2.3 V
3V
∆Ioff
IOZ
All inputs
2.6
0.8 V to 3.6 V
V
V
V
VCC − 0.1
0.7 × VCC
1.65 V
V
2.55
0.1
0.1
1.1 V
0.3 × VCC
0.3 × VCC
1.4 V
0.31
0.37
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
0.44
0.45
0.1
0.5
µA
0.2
0.6
µA
2.3 V
IOL = 2.7 mA
IOL = 4 mA
II
Ioff
VCC − 0.1
0.75 × VCC
UNIT
0.6
0.8 V
IOH = −2.7 mA
IOH = −4 mA
IOL = 20 µA
IOL = 1.1 mA
TA = −40°C TO 85°C
MIN
MAX
0.8 V
3V
IOH = −20 µA
IOH = −1.1 mA
TA = 25°C
MIN
MAX
3V
V
VI = GND to 3.6 V
VI or VO = 0 V to 3.6 V
0 V to 3.6 V
VI or VO = 0 V to 3.6 V
VO = VCC or GND
0 V to 0.2 V
0.2
0.6
µA
3.6 V
0.1
0.5
µA
0V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SCES594A – JULY 2004 − REVISED OCTOBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
ICC
VI = GND or (VCC to 3.6 V), OE = GND,
IO = 0
0.8 V to 3.6 V
OE input
VI = VCC − 0.6 V,†
IO = 0
3.3 V
All inputs
VI = GND to 3.6 V, OE = VCC‡
Data inputs
∆ICC
Ci
TA = −40°C
TO 85°C
TA = 25°C
VCC
TYP
MAX
MIN
0.5
0.9
40
VI = VCC or GND
Co
VO = VCC or GND
† One input at VCC − 0.6 V, other input at VCC or GND
‡ To show ICC is very low when the input-disable feature is enabled.
50
110
0.8 V to 3.6 V
UNIT
MAX
120
0
0V
1.5
3.6 V
1.5
3.6 V
3
µA
µA
A
nA
pF
pF
switching characteristics over recommended operating free-air temperature range, CL = 5 pF
(unless otherwise noted) (see Figures 3 and 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
tpd
A, B, C, or D
Y
OE
Y
10
OE
Y
POST OFFICE BOX 655303
UNIT
MAX
MIN
MAX
1.2 V ± 0.1 V
0.5
9.9
20.1
0.5
26.6
1.5 V ± 0.1 V
1.4
6.6
11.9
0.5
16.8
1.8 V ± 0.15 V
1.8
5.3
8.9
1
13
2.5 V ± 0.2 V
2.1
3.9
5.8
1.3
8.9
3.3 V ± 0.3 V
1.9
3.3
4.8
1.2
7.4
1.2 V ± 0.1 V
0.6
11.1
21.7
0.5
25.2
1.5 V ± 0.1 V
2.3
7.4
12.6
1.4
16.4
1.8 V ± 0.15 V
2
5.7
9.4
1.1
12.8
2.5 V ± 0.2 V
2.1
4.1
6.2
1.2
8.5
3.3 V ± 0.3 V
1.9
3.4
5
1.1
6.7
8.2
ns
9.8
1.2 V ± 0.1 V
1.4
4.5
7.7
1.5
1.5 V ± 0.1 V
1.7
3.2
4.8
1.7
6
1.8 V ± 0.15 V
1.5
3
4.7
1.3
6.1
2.5 V ± 0.2 V
0.9
1.9
3
0.7
4.2
3.3 V ± 0.3 V
0.8
2.5
4.4
0.7
4.5
• DALLAS, TEXAS 75265
ns
35
0.8 V
tdis
TYP
32
0.8 V
ten
TA = −40°C
TO 85 °C
TA = 25°C
VCC
ns
SCES594A – JULY 2004 − REVISED OCTOBER 2004
switching characteristics over recommended operating free-air temperature range, CL = 10 pF
(unless otherwise noted) (see Figures 3 and 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
tpd
A, B, C, or D
Y
OE
Y
OE
Y
POST OFFICE BOX 655303
MAX
MIN
MAX
1.2 V ± 0.1 V
0.4
10.7
21.1
0.7
29.8
1.5 V ± 0.1 V
2
7.2
12.6
1.1
18.5
1.8 V ± 0.15 V
2.3
5.8
9.5
1.5
14.5
2.5 V ± 0.2 V
2.5
4.4
6.3
1.7
10.5
3.3 V ± 0.3 V
2.3
3.7
5.2
1.5
8.4
1.2 V ± 0.1 V
1.4
12.1
22.8
0.8
29.3
1.5 V ± 0.1 V
2.8
8
13.3
2
18.7
1.8 V ± 0.15 V
2.5
6.2
10
1.6
14.8
2.5 V ± 0.2 V
2.5
4.5
6.7
1.6
9.9
3.3 V ± 0.3 V
2.3
3.8
5.4
1.5
8.2
ns
ns
0
1.2 V ± 0.1 V
2
5.6
9.3
2
10
1.5 V ± 0.1 V
2.5
4.1
5.8
2.4
7.6
1.8 V ± 0.15 V
2.9
4.2
5.7
2.7
7.9
2.5 V ± 0.2 V
1.1
2.7
4.4
1.1
5.5
3.3 V ± 0.3 V
1.9
3.5
5.2
1.9
5.8
• DALLAS, TEXAS 75265
UNIT
0
0.8 V
tdis
TYP
36
0.8 V
ten
TA = −40°C
TO 85°C
TA = 25°C
VCC
ns
11
SCES594A – JULY 2004 − REVISED OCTOBER 2004
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figures 3 and 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
tpd
A, B, C, or D
Y
OE
Y
12
OE
Y
POST OFFICE BOX 655303
UNIT
MAX
MIN
MAX
1.2 V ± 0.1 V
0.9
11.4
22
0.5
30.8
1.5 V ± 0.1 V
2.5
7.8
13.2
1.6
19.2
1.8 V ± 0.15 V
2.7
6.3
10
1.9
15.1
2.5 V ± 0.2 V
2.8
4.7
6.6
2
10.8
3.3 V ± 0.3 V
2.6
4
5.5
1.8
8.8
1.8
13
24.2
1.3
30.6
1.5 V ± 0.1 V
3.2
8.6
14.1
2.4
19.5
1.8 V ± 0.15 V
2.9
6.7
10.6
2
15.4
2.5 V ± 0.2 V
2.8
4.9
7
1.9
10.3
3.3 V ± 0.3 V
2.6
4.1
5.7
1.8
8.6
10.7
ns
13
1.2 V ± 0.1 V
2.7
6.3
9.9
2.8
1.5 V ± 0.1 V
3.2
4.6
6.1
3.1
8
1.8 V ± 0.15 V
3.2
4.8
6.6
3
8.8
2.5 V ± 0.2 V
2.2
3.4
4.7
2
6
3.3 V ± 0.3 V
2.4
4.4
6.5
2.3
7.2
• DALLAS, TEXAS 75265
ns
44
1.2 V ± 0.1 V
0.8 V
tdis
TYP
38
0.8 V
ten
TA = −40°C
TO 85°C
TA = 25°C
VCC
ns
SCES594A – JULY 2004 − REVISED OCTOBER 2004
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figures 3 and 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
tpd
Y
A, B, C, or D
Y
OE
OE
Y
MAX
MIN
MAX
1.2 V ± 0.1 V
3.1
14
24.9
2.6
36.1
1.5 V ± 0.1 V
4.2
9.6
15.1
3.3
23.1
1.8 V ± 0.15 V
4.1
7.9
11.7
3.3
18
2.5 V ± 0.2 V
4.1
5.9
7.9
3.1
12.7
3.3 V ± 0.3 V
3.7
5.1
6.7
2.8
10.4
UNIT
ns
50
1.2 V ± 0.1 V
4.4
16
27.6
3.9
36.8
1.5 V ± 0.1 V
5.3
10.7
16.2
4.3
23.6
1.8 V ± 0.15 V
4.6
8.5
12.4
3.6
18.6
2.5 V ± 0.2 V
4.2
6.3
8.5
3.2
12.6
3.3 V ± 0.3 V
3.8
5.4
7.1
2.9
10.2
6
14.6
0.8 V
tdis
TYP
48
0.8 V
ten
TA = −40°C
TO 85°C
TA = 25°C
VCC
ns
19
1.2 V ± 0.1 V
6
10.1
14.2
1.5 V ± 0.1 V
5.1
7.4
10.6
5
10.1
1.8 V ± 0.15 V
5.5
8.6
11.6
5.5
12.1
2.5 V ± 0.2 V
3.3
5.9
8.3
3.3
8.9
3.3 V ± 0.3 V
6
8.7
10.9
5.9
11.8
ns
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
Power dissipation capacitance
f = 10 MHz
Outputs disabled
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC
0.8 V
TYP
1.2 V ± 0.1 V
4
1.5 V ± 0.1 V
4
1.8 V ± 0.15 V
4
2.5 V ± 0.2 V
5
3.3 V ± 0.3 V
5
0.8 V
UNIT
4
0
1.2 V ± 0.1 V
0
1.5 V ± 0.1 V
0
1.8 V ± 0.15 V
0
2.5 V ± 0.2 V
0
3.3 V ± 0.3 V
0
pF
13
SCES594A – JULY 2004 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
VCC
Timing Input
0V
tPLH
tPHL
tsu
VOH
Output
VCC/2
VM
th
VCC
VM
VOL
Data Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, for propagation delays
tr/tf = 3 ns, for setup and hold times and pulse width tr/tf = 1.2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. tPLH and tPHL are the same as tpd.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES594A – JULY 2004 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 × VCC
5 kΩ
From Output
Under Test
CL
(see Note A)
S1
GND
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUP1G99DCTR
ACTIVE
SM8
DCT
8
3000
None
CU SNPB
Level-1-235C-UNLIM
SN74AUP1G99DCTT
ACTIVE
SM8
DCT
8
250
None
CU SNPB
Level-1-235C-UNLIM
SN74AUP1G99DCUR
ACTIVE
US8
DCU
8
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G99DCUT
ACTIVE
US8
DCU
8
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2005, Texas Instruments Incorporated